JP2001345432A - Solid electronic device provided with dielectric capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the oixdation resistance of a dielectric capacitor to electrodes without impeding the enhancement of the integration degree of a solid electronic device in the solid electronic device provided with the dielectric capacitor. SOLUTION: A solid electronic device is constituted in a structure that a metal nitride layer 3 constituting an embedded conductor 2 is provided on the surface of the embedded conductor 2 embedded in an insulating layer 1 and at the same time, a dielectric capacitor 5 is provided on the layer 3 via an intermediate layer 4, which consists of a conductive oxide layer, such as an IrO2 layer or an RuO2 layer, and has an oxygen barrier resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state electronic device having a dielectric capacitor, and more particularly, to a dielectric capacitor characterized by a connection structure between a lower electrode of an information storage capacitor and a plug of a semiconductor memory device. And a solid-state electronic device having the same.

[0002]

2. Description of the Related Art Conventionally, DR for recording various kinds of information has been used.
AM (dynamic random access memory),
SRAM (static random access memory), FLASH (flash memory), or ferroelectric memory (FeRAM: Ferroelectric)
Semiconductor storage devices such as cRAM) are used.

In such a semiconductor memory device, a lower electrode is connected to a buried conductor called a plug connected to a source region of a MOSFET serving as a switching element in order to improve the degree of integration and to form an element at a high density. Usually, a capacitor is formed as follows.

In recent years, the area of the dielectric layer constituting the capacitor has been reduced with the further improvement of the degree of integration and miniaturization of the element. As a layer, a material having a higher dielectric constant is required, and as described above, a ferroelectric memory using a ferroelectric as the dielectric layer has been put to practical use.

[0005] A dielectric having such high dielectric constant characteristics,
In particular, ferroelectrics are often oxides of multiple metal elements, and to form such metal oxides,
A high temperature oxidation process is required. For example, as a ferroelectric material, PZT (PbZr _x Ti _1-x O ₃ ) or PZT
A perovskite oxide containing Pb such as LZT (La-doped PZT) or a Bi-based layered perovskite oxide such as SBT is used, and is used as a metal oxide by a sputtering method, a sol-gel (Sol-Gel) method, or the like. After the film is formed, a heat treatment is performed in an oxidizing atmosphere to form a perovskite structure to increase the dielectric constant.

In order to form such a ferroelectric capacitor in a highly integrated semiconductor memory device, it is necessary to form a capacitor structure on the plug as described above. Since it is formed of a conductor whose resistance increases due to oxidation of W or the like, it is necessary to take measures for preventing the upper surface of the plug from being oxidized in the above-described high-temperature oxidation process.

Therefore, an oxygen barrier layer which is conductive and does not transmit oxygen is inserted between the plug and the capacitor. However, in order to form a capacitor, not only the oxygen barrier property but also the adhesion between the layers becomes important. Therefore, conventionally, an intermediate layer such as TiN is provided between the plug and the oxygen barrier layer. Is provided to enhance the adhesion.

Here, a conventional ferroelectric capacitor will be described with reference to FIG. FIG. 5A is a schematic cross-sectional view showing an electrode structure of a ferroelectric capacitor constituting a conventional FeRAM.
Illustration of the FET and the like is omitted. First, while forming a p-type well region in a predetermined region of an n-type silicon substrate,
After an element isolation oxide film is formed by selectively oxidizing the silicon substrate, a gate electrode made of WSi is formed in the element formation region via a gate insulating film, and ions such as As are implanted using the gate electrode as a mask. By doing so, an n ^- type LDD (Lightly Doped Dra
in) regions (both not shown) are formed.

Next, an SiO ₂ film or the like is deposited on the entire surface,
After forming a sidewall by performing anisotropic etching, ion implantation of As or the like is performed again to form an n ⁺ -type source / drain region.
EOS (Tetra-Ethyl-Ortho-Sil)
icate) After forming an interlayer insulating film 31 made of a thick SiO ₂ film or the like such as a -NSG film, a via hole reaching an n ⁺ type source / drain region is formed, and the via hole is filled with W to form a W plug 32. I do. In the figure, the W plug 32 connected to the n ⁺ type source region is shown.

Next, Ti is deposited by sputtering.
An N intermediate layer 33, an Ir-oxygen barrier layer 34, and a Pt lower electrode 35 are sequentially deposited, and then an amorphous sputtered PZT film is deposited again by a sputtering method. Heat treatment for 30 to 60 minutes in an atmosphere of atmospheric pressure oxygen
By crystallizing the film as a perovskite oxide, a PZT dielectric layer 36 is crystallized.

Next, Pt is again deposited on the PZT dielectric layer 36 by a sputtering method to form a Pt upper electrode 37, and then the Pt upper electrode 37 is formed in an oxygen atmosphere at atmospheric pressure.
Heat treatment at 0-650 ° C for about 30 minutes
The dielectric layer 36 recovers from the damage.

Next, after the Pt upper electrode 37 to the TiN intermediate layer 33 are patterned by etching, the Pt upper electrode 37 to the TiN intermediate layer 33 are heated at 500 to 650 ° C. for 30 to 60 ° C. in an oxygen atmosphere at atmospheric pressure.
The ferroelectric capacitor connected to the W plug 32 is formed by performing a heat treatment for about a minute to recover the damage caused by the etching. Thereafter, the basic configuration of the ferroelectric memory is completed by forming a normal multilayer wiring structure.

Referring to FIG. 5B, however, the TiN intermediate layer 33 for improving the adhesion is
Due to low oxidation resistance, there is a problem that oxidation proceeds from an exposed side surface in an annealing step in an oxidizing atmosphere after etching. If the heating temperature is low and the heating time is short, this is shown in the figure. As described above, the Ti oxide layer 38 is kept at a short distance from the side surface, but there is a problem that the adhesion is deteriorated in the region where the Ti oxide layer 38 is formed.

Referring to FIG. 5C, when the heating temperature is high and the heating time is long, the oxidation proceeds to the center as shown in the figure. And the upper portion of the W plug 32 is oxidized to form the W oxide layer 39. In this case, together with the deterioration of the adhesion,
An electrical obstruction problem occurs.

Therefore, a means for preventing such oxidation of the TiN intermediate layer 33 and the like has been proposed, and will be described with reference to FIG. FIG. 6 is an explanatory view of an improved electrode structure of a conventional ferroelectric capacitor. First, a TiN intermediate layer 33 and Ir with respect to oxygen are covered by a sputtering method so as to cover an interlayer insulating film 31 and a W plug 32. After depositing the barrier layer 34, the TiN intermediate layers 33 and I are patterned by patterning into an area larger than the conventional area, then depositing a SiN film having excellent oxidation resistance over the entire surface and then performing anisotropic etching.
A sidewall 40 made of a SiN film is formed on the side surface of the r-oxygen barrier layer 34.

Thereafter, the Pt lower electrode 35, the PZT dielectric layer 36, and the Pt upper electrode 37 are sequentially formed by the process described with reference to FIG. 5A, and then the Pt upper electrode 37 to the Pt lower electrode 35 are formed. By patterning, a ferroelectric capacitor connected to the W plug 32 is formed.

With such a structure, T having poor oxidation resistance is used.
Since the exposed side surface of the iN intermediate layer 33 is covered with the sidewall 40 made of a SiN film having excellent oxidation resistance, there is no problem of oxidation in the heat treatment step for recovering damage after the etching step.

[0018]

However, in the electrode structure shown in FIG. 6, the characteristics of the ferroelectric capacitor are determined by the pattern shapes of the Pt upper electrode 37 to the Pt lower electrode 35. To maintain the pattern shape of the lower electrode 37 to the Pt lower electrode 35 to a certain size, P
Since it is necessary to make the pattern shapes of the t upper electrode 37 to the Pt lower electrode 35 larger than that, there is a problem that the capacitor area becomes larger than in the case of FIG.

Therefore, an object of the present invention is to increase the oxidation resistance of the electrodes of a capacitor without hindering the improvement of the degree of integration.

[0020]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. Referring to FIG. 1, in order to achieve the above-mentioned object, in the present invention, a buried conductor 2 embedded in an insulating layer 1, in particular, a buried conductor 2 Is provided, and IrO _{2 is formed} on the nitride layer 3.
Alternatively, a dielectric capacitor 5 is provided via an intermediate layer 4 made of a conductive oxide such as RuO ₂ and having an oxygen barrier property.

As described above, by providing the metal nitride layer 3 constituting the buried conductor 2 on the surface of the buried conductor 2, the surface of the buried conductor 2 is oxidized to increase the resistance. Nothing. Further, since the intermediate layer 4 made of a conductive oxide and having an oxygen barrier property is interposed, the intermediate layer 4 having an oxygen barrier property is not further oxidized, and
Since the intermediate layer 4 having oxygen barrier properties suppresses transmission of oxygen, the metal nitride layer 3 is not oxidized.

Further, the present invention is characterized in that as the lower electrode 6 or the upper electrode 8 constituting the dielectric capacitor 5, a conductor structure that improves the characteristics of the dielectric capacitor 5 is used. For example, by using an electrode having a three-layer structure of a metal layer / a conductive oxide layer / a metal layer as the upper electrode 8, the characteristics of the dielectric capacitor 5 can be improved.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a first embodiment of the present invention will be described with reference to FIGS. Note that FIG.
3 is a schematic cross-sectional view near a ferroelectric capacitor. Referring to FIG. 2A, a MOSFET (not shown) is formed in a predetermined region of a silicon substrate in a process similar to a conventional process of manufacturing a FeRAM, and a via hole reaching an n ⁺ type source region is formed in an interlayer insulating film 11. Then, after filling this via hole with W, the W film deposited on the area other than the via hole is removed by the CMP method to form a W plug 12, and then, the surface of the W plug 12 is formed by etching. By removing, a concave portion 13 having a depth of 1 to 100 nm, for example, 50 nm is formed.

Next, as shown in FIG. 2B, the recess 13 is filled with a WN layer by sputtering W in an atmosphere containing N _2, and then the surface of the W plug 12 is covered by performing the CMP method again. The recess 13 is buried by providing the WN layer 14 as described above.

Next, as shown in FIG. 2C, an IrO ₂ intermediate layer 15 having a thickness of 1 to 100 nm, for example, 50 nm is deposited on the entire surface by sputtering Ir in an O ₂ atmosphere.

Referring to FIG. 3D, a Pt layer 17 having a thickness of, for example, 200 nm is deposited again by the sputtering method.
_1.1 with a disc of Zr _0.53 Ti _0.47 O ₃ composition as a target, the flow rate ratio of Ar and O ₂ is Ar: O ₂ = 8: 2 as process gas while a 0.02Torr flowing,
At room temperature by applying 50 W of RF power, the film thickness becomes 2
A PZT film having a thickness of 00 to 400 nm is formed. This sputtered PZT film is in an amorphous state when formed.

Next, for example, by performing a heat treatment for 30 minutes in an oxygen atmosphere at 650 ° C. and atmospheric pressure,
The sputtered PZT film is crystallized as a perovskite oxide to form a crystallized PZT layer 18.

Next, on the PZT layer 18 crystallized again by the sputtering method, a thickness of, for example, 200 n
m Pt layer 19, and then heat-treated for 30 minutes in an atmospheric oxygen atmosphere at 500 ° C.
In the step of depositing the t-layer 19, the damage caused to the PZT layer 18 is recovered.

Next, as shown in FIG. 3E, the upper electrode 19 is subjected to reactive ion etching using an etch gas composed of Ar and Cl _2.
After the IrO ₂ intermediate layer 15 is etched to a predetermined area, a heat treatment is performed for 30 minutes in an atmospheric oxygen atmosphere at 500 ° C., for example, to recover the damage caused by the etching process, and thereby the Pt upper electrode 2
3 / PZT dielectric layer 22 / Pt lower electrode 21 / Ir with respect to oxygen barrier layer 20 constitutes a ferroelectric capacitor having a desired capacitance. Thereafter, the basic configuration of the FeRAM is completed by performing a normal multilayer wiring process.

As described above, according to the first embodiment of the present invention, the surface of the W plug 12 is covered with the WN layer 14 and has excellent oxygen barrier properties and is a conductive oxide of IrO. ₍₂ ) Since the ferroelectric capacitor is provided with the intermediate layer 15 interposed therebetween, in the heat treatment step in an oxidizing atmosphere for recovering the damage caused by the etching step, Ir
The O ₂ intermediate layer 15 is not oxidized and deteriorated.

Further, like a conventional dielectric capacitor,
Since it is not necessary to form the intermediate layer and the oxygen barrier layer in an area larger than the main body of the dielectric capacitor, the degree of integration is not deteriorated. Further, since the IrO ₂ intermediate layer 15 does not transmit oxygen, even if a sidewall is not formed, oxygen does not enter into the inside and the WN layer 14 is not oxidized, and even if oxygen enters, Since the WN layer 14 has a certain degree of oxidation resistance, the resistance of the W plug 12 does not increase due to oxidation. Note that IrO ₂ has better adhesion than the conventional TiN intermediate layer, so that adhesion does not matter.

Next, a second embodiment of the present invention will be described with reference to FIG. 4, except that the process of forming the WN layer is different, and the other manufacturing steps are the same as those of the above-described first embodiment. The description is simplified because it is the same. First, as in the first embodiment, a MOSFET (not shown) is formed in a predetermined region of a silicon substrate, and a via hole reaching an n ⁺ -type source region is formed in an interlayer insulating film 11 as in the first embodiment. After filling the via hole with W, the W film deposited on the area other than the via hole is removed by the CMP method to form the W plug 12, and then the surface of the W plug 12 is etched. To a depth of 1 to 100 nm, for example, 50 n
The m concave portions 13 are formed.

Next, referring to FIG. 4B, the surface of the W plug 12 is nitrided by performing a plasma treatment in an N plasma atmosphere 24 to form the WN layer 14 and fill the recess 13. In this case, the depth of the recess 13 is set in advance according to the thickness of the WN layer 14 to be formed, so that the surface after the formation of the WN layer 14 is substantially flat.

Referring to FIG. 4 (c), the same steps as those shown in FIGS. 2 (c) to 3 (e) are performed to obtain the Pt upper electrode 23 / PZT dielectric layer 22 / Pt lower electrode 21 / An FeRAM having a ferroelectric capacitor composed of Ir versus the oxygen barrier layer 20 is obtained.

As described above, in the second embodiment of the present invention, the WN layer 14 serving as an oxidation-resistant film is formed by plasma processing in N plasma, so that W
Since the N layer is not formed, it is not necessary to remove the unnecessary WN layer by the CMP process as in the first embodiment.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in the embodiments, and various changes can be made. For example, although using an intermediate layer IrO _2, it is not limited to IrO _2, a conductive oxide in the same manner as IrO ₂ R
uO ₂ may be used, and further, IrO ₂
Or RuO ₂ , or (Ir, Ru) O ₂
It may be used as a film.

In each of the above embodiments, the lower electrode has a two-layer structure of an Ir layer and a Pt layer serving as an oxygen barrier layer. However, the lower electrode is limited to such a two-layer structure. But not Ir, IrO ₂ , Ru, RuO ₂ , Pt,
Alternatively, it may be constituted by a single layer structure of PtO ₂ or a multilayer structure obtained by combining these. In the case of a single layer structure, the lower electrode also serves as an oxygen barrier layer.

In each of the above embodiments, PZT is used as the ferroelectric film. However, the present invention is not limited to PZT, but is also applicable to perovskite oxides containing Pb, such as PZ, PT, and PLZT. Things.

In the description of each of the above embodiments, the PZT layer is formed by the sputtering method, but the PZT layer formed by the sol-gel method or the MOCVD method is used.
Layers may be used.

In addition to the perovskite oxide containing Pb, the following general formula (Bi ₂ O ₂ ) ²⁺ (A _n-1 B _n O _{3n + 1} ) ^2- such as SBT, where A = Bi, Pb, Ba, Sr, Ca, Na, B = Ti, Ta, Nb, W, Mo, Fe, Co, Cr, Bi-based layered perovskite oxide represented by n = 1 to 5, BST
Ba, Sr, and Ti oxides may be used.

Further, the dielectric layer constituting the dielectric capacitor is not limited to the ferroelectric layer, but may be SiO ₂ , S
Ordinary dielectrics such as i ₃ N ₄ or SiON may be used, and further, Ta ₂ O ₅ or Al ₂
A high dielectric material such as O ₃ may be used.

In each of the above embodiments, the upper electrode is constituted by a single-layer Pt upper electrode.
It is not limited to the upper electrode, and a single element metal made of Ir or Ru may be used.
An alloy between r and Ru may be used.

The upper electrode need not be a single layer,
From the dielectric layer side, a conductive oxide layer / metal layer or a multilayer structure film such as a metal layer / conductive oxide layer / metal layer may be used. In this case, the conductive oxide layer may be used. Is I
rO ₂ or RuO ₂ may be used, and the metal layer is a single element metal of Ru, Pt, or Ir, or P
An alloy between t, Ir, and Ru may be used, whereby superior ferroelectric capacitor characteristics can be obtained as compared with the case where an upper electrode made of a single-layer metal is used.

In the second embodiment, the surface of the W plug is nitrided in N plasma to form the WN layer. However, the present invention is not limited to such a plasma nitriding method. Heat treatment in an ammonia atmosphere
The surface of the plug may be nitrided.

In the second embodiment, the concave portion is formed in advance so that the surface after providing the WN layer is flat. However, it is not always necessary to form the concave portion. The WN layer formed by nitriding is formed as a projection, but the IrO ₂ intermediate layer may be formed so as to cover the entire protruding WN layer.

In the description of each of the above embodiments, the information storage capacitor of the semiconductor memory device has been described. However, the present invention is not limited to such a capacitor for a semiconductor memory device. The present invention is also applicable to a normal semiconductor integrated circuit device using a body capacitor or a high-dielectric capacitor as a small capacitor having a large capacity, or a capacitor of another electronic device.

In each of the above embodiments, when forming the ferroelectric capacitor, the lower electrode, the ferroelectric film, and the upper electrode are deposited on the entire surface and then etched into a predetermined shape. Patterning, but is not limited to such a process, using a mask sputtering method, a lower electrode, a ferroelectric film, and
The upper electrode may be selectively deposited sequentially in a predetermined shape. When such a selective deposition process is used, the oxidation accompanying the crystallization process of the ferroelectric or the recovery process of the damage may cause a problem. Never be.

Here, with reference to FIG. 1 again, additional notes of the present invention will be described. See FIG. 1 (Supplementary Note 1) In a solid-state electronic device including a dielectric capacitor 5 connected to a buried conductor 2 embedded in an insulating layer 1, a surface of the buried conductor 2 is provided on the surface of the buried conductor 2. 2, and a dielectric capacitor 5 is provided on the nitride layer 3 via an intermediate layer 4 made of a conductive oxide and having an oxygen barrier property. Solid state electronic device provided with a dielectric capacitor. (Supplementary Note 2) The solid-state electronic device provided with the dielectric capacitor according to Supplementary Note 1, wherein the two buried conductors are made of tungsten. (Supplementary note 3) The dielectric capacitor according to Supplementary note 1 or 2, wherein the intermediate layer 4 made of the conductive oxide and having an oxygen barrier property is made of at least one of iridium oxide and ruthenium oxide. Equipped solid state electronic device. (Supplementary Note 4) The upper electrode 8 of the dielectric capacitor 5 is
A solid-state electronic device comprising the dielectric capacitor according to any one of supplementary notes 1 to 3, further comprising a metal layer. (Supplementary Note 5) The upper electrode 8 of the dielectric capacitor 5 is
4. A solid-state electronic device comprising the dielectric capacitor according to any one of supplementary notes 1 to 3, wherein the solid-state electronic device has a multilayer structure including at least a conductive oxide layer and a metal layer. (Supplementary Note 6) The upper electrode 8 of the dielectric capacitor 5 is
The dielectric capacitor according to claim 5, wherein the dielectric capacitor has any one of a conductive oxide layer / metal layer and a multilayer structure including a metal layer / conductive oxide layer / metal layer from the dielectric layer 7 side. Equipped solid state electronic device. (Supplementary note 7) The solid-state electronic device provided with the dielectric capacitor according to supplementary note 6, wherein the conductive oxide layer forming a part of the upper electrode 8 is made of at least one of iridium oxide and ruthenium oxide. apparatus. (Supplementary Note 8) The dielectric according to any one of Supplementary Notes 4 to 7, wherein a metal layer forming the upper electrode 8 of the dielectric capacitor 5 is made of any one of Ir, Ru, and Pt. Solid-state electronic device with a capacitor. (Supplementary Note 9) The lower electrode 6 of the dielectric capacitor 5 is
Ir layer, Ir oxide layer, Ru layer, Ru oxide layer, Pt
A solid-state electronic device comprising the dielectric capacitor according to any one of supplementary notes 1 to 8, comprising at least one of a layer and a Pt oxide layer. (Supplementary Note 10) Dielectric Layer 7 of Dielectric Capacitor 5
Are Si oxides, Si oxynitrides, Si nitrides, Ta oxides, Al oxides, oxides mainly composed of Pb, Zr, Ti, oxides mainly composed of Sr, Bi, Ta, or 10. A solid-state electronic device comprising the dielectric capacitor according to any one of supplementary notes 1 to 9, wherein the solid-state electronic device includes at least one of oxides made of Ba, Sr, and Ti.

[0049]

According to the present invention, a metal nitride constituting a plug is provided on the surface of a plug such as W,
Since the dielectric capacitor is provided via the conductive oxide intermediate layer having an oxygen barrier property such as O ₂ , the intermediate layer is not oxidized in the oxidation heat treatment step during the process, and the adhesion is not deteriorated. Also, the electrical resistance does not increase due to the oxidation of the plug, thereby preventing the deterioration of the ferroelectric capacitor or the high dielectric capacitor, and increasing the integration and performance of the semiconductor memory device. High reliability can be achieved, and this greatly contributes to the realization of a logic circuit mixed FeRAM.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of an electrode structure of a conventional ferroelectric capacitor.

FIG. 6 is an explanatory diagram of an improved electrode structure of a conventional ferroelectric capacitor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 insulating layer 2 buried conductor 3 nitride layer 4 intermediate layer 5 dielectric capacitor 6 lower electrode 7 dielectric layer 8 upper electrode 11 interlayer insulating film 12 W plug 13 recess 14 WN layer 15 IrO ₂ intermediate layer 16 Ir layer 17 Pt layer 18 PZT layer 19 Pt layer 20 Ir to oxygen barrier layer 21 Pt lower electrode 22 PZT dielectric layer 23 Pt upper electrode 24 N plasma atmosphere 31 Interlayer insulating film 32 W plug 33 TiN intermediate layer 34 Ir to oxygen barrier layer 35 Pt Lower electrode 36 PZT dielectric layer 37 Pt upper electrode 38 Ti oxide layer 39 W oxide layer 40 Side wall

Claims (5)

[Claims] 1. A solid-state electronic device comprising a dielectric capacitor connected to a buried conductor embedded in an insulating layer, wherein a surface of the buried conductor has a surface on which the metal constituting the buried conductor is nitrided. A solid-state electronic device comprising a dielectric capacitor and a dielectric capacitor provided on the nitride layer via an intermediate layer made of a conductive oxide and having an oxygen barrier property. 2. The solid-state electronic device having a dielectric capacitor according to claim 1, wherein said buried conductor layer is made of tungsten. 3. The dielectric capacitor according to claim 1, wherein the intermediate layer made of the conductive oxide and having an oxygen barrier property is made of at least one of iridium oxide and ruthenium oxide. A solid-state electronic device provided with. 4. The solid-state electronic device comprising a dielectric capacitor according to claim 1, wherein the upper electrode of the dielectric capacitor includes a metal layer. 5. The dielectric capacitor according to claim 1, wherein the upper electrode of the dielectric capacitor has a multilayer structure including at least a conductive oxide layer and a metal layer. A solid-state electronic device provided with.