JPH10242410A - Semiconductor memory cell and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory cell that has a planar stack type capacitor structure, can increase the area of a ferroelectric thin film, and can increase the amount of accumulated electric charge. SOLUTION: A semiconductor memory cell comprises a planar first capacitor, a MOS-type transistor element provided at the upper part of the first capacitor via a first interlayer insulation layer 12, and a planar second capacitor provided at the upper part of the MOS-type transistor element via a second interlayer insulation layer 40. In this case, each of first and second capacitors comprises lower electrodes 21 and 51, capacitor insulating films 22 and 52 consisting of a ferroelectric thin film, and upper electrodes 23 and 53 (a), and each of the lower electrodes 21 and 51 is connected to one source/drain region 34A of the MOS-type transistor element via first and second contact plugs 14 and 42 provided at the first and the second interlayer insulation layers 12 and 40 (b).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell using a ferroelectric thin film based on a so-called bonding SOI technique and a method of manufacturing the same. FERAM) or D
The present invention relates to a semiconductor memory cell including a RAM and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the progress of film forming technology, application studies of nonvolatile memories using ferroelectric thin films have been actively pursued. This non-volatile memory is a non-volatile memory capable of high-speed rewriting, utilizing high-speed polarization inversion of a ferroelectric thin film and its remanent polarization. Non-volatile memories provided with ferroelectric thin films that are currently being studied are of two types: a method that detects a change in the amount of charge stored in a ferroelectric capacitor and a method that detects a change in the resistance of a semiconductor due to spontaneous polarization of the ferroelectric. Can be classified into one. The semiconductor memory cell in the present invention belongs to the former.

A non-volatile semiconductor memory cell of the type that detects a change in the amount of charge stored in a ferroelectric capacitor basically has a capacitor structure and a selection transistor element. The capacitor structure includes, for example, a lower electrode and an upper electrode, and a capacitor insulating film formed of a ferroelectric thin film sandwiched therebetween. Writing and reading of data in this type of non-volatile memory cell is performed by applying a ferroelectric PE hysteresis loop shown in FIG. When an external electric field is applied to the ferroelectric thin film and then the external electric field is removed, the ferroelectric thin film exhibits spontaneous polarization. Then, the residual polarization of the ferroelectric thin film is a -P _r when when positive direction of the external electric field is applied + P _r, the negative direction of the external electric field is applied. Here, the case where the remanent polarization is + P _r (see “D” in FIG. 14) is “0”, and the state where the remanent polarization is −P _r (“A” in FIG. 14).
Is set to “1”.

In order to determine the state of “1” or “0”, for example, an external positive electric field is applied to the ferroelectric thin film. Thus, the polarization of the ferroelectric thin film is in the state of “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric thin film changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric thin film changes from “A” to “C” via “B”. If the data is "0",
No polarization inversion of the ferroelectric thin film occurs. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric thin film.
As a result, there is a difference in the amount of mobile charge corresponding to the difference in the amount of stored charge (polarization state) of the capacitor structure. By turning on the selection transistor element of the selected memory cell, this accumulated charge is detected as a bit line potential. If the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric thin film becomes the state of "D" in FIG. 14 regardless of whether the data is "0" or "1". Therefore, when the data is “1”, an external electric field in the negative direction is applied to change the state to “A” along the paths “D” and “E”, and the data “1” is written.

A nonvolatile semiconductor memory is shown in FIG.
As shown in a schematic layout diagram of FIG. 15 and a schematic partial cross-sectional view of FIG. 15B, having a so-called planar-stack type capacitor structure is advantageous in terms of a semiconductor memory manufacturing process. This is desirable from the viewpoint of increasing the effective area of the dielectric thin film. Incidentally, FIG.
FIG. 3A is a partial cross-sectional view along line BB of FIG. In a semiconductor memory having such a structure, when the minimum etching processing dimension (line width) is F and, for example, the size of one semiconductor memory cell is 4.8F × 2.4F (= 12F ² ), the planar shape is rectangular. The size of the ferroelectric thin film of 3.8
It may be F × 1.4F. In addition, the interval between adjacent semiconductor memory cells may be set to 1F.

However, in order to manufacture a non-volatile semiconductor memory of 1 gigabit level, in order to increase the area of the ferroelectric thin film and increase the residual polarization charge, a so-called DRAM, which is employed in a DRAM, is required. It is said that a pedestal capacitor structure must be employed. A DRAM having a pedestal-type capacitor structure using a high dielectric thin film (for example, SrTiO ₃ ) similar to a ferroelectric thin film used for a nonvolatile semiconductor memory
However, for example, the document "A Gbit-scale DRAM stacked capaci
tor technology with ECR MOCVD SrTiO ₃ and RIE patte
rned RuO ₂ / TiNstorage nodes ", PY Lesaicherre, et a
l., IEDM 94-841, 34.1.1. FIG. 16 shows a schematic partial cross-sectional view of the DRAM disclosed in this document.
In the cell, the lower electrode made of RuO ₂ is RIE
It has a columnar shape patterned by a method. By making the lower electrode into a columnar shape, the area of the high dielectric thin film covering the lower electrode can be increased.

[0007]

When a semiconductor memory using a ferroelectric thin film is manufactured, it is necessary to increase the thickness of the ferroelectric thin film. 1 Gigabit DRAM
The thickness of the high dielectric thin film may be 50 nm or less,
In a nonvolatile semiconductor memory cell, the ferroelectric thin film needs to have a thickness of about 120 nm or more. FIG. 17 is a schematic layout diagram of a semiconductor memory having a pedestal capacitor structure. FIG. 18 is a schematic partial cross-sectional view. 18A and 18B are partial cross-sectional views taken along lines AA and BB in FIG. In the semiconductor memory having the pedestal type capacitor structure, as shown in FIG. 18B, a ferroelectric thin film and an upper electrode are disposed between lower electrodes adjacent to each other along a line BB in FIG. Is difficult to embed, and the size (length) of the capacitor structure along the line BB in FIG. 17A needs to be increased by about 0.4F. Also, as shown in FIG.
17A, it becomes difficult to secure a margin associated with processing of the upper electrode and the ferroelectric thin film adjacent to each other along the line AA of FIG. It is necessary to increase the size (length) of the capacitor structure by about 0.8F. The design rule is 0.18 μm (= F), and the size of one semiconductor memory cell is 1.0 μm × 0.50 μm
(= 15.7 F ² ), the height of the pedestal type capacitor structure is 0.56 μm, and the thickness of the ferroelectric thin film is 120 n.
When m, 2P _r = 16 μC / cm ² , the size of the capacitor structure is about 0.34 μm ² . In the semiconductor memory cell having the pedestal capacitor structure, the area of the memory cell is (2.4 + 0.
4) × (4.8 + 0.8) = 15.7F ² , which is the size of the conventional semiconductor memory cell 12F ² (= 4.8F ×
In comparison with 2.4F), the area is increased by about 36%. That is, the superiority of the semiconductor memory having the pedestal capacitor structure to the semiconductor memory having the planar-stack capacitor structure is lost.

[0008] In a DRAM using a high dielectric thin film, the accumulated charge and the applied voltage have a linear relationship. On the other hand, in a semiconductor memory cell using a ferroelectric thin film, as shown in FIG. 14, the accumulated charge and the applied voltage have a non-linear relationship, and have a hysteresis characteristic. And
The characteristics of the ferroelectric thin film are sensitive to the surface condition of the lower electrode. When the technique disclosed in the above document is applied to a semiconductor memory using a ferroelectric thin film, that is, when a ferroelectric thin film is formed on a lower electrode having a columnar shape patterned by RIE. The surface of such a lower electrode is usually damaged and rough, and has poor surface morphology.
As a result, the characteristics of the ferroelectric thin film may be deteriorated. Furthermore, electric field concentration occurs at the corners of the columnar lower electrode, which may cause a difference between the characteristics of the ferroelectric thin film at the plane portion of the lower electrode and the characteristics of the ferroelectric thin film at the corners. For the above reasons, it is desirable to adopt a semiconductor memory having a planar-stack capacitor structure rather than a pedestal capacitor structure, if possible, even in a 1 gigabit level semiconductor memory.

Accordingly, an object of the present invention is to provide a semiconductor memory cell having a planar-stack type capacitor structure, capable of increasing the area of a ferroelectric thin film, and capable of increasing the amount of stored charges, and a method of manufacturing the same. Is to provide.

[0010]

In order to achieve the above object, a semiconductor memory cell according to the present invention has a so-called bonding S
It has an OI structure. That is, in the semiconductor memory cell of the present invention, a first capacitor portion having a plate shape and an MO provided above the first capacitor portion with a first interlayer insulating layer interposed therebetween.
An S-type transistor element; and a plate-shaped second capacitor section provided above the MOS transistor element with a second interlayer insulating layer interposed therebetween. (A) Each of the first and second capacitor sections Is composed of a lower electrode, a capacitor insulating film composed of a ferroelectric thin film, and an upper electrode.
The lower electrode constituting the first capacitor section is connected to the lower electrode through a first contact plug provided in the first interlayer insulating layer.
The third electrode is connected to one of the source / drain regions of the OS-type transistor element, and (c) the lower electrode constituting the second capacitor section is via a second contact plug provided in the second interlayer insulating layer. It is characterized in that it is connected to the one source / drain region of the MOS transistor element.

In the semiconductor memory cell according to the present invention, the first capacitor connected to the upper electrode forming the first capacitor portion is provided.
And a second plate line connected to an upper electrode constituting the second capacitor section,
Is preferably electrically connected to the second plate line. Further, the MOS transistor element is formed in a semiconductor layer, and the semiconductor memory cell is preferably supported by a support substrate located below the first plate line via an insulating material layer and a polycrystalline silicon layer. . Incidentally, the first plate line and the second plate line may be connected to one of the source / drain regions of the plate line selecting transistor element constituting the decoder. Alternatively, the first plate line and the second plate line
May be connected via a contact hole. Further, the first contact hole and the lower electrode forming the first capacitor portion may be integrally formed, or the second contact hole and the lower electrode forming the second capacitor portion may be integrally formed. You may.

In order to achieve the above object, a method of manufacturing a semiconductor memory cell according to the present invention comprises the steps of (a) forming a concave portion on a surface of a semiconductor substrate, and then forming a first interlayer insulating layer on the surface of the semiconductor substrate. Forming a first contact plug on the first interlayer insulating layer, and (b) forming a lower electrode connected to the first contact plug on the first interlayer insulating layer, and a ferroelectric substance. A step of forming a capacitor-like insulating film made of a thin film, and a plate-shaped first capacitor part made of an upper electrode; and (c) an insulating material layer on the first interlayer insulating layer including on the first capacitor part And a step of bonding a support substrate to the surface of the polycrystalline silicon layer after forming the polycrystalline silicon layer, and (d) polishing the semiconductor substrate from the back side of the semiconductor substrate to form a MOS transistor element. Half the board part Leaving a body layer and exposing a part of the first interlayer insulating layer; and (e) a MOS transistor element having one source / drain region connected to the first contact plug in the semiconductor layer. And (f) a first step including on the MOS transistor element.
Forming a second interlayer insulating layer on the second interlayer insulating layer, and then forming a second contact plug connected to the one source / drain region on the second interlayer insulating layer;
Forming a lower electrode connected to the second contact plug, a capacitor insulating film made of a ferroelectric thin film, and a flat second capacitor portion made of an upper electrode on the second interlayer insulating layer; It is characterized by comprising.

In the method of manufacturing a semiconductor memory cell according to the present invention, after the step (b), after forming the first insulating layer on the first interlayer insulating layer including on the first capacitor portion, Forming a first plate line connected to an upper electrode constituting the first capacitor section via a contact plug provided in the first insulating layer [step (b ′)]
Forming a second insulating layer on the second interlayer insulating layer including on the second capacitor section after the step (g), and forming an upper electrode and a second electrode on the second capacitor section. Forming a second plate line connected via a contact plug provided in the second insulating layer, and electrically connecting the first plate line and the second plate line. )], And in the step (c), it is preferable that the insulating material layer and the polycrystalline silicon layer are formed on the first insulating layer including on the first plate line.

In the method for manufacturing a semiconductor memory cell, after the first insulating layer is formed on the first interlayer insulating layer including on the first capacitor portion in the above step (b ′), A third contact plug for connection with a plate line selecting transistor element manufactured in a later step is formed in the first interlayer insulating layer and the first insulating layer, and then a first capacitor portion is formed. Connected to the upper electrode via a contact plug provided in the first insulating layer, and
Forming a first plate line connected to the third contact plug; polishing the semiconductor substrate from the back side of the semiconductor substrate in step (d) to form a MOS transistor element and a plate line selecting transistor element; A part of the semiconductor substrate to be left is left as a semiconductor layer, and a part of the first interlayer insulating layer is exposed. In step (e), one of the source / drain regions is added to the third layer in the semiconductor layer. Forming a plate line selecting transistor element connected to the contact plug, forming a second insulating layer on the second interlayer insulating layer including on the second capacitor portion in the step (h), Forming a fourth contact plug connected to the one source / drain region of the line selecting transistor element in the second interlayer insulating layer and the second insulating layer; A second plate line connected to the upper electrode constituting the capacitor portion via a contact plug provided in the second insulating layer and connected to the fourth contact plug may be formed. it can.
In the case where the upper electrode of the adjacent plurality of semiconductor memory cells are connected to one plate line, the upper electrode, via a plate line, for example (V _cc -V _ss) / 2
What is necessary is just to apply the fixed voltage of (V).

The order of film formation and patterning of the lower electrode layer, the ferroelectric thin film and the upper electrode layer for forming the first capacitor portion or the second capacitor portion is shown below. Is included in the method for manufacturing a semiconductor memory cell of the present invention. (A) Lower electrode layer, ferroelectric thin film and upper electrode layer are sequentially formed, and collective patterning of upper electrode layer, ferroelectric thin film and lower electrode layer is performed. (B) Lower electrode layer is formed and patterned. Deposition of a dielectric thin film and an upper electrode layer sequentially, and collective patterning of an upper electrode layer and a ferroelectric thin film. (C) Deposition and patterning of a lower electrode layer, deposition and patterning of a ferroelectric thin film, and an upper electrode. Layer formation and patterning

In the above embodiments (B) and (C), the upper electrode layer and the ferroelectric thin film are patterned so that one upper electrode and a capacitor insulating film are formed on one lower electrode. Alternatively, patterning may be performed so as to cover a plurality of lower electrodes. In the case of the former patterning, V _ss (V) or V _cc is applied to the upper electrode, for example.
(V) is applied. On the other hand, in the latter case the patterning, the upper electrode, a constant voltage is applied, for example, _{(V cc -V ss) / 2} (V).

Alternatively, simultaneously with forming the first contact plug in the first interlayer insulating layer, a lower electrode constituting the first capacitor section may be formed on the first interlayer insulating layer. At the same time as forming the second contact plug in the two interlayer insulating layers, a lower electrode constituting the second capacitor portion may be formed on the second interlayer insulating layer.

The ferroelectric thin film may be formed by, for example, a solution chemical growth method (sol-gel method or MOD method), a chemical vapor deposition method (including a metal organic chemical vapor deposition method), or a physical vapor deposition method. Method (evaporation method including laser ablation method and sputtering method)
Can be formed. The patterning of the ferroelectric thin film can be performed by, for example, the RIE method.

Examples of the ferroelectric thin film include a Bi-based layered structure perovskite type ferroelectric thin film. B
The i-type layered structure perovskite-type ferroelectric material belongs to a so-called nonstoichiometric compound, and has tolerance to a composition deviation at both sites of a metal element and an anion (O or the like) element. Also, it is not uncommon for the composition to exhibit optimal electrical characteristics at a position slightly deviating from the stoichiometric composition. The Bi-based layered structure perovskite-type ferroelectric material has, for example, the general formula (Bi ₂
O ₂ ) ²⁺ (A _m-1 B _m O _{3m + 1} ) ^2- . Here, “A” is Bi, Pb, Ba, Sr, Ca, N
represents one kind of metal selected from the group consisting of metals such as a, K, and Cd, and “B” represents Ti, Nb, Ta,
One type selected from the group consisting of W, Mo, Fe, Co, and Cr, or a combination of a plurality of types at an arbitrary ratio. M is an integer of 1 or more.

Alternatively, the Bi-based layered structure perovskite type ferroelectric thin film may be Bi _X (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d (1) (where 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) as a main crystal phase.
Note that “(Sr, Ca, Ba)” represents Sr, Ca, and Ba.
Means one element selected from the group consisting of Alternatively, the ferroelectric thin _{film, Bi X Sr Y Ta 2 O} d (2) ( where, 1.7 ≦ X ≦ 2.5,0.6 ≦ Y ≦ 1.2,
(8.0 ≦ d ≦ 10.0) as a main crystal phase. In these cases, it is more preferable that the crystal phase represented by the formula (1) or (2) be contained at 85% or more as a main crystal phase.
The ferroelectric thin film containing the crystal phase represented by the formula (1) or (2) as a main crystal phase includes Bi oxide,
Oxides of Ta and Nb, and composite oxides of Bi, Ta and Nb may be slightly contained. Here, if the composition of the ferroelectric thin film represented by the formula (1) is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb ₂ O ₉ ,
Bi ₂ BaTa ₂ O ₉ and Bi ₂ SrTaNbO ₉ can be exemplified. Alternatively, Bi ₄ SrTi ₄ O ₁₅ , Bi ₄ Ti ₃ O ₁₂ , Bi may be used as the ferroelectric thin film in the present invention.
_{Although 2} PbTa ₂ O _{9 and the} like can be exemplified, also in these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change.

Alternatively, as a material constituting the ferroelectric thin film, PbTiO ₃ , lead zirconate titanate [PZT, Pb (Zr _{1 -y} , Ti _y) , which is a solid solution of PbZrO ₃ and PbTiO ₃ having a perovskite structure, PZT compounds such as O ₃ (where 0 <y <1)], PLZT which is a metal oxide obtained by adding La to PZT, and PNZT which is a metal oxide obtained by adding Nb to PZT.

In the semiconductor memory cell or the method of manufacturing the same according to the present invention, the material constituting the lower electrode and / or the upper electrode is, for example, ruthenium oxide (Ru).
O _x ), iridium oxide (IrO _x ), Ru, Ru _x / R
laminated structure of u, Ir, the laminated structure of the IrO _X / Ir, P
t, Pd, Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La _0.5 Sr _0.5 Co
O ₃ (LSCO), Pt / LSCO laminated structure, YBa ₂
It can be made of Cu ₃ O ₇ , and among them, ruthenium oxide (RuO _x ) or iridium oxide (IrO _x ) is preferable. In the laminated structure, "/"
The material described before constitutes the ferroelectric thin film side,
The material described after "/" constitutes the plate line side. The lower electrode and / or upper electrode can be formed by a sputtering method or a pulse laser ablation method. Note that the lower electrode and the upper electrode are names based on a MOS transistor element as a selection transistor element. In this specification, the terms “up” and “down” are based on a MOS transistor element in principle. Patterning of the lower electrode and / or the upper electrode can be performed by, for example, an ion milling method or an RIE method. Note that the upper electrode may also serve as a plate line, or a plate line may be provided separately from the upper electrode.

Between the lower electrode and the interlayer insulating layer, for example,
A barrier metal layer made of Ti, TiN, TiN / Ti, or TaN may be formed. The barrier metal layer can be formed by, for example, a sputtering method, which improves the adhesion of the lower electrode to the interlayer insulating layer, improves the crystallinity of the lower electrode, prevents the material constituting the lower electrode from diffusing into the interlayer insulating layer, The film is formed for the purpose of preventing the material constituting the interlayer insulating layer from diffusing into the lower electrode.

As materials for forming the interlayer insulating layer and the insulating layer, SiO ₂ , BPSG, PSG, BSG, AsSG,
PbSG, SbSG, NSG, SOG, LTO (Low Te
mperature Oxide, low temperature CVD-SiO ₂ ), SiN, S
A known material such as iON or a material obtained by laminating these materials can be exemplified.

As a form of the semiconductor memory cell having the capacitor structure of the present invention, a nonvolatile memory (so-called FERA) is used.
M) or DRAM.

In the present invention, first and second MOS type transistor elements functioning as selection transistor elements are provided above and below.
Is provided, it is possible to increase the area of the entire capacitor section of the semiconductor memory cell without increasing the area of the semiconductor memory cell. Can be increased. In addition, since the first capacitor portion and the second capacitor portion are flat,
Due to the planar-stack type structure, electric field concentration hardly occurs in the ferroelectric thin film.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the invention (hereinafter abbreviated as embodiments).

(Embodiment 1) FIG. 1 is a schematic partial cross-sectional view of a semiconductor memory cell according to Embodiment 1. In FIGS. 1 to 10, a region in a direction indicated by an arrow from a portion represented by a symbol “X” is a schematic partial cross-sectional view of the semiconductor memory cell in the X direction (indicating the horizontal direction in the drawing). . In addition, a region in a direction indicated by an arrow from a portion represented by the symbol “Y” is a schematic partial cross-sectional view of the semiconductor memory cell in the Y direction (a direction perpendicular to the X direction and indicating a direction perpendicular to the plane of the drawing). Is shown. Although two semiconductor memory cells are shown in the figure, a large number of semiconductor memory cells are actually arranged in the X direction. Although the decoder is composed of a plurality of plate line selecting transistor elements, only one plate line selecting transistor element is schematically illustrated in the figure.

This semiconductor memory cell has a first capacitor portion in the form of a flat plate and a first capacitor portion above the first capacitor portion.
MOS transistor element provided via an interlayer insulating layer 12 of the first embodiment, and a plate-shaped second capacitor portion provided above the MOS transistor element via a second interlayer insulating layer 40. The first capacitor section includes a lower electrode 2
1. A capacitor insulating film 22 made of a ferroelectric thin film and an upper electrode 23. In addition, the second capacitor unit includes:
It comprises a lower electrode 51, a capacitor insulating film 52 made of a ferroelectric thin film, and an upper electrode 53. The lower electrode 21 constituting the first capacitor unit is connected to the MOS via a first contact plug 14 provided in the first interlayer insulating layer 12.
Source / drain region 34 of type transistor element
A is connected. Further, the lower electrode 51 constituting the second capacitor unit is also connected to one of the source / drain regions 34A of the MOS transistor element via the second contact plug 42 provided in the second interlayer insulating layer 40. Have been.

The semiconductor memory cell according to the first embodiment has a first
And a second plate line 57 connected to the upper electrode 53 forming the second capacitor portion, and a first plate line 27 connected to the upper electrode 23 forming the capacitor portion. Plate line 27 and second plate line 5
7 is electrically connected. First plate line 27
Are formed on the first insulating layer 24, and the second plate lines 57 are formed on the second insulating layer 54. Further, in the semiconductor memory cell of the first embodiment, the first
The plate line 27 is connected to one source / drain region 37A of the plate line selecting transistor element via a third contact plug 26. Also, the second
The plate line 57 is also connected via a fourth contact plug 56 to one of the source / drain regions 37A of the plate line selecting transistor element. In addition, MOS
The type transistor element is formed in the semiconductor layer 10A, and the semiconductor memory cell is supported by the support substrate 30 located below the first plate line 27 via the insulating material layer 28 and the polycrystalline silicon layer 29.

Gate section 32 and source / drain region 3
The MOS transistor element composed of 4A and 34B corresponds to a selection transistor element. The plate line selecting transistor element includes a gate section 36 and source / drain regions 37A and 37B.

The other source / drain region 34 B of the MOS transistor is connected to the bit line 41. In the first embodiment, one capacitor insulating film 22,
52 and the upper electrodes 23 and 53
This is a structure formed on 51. The upper electrodes 23 and 53 of the plurality of semiconductor memory cells arranged in the Y direction are
The first and second plate lines 27 and 57 are shared.
The upper electrode 23, 53, via the plate line 27,57, for instance a constant voltage _{(V cc -V ss) / 2} (V) is applied. On the other hand, for example, V _ss or V _cc is applied to the bit line 41. As a result, information “0” or “1” can be written in the capacitor insulating films 22 and 52 made of the ferroelectric thin film. Although the bit line 41 extends in the left-right direction (X direction) of FIG. 1 without contacting the contact plug 42, the illustration of the bit line in this state is omitted. The gate section 32 extending in the Y direction also serves as a word line.

In the first embodiment, the lower electrodes 21 and
51 and the upper electrodes 23 and 53 are made of ruthenium oxide (RuO).
₂ ). Further, as the ferroelectric thin film, a Bi-based layered structure perovskite type ferroelectric material represented by the formula (2) was used. A barrier metal layer 20 is formed between the lower electrode 21 constituting the first capacitor section and the first interlayer insulating layer 12. Further, a barrier metal layer 50 is also formed between the lower electrode 51 constituting the second capacitor section and the second interlayer insulating layer 40. Embodiment 1
In, the barrier metal layers 20 and 50 were composed of a TiN layer (upper layer) / Ti layer (lower layer). In the figure,
These barrier metal layers 20 and 50 are represented by one layer.

FIG. 13 shows an equivalent circuit diagram of a semiconductor memory constituted by the semiconductor memory cells of the first embodiment. In the figure, WL ₁ and WL ₂ represent word lines, BL ₁ and BL ₂ represent bit lines, and PL ₁ and PL ₂ represent plate lines.

Hereinafter, a method of manufacturing a semiconductor memory cell according to the present invention will be described with reference to schematic partial cross-sectional views of a semiconductor substrate and the like in FIGS.

[Step-100] First, a concave portion 11 is formed on the surface of the semiconductor substrate 10, and then a first interlayer insulating layer 12 is formed on the surface of the semiconductor substrate 10, and then the first interlayer insulating layer 12 is formed. A first contact plug 14 is formed on 12. Specifically, first, the MOS type transistor functioning as a selection transistor element and the semiconductor substrate 10 other than the portion where the plate line selection transistor element is to be formed
(Corresponding to a region where an element isolation region is to be formed) by etching to form a concave portion 11 (FIG. 2A).
reference).

[Step-110] Thereafter, for example, BPSG
Is formed on the entire surface by the CVD method under the conditions exemplified in Table 1 below. The first
After the formation of the first interlayer insulating layer 12, it is preferable to reflow the first interlayer insulating layer 12 in a nitrogen gas atmosphere, for example, at 900 ° C. for 20 minutes. Further, if necessary, the top surface of the first interlayer insulating layer 12 is polished chemically and mechanically by, for example, a chemical mechanical polishing method (CMP method) to flatten the first interlayer insulating layer 12. Is desirable. Then MO
One source / drain region 34A of the S-type transistor
First interlayer insulating layer 1 corresponding to the portion above
An opening 13 is formed in the portion 2 by RIE. Then, the inside of the opening 13 is filled with polycrystalline silicon doped with impurities, and the first contact plug 1 is formed.
Complete 4 Specifically, the first portion including the inside of the opening 13
A polycrystalline silicon layer doped with impurities is formed on the interlayer insulating layer 12 by CVD, and the polycrystalline silicon layer is etched back to form the opening 13.
The inside is filled with polycrystalline silicon to form a first contact plug 14. Thus, the structure shown in the schematic partial cross-sectional view of FIG. 2B can be obtained.

[0038]

[Table 1] Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ Film formation temperature: 400 ° C Reaction pressure: normal pressure

[Step-120A] Next, on the first interlayer insulating layer 12, a lower electrode 21 connected to the first contact plug 14, a capacitor insulating film 22 made of a ferroelectric thin film, and an upper electrode 23 To form a first capacitor portion having a flat plate shape. For this purpose, first, a barrier metal layer 20 composed of a TiN layer / Ti layer is formed under the conditions shown in Table 2 below. The Ti layer is the lower layer and the TiN layer is the upper layer. Next, Ru (ruthenium) as a target
And a lower electrode layer made of RuO _{2 is formed} on the barrier metal layer 20 by a DC sputtering method using O ₂ / Ar as a process gas.

[0040]

Table 2 Sputtering conditions for Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Heating of substrate: None Sputtering condition for TiN layer (thickness: 100 nm) Process gas: N ₂ / Ar = 100/35 sccm Pressure: 1.0 Pa RF power: 6 kW Heating of substrate: None

[Step-120B] Then, a ferroelectric thin film made of a Bi-based layered structure perovskite ferroelectric material is formed on the entire surface by MOCVD. For example,
Table 3 below shows examples of film formation conditions for the ferroelectric thin film represented by Bi _X Sr _Y Ta ₂ O _d in the formula (2).

[0042]

[Table 3]

Alternatively, Bi _X Sr _Y Ta _{2 of the} formula (2)
A ferroelectric thin film represented by _Od can be formed on the entire surface by a pulse laser ablation method, a sol-gel method, or an RF sputtering method. The film forming conditions in this case are exemplified below. Incidentally, after forming the ferroelectric thin film represented by Bi _X Sr _Y Ta ₂ O _d of formula (2), 800 ° C × 1 hour, it is preferable to perform the post-baking in an oxygen atmosphere.

[0044]

TABLE 4 deposited by pulsed laser ablation _{target: Bi X Sr Y Ta 2 O} d using laser: KrF excimer laser (wavelength of 248 nm,
(Pulse width: 25 ns, 5 Hz) Film forming temperature: 500 ° C. Oxygen concentration: 3 Pa

[0045]

Table 5: Film formation by sol-gel method Raw material: Bi (CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₃ [bismuth / 2-ethylhexanoic acid, Bi (OOc) ₃ ] Sr (CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [bismuth / 2-ethylhexanoic acid, Sr (OOc) ₂ ] Ta (OEt) ₅ [tantalum ethoxide] Spin coating conditions: 3000 rpm × 20 seconds Drying: 250゜ C × 7 minutes Firing: 400-800 ゜ C × 1 hour (RT if necessary
A processing is added)

[0046]

[Table 6] Film formation by RF sputtering Target: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Film formation temperature: room temperature to 600 ° C. Process gas: Ar / O ₂ flow ratio = 2/1 to 9/1

[Step-120C] Next, as in [Step-120A], an upper electrode layer made of RuO ₂ is formed on the ferroelectric thin film, and then the upper electrode layer, the ferroelectric thin film,
The lower electrode layer and the barrier metal layer 20 are patterned by, for example, the RIE method. Thus, a lower electrode 21 made of RuO _2, the capacitor insulating film 22 made of a ferroelectric thin film formed on the lower electrode 21, and RuO ₂
Can be formed on the first interlayer insulating layer 12. Thus, a structure whose schematic partial cross-sectional view is shown in FIG. 3 can be obtained. In addition, since the ferroelectric thin film can be formed on the lower electrode in the surface state as it is formed, deterioration of the PE hysteresis loop characteristic of the ferroelectric thin film can be prevented.

[Step-130] Next, after forming the first insulating layer 24 on the first interlayer insulating layer 12 including the upper part of the first capacitor portion, select a plate line to be formed in a later step. Contact plug 26 for connection with the transistor element for the first interlayer insulating layer 12 and the first insulating layer 2
4 is formed. Specifically, a first insulating layer 24 made of, for example, SiO ₂ is formed on the entire surface by a CVD method. next,
The RI of the first insulating layer 24 and the first interlayer insulating layer 12 above the portion where one of the source / drain regions 37A of the plate line selecting transistor element is to be formed.
The opening 25 is formed by the E method. Further, an opening is formed in the first insulating layer 24 above the upper electrode 23. And
The opening is filled with polycrystalline silicon doped with impurities. As a result, the third contact plug 26 is formed in the first insulating layer 24 and the first interlayer insulating layer 12 above the portion where the one source / drain region 37A of the plate line selecting transistor element is to be formed. (See FIG. 4). Specifically, after a polycrystalline silicon layer doped with impurities is formed on the first insulating layer 24 including the inside of the opening by the CVD method, the polycrystalline silicon layer may be etched back.

[Step-140] Then, the upper electrode 23 constituting the first capacitor portion is connected via a contact plug provided in the first insulating layer 24, and
A first plate line 27 connected to the contact plug 26 is formed. That is, the first including the contact plug
On the insulating layer 24, for example, a metal wiring material layer is formed by a sputtering method, and the metal wiring material layer is patterned to form a first plate line 27.

[Step-150] Next, on the first interlayer insulating layer including on the first capacitor portion (more specifically, in the first embodiment, the first After forming the insulating material layer 28 and the polycrystalline silicon layer 29 on the first insulating layer 24), the support substrate 30 is bonded to the surface of the polycrystalline silicon layer 29. That is, after an insulating material layer 28 made of, for example, SiO ₂ is formed on the entire surface by a CVD method, a flattening process is performed. Then, after a polycrystalline silicon layer 29 is formed on the insulating material layer 28 by a CVD method, the polycrystalline silicon layer 29 is flattened (see FIG. 5). And a support substrate 3 made of a silicon semiconductor substrate.
0 and the polycrystalline silicon layer 29 (FIG. 6)
The semiconductor substrate 10 and the support substrate 30 are bonded together by thermocompression bonding in an O ₂ atmosphere of 700 ° C. or more.
Thereafter, the semiconductor substrate 10 is polished from the back surface side of the semiconductor substrate 10 to leave a portion of the semiconductor substrate on which the MOS transistor element is to be formed as the semiconductor layer 10A and expose a part of the first interlayer insulating layer 12. Thus, the structure shown in FIG. 7 with a schematic partial cross-sectional view can be obtained. At the same time, the portion of the semiconductor substrate where the plate line selecting transistor element is to be formed is left as the semiconductor layer 10B.

[Step-160] Then, the semiconductor layer 10A
Then, a MOS transistor element in which one of the source / drain regions 34A is connected to the first contact plug 14 is formed. At the same time, a transistor element for plate line selection in which one source / drain region 37A is connected to the third contact plug 26 is formed in the semiconductor layer 10B. Specifically, the surfaces of the semiconductor layers 10A and 10B are oxidized by, for example, a pyrogenic method to form the gate oxide film 3A.
1, 35 are formed. Next, a polycrystalline silicon layer doped with impurities is formed on the entire surface by a CVD method, and a SiO ₂ layer serving as an offset oxide film is further formed.
The O ₂ layer and the polysilicon layer are patterned to form gate portions 32 and 36. The gate section 32 also serves as a word line. Next, ions are implanted into the semiconductor layers 10A and 10B to form an LDD structure. After that, C
After forming the SiO ₂ layer by the VD method, the SiO ₂ layer is etched back to form the gate sidewalls 33 on the side surfaces of the gate portions 32 and 36. Next, after ion implantation is performed on the semiconductor layers 10A and 10B, activation annealing treatment of the ion-implanted impurities is performed, so that the source / drain regions 34A, 34B, 37A,
37B is formed. Thus, the structure shown in the schematic partial sectional view of FIG. 8 can be obtained.

Thereafter, the lower insulating layer made of SiO ₂ is
After being formed by the VD method, the other source / drain region 3 is formed.
An opening is formed in the lower insulating layer above 4B by RIE. Then, after a polycrystalline silicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method, the bit line 41 is formed by patterning the polycrystalline silicon layer on the lower insulating layer. Form. Thereafter, an upper insulating layer made of BPSG is formed on the entire surface by a CVD method. After the formation of the upper insulating layer made of BPSG, for example, at 900 ° C. for 20 minutes in a nitrogen gas atmosphere,
It is preferable to reflow the upper insulating layer. Furthermore,
If necessary, for example, chemical mechanical polishing (CMP)
It is desirable to polish the top surface of the upper insulating layer chemically and mechanically to flatten the upper insulating layer. The lower insulating layer and the upper insulating layer are collectively referred to as a second interlayer insulating layer 4 hereinafter.
Call it 0.

[Step-170] Thus, after the second interlayer insulating layer 40 is formed on the first interlayer insulating layer 12 including on the MOS transistor element, the second contact is formed on the second interlayer insulating layer 40. The plug 42 is formed. That is, MOS
Source / drain region 34 of type transistor element
An opening is formed in the second interlayer insulating layer 40 above A by RIE. Then, a polycrystalline silicon layer doped with impurities is formed on the second interlayer insulating layer 40 including the inside of the opening by a CVD method. Next, the second contact plug 42 is formed by etching back the polycrystalline silicon layer on the second interlayer insulating layer 40. Thus, the structure shown in FIG. 9 with a schematic partial sectional view can be obtained.

[Step-180] After that, the lower electrode 51 connected to the second contact plug 42, the capacitor insulating film 52 made of a ferroelectric thin film, and the upper electrode 53 are formed on the second interlayer insulating layer 40. A second flat plate-shaped capacitor portion is formed. Specifically, [Step-120A]-
The same step as [Step-120C] may be performed. In this way, a structure whose schematic partial cross-sectional view is shown in FIG. 10 can be obtained.

[Step-190] Next, after the second insulating layer 54 is formed on the second interlayer insulating layer 40 including the upper part of the second capacitor part, the upper electrode 53 of the second capacitor part is formed.
Is connected to one of the source / drain regions 37A of the plate line selecting transistor element via the second plate line 57 by connecting a fourth contact plug 56 to the second interlayer insulating layer 40 and the second insulating layer 54. Form. Specifically, the second insulating layer 54 made of, for example, SiO ₂ is formed by CVD.
It is formed on the entire surface by a method. Next, the second region above the source / drain region 37A of the plate line selecting transistor element
RIE is applied to the portions of the insulating layer 54 and the second interlayer insulating layer 40.
The opening 55 is formed by the method. Further, an opening is formed in the second insulating layer 54 above the upper electrode 53. Then, the inside of the opening is filled with polycrystalline silicon doped with impurities. As a result, the fourth insulating layer 54 and the second interlayer insulating layer 40 above the one source / drain region 37A of the plate line selecting transistor element are placed in the fourth
Is formed (see FIG. 11).
Specifically, after a polycrystalline silicon layer doped with impurities is formed on the second insulating layer 54 including the inside of the opening 55 and the like by the CVD method, the polycrystalline silicon layer is etched back. Good.

[Step-1000] Next, the upper electrode 53 constituting the second capacitor section is connected via a contact plug provided on the second insulating layer 54 and is connected to the fourth contact plug 56. The formed second plate line 57 is formed. That is, for example, a metal wiring material layer is formed on the second insulating layer 54 including on the contact plug by a sputtering method, and the metal wiring material layer is patterned to form the second plate line 57. Thus,
A semiconductor memory cell of Embodiment 1 whose schematic partial cross-sectional view is shown in FIG. 1 can be manufactured.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. The gate portions 32 and 36 and the bit line 41 can be made of polycide or metal silicide instead of being made of a polysilicon layer. As each interlayer insulating layer, B
PSG, BSG, AsS instead of PSG or SiO ₂
G, PbSG, SbSG, SOG, SiON or S
A known insulating material such as iN, or a laminate of these insulating materials can be used. The procedure for forming the bit lines 41 is arbitrary. For example, the bit lines can be formed after the plate lines 57 are formed.

Instead of forming the ferroelectric thin film from a Bi-based layered structure perovskite type ferroelectric material, PZT
Alternatively, it can be composed of PZLT. Table 7 below shows conditions for forming PZT or PZLT by magnetron sputtering.

[0059]

[Table 7] Target: PZT or PZLT Process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Film formation temperature: 500 ° C

Alternatively, PZT or PLZT can be formed by a pulse laser ablation method. Table 8 below shows examples of film forming conditions in this case.

[0061]

Table 8 Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 ns, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film forming temperature: 550 to 600 ° C. Oxygen concentration: 40 to 120 Pa

The lower electrode layer and the upper electrode layer may be made of platinum. P by RF magnetron sputtering
Table 9 below shows examples of the film forming conditions for the t film.

[0063]

Anode voltage: 2.6 kV Input power: 1.1 to 1.6 W / cm ² Process gas: Ar / O ₂ = 90/10 sccm Pressure: 0.7 Pa Film forming temperature: 600 to 750 ° C. Deposition rate : 5 to 10 nm / min

Alternatively, the lower electrode layer and the upper electrode layer
For example, it can be composed of LSCO. Table 10 below shows examples of the film forming conditions by the pulse laser ablation method in this case.

[0065]

[Table 10] Target: LSCO Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 ns, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film forming temperature: 550 to 600 ° C. Oxygen concentration: 40 to 120 Pa

Contact plugs (connection holes) 14, 26,
42, 56, etc. are formed in openings formed in the first interlayer insulating layer 12, the second interlayer insulating layer 40, the first insulating layer 24, the second insulating layer 54, etc., for example, W, Ti, Pt, Pd,
It can also be formed by embedding a metal wiring material made of a high melting point metal such as Cu, TiW, TiNW, WSi ₂ , MoSi ₂ or a metal silicide. The top surface of the contact plug may exist on substantially the same plane as the surface of the interlayer insulating layer or the insulating layer, or the top of the contact plug may extend on the surface of the interlayer insulating layer or the insulating layer. In order to fill the opening with tungsten, specifically,
A tungsten layer is formed on the entire surface including the inside of the opening, and thereafter, the interlayer insulating layer and the tungsten layer on the insulating layer are etched back. The following Table 11 and Table 12 show the CVD conditions and etching conditions for forming the tungsten layer. It is preferable that a Ti layer and a TiN layer are sequentially formed on the interlayer insulating layer including the inside of the opening by, for example, magnetron sputtering before forming the tungsten layer. Ti layer and T
The reason for forming the iN layer is to obtain an ohmic low contact resistance, to prevent the occurrence of damage to the semiconductor substrate and the semiconductor layer in the blanket tungsten CVD method, and to improve the adhesion of tungsten. The Ti layer and the TiN layer may be formed, for example, under the conditions shown in Table 2.

[0067]

Table 11 Conditions for CVD film formation of tungsten layer Gas used: WF ₆ / H ₂ / Ar = 40/400/2250 sccm Pressure: 10.7 kPa Film formation temperature: 450 ° C.

[0068]

Table 12 Etching conditions for tungsten layer, TiN layer and Ti layer First stage etching: Tungsten layer etching Gas used: SF ₆ / Ar / He = 110: 90: 5 sccm Pressure: 46 Pa RF power: 275 W Second stage Etching: TiN layer / Ti layer etching Gas used: Ar / Cl ₂ = 75/5 sccm Pressure: 6.5 Pa RF power: 250 W

If it is necessary to further increase the area of the capacitor insulating film, the first
Have a structure such that a part of their peripheral portions vertically overlap each other via an insulating layer, and / or
Alternatively, the second capacitor portions of adjacent semiconductor memory cells may have a structure in which a part of their peripheral portions overlaps vertically via an insulating layer. FIG. 12 is a schematic partial cross-sectional view of a structure in which second capacitor portions of adjacent semiconductor memory cells are vertically overlapped with each other at a part of their peripheral portions via a third interlayer insulating layer. . still,
In FIG. 12, the MOS transistor element and the first
The illustration of the capacitor section, the plate line selecting transistor element and the like is omitted. In addition, a component of one second capacitor unit and components related thereto are denoted by “A” at the end of the reference number, and a component of the other second capacitor unit and components related thereto are denoted by “A”. "B" was added to the end of the reference number.

A semiconductor memory cell of the present invention and a method of fabricating the same are described by using a nonvolatile memory (a so-called FE) using a ferroelectric thin film.
Not only RAM) but also DRAM. In this case, the polarization of the ferroelectric thin film is used within a range of an additional voltage that does not cause polarization inversion. That is, the difference between the residual polarization P _r when maximum by an external electric field (saturation) polarization P _max and the external electric field is 0 (P _max -P _r) is a constant relationship between the power supply voltage (approximately proportional relationship) Take advantage of the properties you have.
Polarization of the ferroelectric thin film is always located between the saturation polarization (P _max) and the residual polarization (P _r), not inverted. Data is held by refresh.

[0071]

According to the present invention, the first and second capacitor sections are provided above and below the MOS transistor element, so that the area of the semiconductor memory cell can be reduced without increasing the area of the semiconductor memory cell. The area of the entire capacitor section can be doubled. As a result, it is possible to increase the amount of charge stored in the capacitor portion. In addition, since the first capacitor portion and the second capacitor portion are plate-shaped, that is, because they have a planar stack type structure, electric field concentration hardly occurs in the ferroelectric thin film.

[Brief description of the drawings]

FIG. 1 is a schematic partial sectional view of a semiconductor memory cell according to a first embodiment of the present invention;

FIG. 2 is a schematic partial cross-sectional view of a semiconductor substrate and the like for describing a method for manufacturing a semiconductor memory cell of Embodiment 1 of the present invention.

FIG. 3 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 4;

FIG. 6 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 5;

FIG. 7 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of the semiconductor substrate and the like for describing the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 7;

FIG. 9 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 8;

FIG. 10 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 9;

FIG. 11 is a schematic partial cross-sectional view of the semiconductor substrate and the like for illustrating the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 10;

FIG. 12 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 13 is an equivalent circuit diagram of the semiconductor memory according to the first embodiment of the present invention;

FIG. 14 is a PE hysteresis loop diagram of a ferroelectric substance.

FIG. 15 is a schematic layout diagram and a schematic partial cross-sectional view of a conventional semiconductor memory having a planar-stack type capacitor structure.

FIG. 16 is a schematic partial cross-sectional view of a conventional DRAM.

FIG. 17 is a schematic layout view of a semiconductor memory having a conventional pedestal type capacitor structure.

FIG. 18 is a schematic partial cross-sectional view of a semiconductor memory having a conventional pedestal type capacitor structure.

[Explanation of symbols]

Reference numeral 10: semiconductor substrate, 10A: semiconductor layer, 11.
..Recessed part, 12, first interlayer insulating layer, 13, 25,
55 ... opening, 14 ... first contact plug, 20, 50 ... barrier metal layer, 21, 51 ...
.Lower electrodes, 22, 52: capacitor insulating film, 2
3, 53: upper electrode, 24: first insulating layer, 2
6 ... third contact plug, 27 ... first plate line, 28 ... insulating material layer, 29 ... polycrystalline silicon layer, 30 ... support substrate, 31, 35 ... Gate oxide film, 32, 36 ... Gate part, 33 ... Gate sidewall, 34A, 34B, 37A, 37B
..Source / drain region, 40 ... second interlayer insulating layer, 41 ... bit line, 42 ... second contact plug, 54 ... second insulating layer, 56 ... 4 contact plugs, 57 ... second plate line

Claims (5)

[Claims] A first capacitor portion having a plate shape, a MOS transistor element provided above the first capacitor portion via a first interlayer insulating layer, and a first transistor portion provided above the first capacitor portion. A semiconductor memory cell comprising a plate-shaped second capacitor portion provided with a second interlayer insulating layer interposed therebetween, wherein (a) each of the first and second capacitor portions is a lower electrode, a ferroelectric material. (B) a lower electrode forming a first capacitor portion, the lower electrode comprising a first capacitor portion;
Are connected to one of the source / drain regions of the MOS transistor element through a first contact plug provided in the interlayer insulating layer, and
A semiconductor memory cell connected to said one source / drain region of a MOS transistor element via a second contact plug provided in said interlayer insulating layer. A first plate line connected to an upper electrode forming the first capacitor portion; and a second plate line connected to an upper electrode forming the second capacitor portion. 2. The semiconductor memory cell according to claim 1, wherein the first plate line and the second plate line are electrically connected. 3. The MOS transistor element is formed in a semiconductor layer, and the semiconductor memory cell is supported by a support substrate located below the first plate line via an insulating material layer and a polycrystalline silicon layer. 3. The semiconductor memory cell according to claim 2, wherein: 4. A method according to claim 1, wherein a concave portion is formed on a surface of the semiconductor substrate.
Next, after forming a first interlayer insulating layer on the surface of the semiconductor substrate, forming a first contact plug in the first interlayer insulating layer; (b) forming a first contact plug on the first interlayer insulating layer; (C) forming a first flat plate-shaped capacitor portion including a lower electrode connected to the first contact plug, a capacitor insulating film including a ferroelectric thin film, and an upper electrode; After forming an insulating material layer and a polycrystalline silicon layer on the first interlayer insulating layer including the above,
Bonding a support substrate to the surface of the polycrystalline silicon layer; and (d) polishing the semiconductor substrate from the back side of the semiconductor substrate.
Leaving a part of the semiconductor substrate on which the OS-type transistor element is to be formed as a semiconductor layer and exposing a part of the first interlayer insulating layer; and (e) forming one source / drain region in the semiconductor layer. Forming a MOS transistor element connected to the first contact plug; and (f) forming a second interlayer insulating layer on the first interlayer insulating layer including on the MOS transistor element; Forming a second contact plug connected to the source / drain region in the second interlayer insulating layer; and (g) forming a lower electrode connected to the second contact plug on the second interlayer insulating layer. Forming a capacitor insulating film made of a ferroelectric thin film and a plate-shaped second capacitor part made of an upper electrode. 5. After the step (b), after forming a first insulating layer on the first interlayer insulating layer including on the first capacitor section, an upper portion constituting the first capacitor section is formed. Forming a first plate line connected to the electrode via a contact plug provided on the first insulating layer; and after the step (g), a second plate including a portion above the second capacitor portion. After forming a second insulating layer on the interlayer insulating layer, a second plate line connected to an upper electrode constituting the second capacitor unit via a contact plug provided in the second insulating layer is formed. Forming and electrically connecting the first plate line and the second plate line. In the step (c), on the first insulating layer including on the first plate line Forming an insulating material layer and a polycrystalline silicon layer on the substrate The method for manufacturing a semiconductor memory cell according to 4.