JP2002353416A - Semiconductor storage device and manufacturing method therefor - Google Patents

Semiconductor storage device and manufacturing method therefor

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Publication number
JP2002353416A
JP2002353416A JP2001157252A JP2001157252A JP2002353416A JP 2002353416 A JP2002353416 A JP 2002353416A JP 2001157252 A JP2001157252 A JP 2001157252A JP 2001157252 A JP2001157252 A JP 2001157252A JP 2002353416 A JP2002353416 A JP 2002353416A
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Japan
Prior art keywords
insulating film
bonding
semiconductor memory
forming
capacitor
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JP2001157252A
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Japanese (ja)
Inventor
Hidetoshi Iida
英敏 飯田
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Sony Corp
ソニー株式会社
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Priority to JP2001157252A priority Critical patent/JP2002353416A/en
Publication of JP2002353416A publication Critical patent/JP2002353416A/en
Pending legal-status Critical Current

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Abstract

(57) Abstract: A semiconductor memory device capable of forming a capacitor and a transistor at optimum process temperatures without deteriorating the characteristics of each other and a method of manufacturing the same are provided. A step of forming a field-effect transistor on a semiconductor substrate;
Forming the interlayer insulating films 107 and 110 on the substrate 2, and forming the charge storage electrode 112 and the capacitor insulating film 1 on the base material 118.
14 and the step of forming the counter electrode 115 and the step of bonding the semiconductor substrate 101 and the base material 118, preferably at room temperature, so that the field effect transistor 102 and the charge storage electrode 112 are electrically connected. A method of manufacturing a semiconductor storage device having the same, and a semiconductor storage device formed thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device including a transistor and a capacitor and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a capacitor insulating film made of a ferroelectric and a method of manufacturing the same.

[0002]

2. Description of the Related Art An increase in the capacity of a semiconductor memory device has been realized by miniaturization of a memory cell. A memory cell of a semiconductor memory device includes a capacitor in which electric charges are stored, and a switching transistor that connects the capacitor to a bit line. Since the area of the charge storage electrode is reduced due to the miniaturization of the memory cell, the capacitance value of the capacitor is reduced. For the purpose of increasing the area of the charge storage electrode, a capacitor having a three-dimensional charge storage electrode, such as a cylindrical capacitor, has also been formed.

[0003] However, as memory cells are miniaturized and the capacitor area is further reduced, it becomes difficult to form a charge storage electrode having a complicated three-dimensional structure. Therefore, it is necessary to secure the capacitance value of the capacitor by using a ferroelectric material such as a perovskite-type composite oxide for the capacitor insulating film.

Generally, 1T / 1 is used as a ferroelectric memory.
C-type memory cell and MFSFET (Metal-ferroelectric-
semiconductor FET) type memory cells. The 1T / 1C type memory cell has a structure similar to that of a DRAM, and uses a ferroelectric as a capacitor insulating film. On the other hand, MFSF
The ET type memory cell uses a ferroelectric as a gate insulating film of a MISFET. Hereinafter, a ferroelectric memory according to the present invention refers to a 1T / 1C type memory cell.

FIG. 7 is a sectional view showing an example of a ferroelectric memory. As shown in FIG. 7, a switching transistor 202 is formed on a semiconductor substrate 201, and a capacitor 203 is formed thereon. The switching transistor 202 has a source / drain region 204 between which a channel forming region is formed. A gate electrode 206 is formed over the channel formation region with a gate insulating film 205 interposed therebetween. The gate electrode 206 is connected to a word line. The source / drain region 204 and the gate electrode 206 are covered with an interlayer insulating film 207.

[0006] One of the source / drain regions 204 is connected to a bit line 209 via a plug 208.
The bit line 209 is covered with an interlayer insulating film 210. The other of the source / drain regions 204 is a plug 2
11 is connected to the capacitor 203.

[0007] The capacitor 203 has a lower electrode 212 in which electric charges are stored. Lower electrode 212 of ferroelectric memory
As a material, for example, noble metals such as Pt, Ru, and Ir and oxides thereof are used, and Pt is often used.
In particular, when Pt is used for the lower electrode 212, Pb, O, and the like, which are component elements of the ferroelectric substance, easily diffuse into the base through Pt. For the purpose of preventing such diffusion, a diffusion barrier layer 213 is provided at the interface between the lower electrode 212 and the underlying interlayer insulating film 210. As a material of the diffusion barrier layer 213, for example, TiN or Ta is used.

Further, as the interlayer insulating film 210, usually,
Although a silicon oxide film is used, Pt and SiO 2 have poor adhesion. Therefore, for the purpose of improving the adhesion between Pt and SiO 2 , although not shown, an adhesion layer is formed at the interface between the lower electrode 212 and the interlayer insulating film 210 or at the interface between the diffusion barrier layer 213 and the interlayer insulating film 210. May be provided. As a material of the adhesion layer, for example, Ti is used. An upper electrode 215 is formed on the lower electrode 212 via a capacitor insulating film 214. The upper electrode 215 is covered with an insulating film (or a passivation film) 216.

Conventionally, when manufacturing a ferroelectric memory having the above structure, first, a switching transistor 202 is formed on a semiconductor substrate 201, and then a capacitor 203 is formed on the switching transistor 202. Hereinafter, a method for forming the capacitor 203 after forming the switching transistor 202 will be described.

First, as shown in FIG. 8A, after a switching transistor 202 is formed, an interlayer insulating film 2 is formed.
07 is formed. A plug 208 is formed by forming a contact hole in the interlayer insulating film 207 and filling a conductor in the contact hole. In addition, plug 20
8 are formed on the interlayer insulating film 207. After that, an interlayer insulating film 210 covering the bit line 209 is formed on the interlayer insulating film 207.

Next, a contact hole is formed in the interlayer insulating films 207 and 210, and a conductor is buried in the contact hole to form a plug 211. Alternatively, although not shown, a part of the plug 211 (a plug of the interlayer insulating film 207) is formed in the same step as the plug 208, and another part of the plug 211 is formed in the same step as the bit line 209. After the formation of the interlayer insulating film 210, the remaining plugs can be formed only in the interlayer insulating film 210. As a material of the plugs 208 and 211, for example, polysilicon or tungsten is used.

Next, as shown in FIG.
11 on the interlayer insulating film 210 including the diffusion barrier layer 21
3, the lower electrode 212 is formed. Diffusion barrier layer 2
Before forming the layer 13, the above-mentioned adhesion layer may be formed. Next, as shown in FIG.
A capacitor insulating film 214 made of a ferroelectric is formed thereon.

The formation of the capacitor insulating film 214 requires heating for crystallization of the ferroelectric. In particular,
During film formation, the substrate is kept at a crystallization temperature or higher and a desired crystal structure is formed in an as-depo state, or a film is formed at a low temperature and then a heat treatment for crystallization (crystallization annealing) is performed.
The crystallization annealing temperature varies somewhat depending on the film forming method, but is usually 700 ° C. or higher, and particularly about 725 to 750 ° C.

Thereafter, as shown in FIG. 8D, an upper electrode 215 is formed on the capacitor insulating film 214. Further, by forming the insulating film 216 on the entire surface, the ferroelectric memory shown in FIG. 7 is obtained. In the process of processing the lower electrode 212, the capacitor insulating film 214, and the upper electrode 215, since the capacitor insulating film 214 is damaged by etching, before or after the formation of the insulating film 216, a high temperature, for example, 600-700 ° C. Heat treatment may be performed.

Since the steps of forming the lower electrode 212, the capacitor insulating film 214, and the upper electrode 215 include a film forming step and a processing step (etching step), as described above, the lower electrode 212, the capacitor insulating film 214, Instead of forming the upper electrode 215 in this order, a layered body may be formed by sequentially forming the material of each layer, and then the upper electrode 215, the capacitor insulating film 214, and the lower electrode 212 may be etched in this order.

Further, in order to increase the electrode area, an upper electrode may be formed not only on the upper portion of the lower electrode but also on the side surface thereof via a capacitor insulating film. In accordance with such a change in the shape of the capacitor, the method of forming the capacitor is appropriately changed. In any case, after the formation of the switching transistor, the capacitor is formed on the switching transistor via an interlayer insulating film.

[0017]

However, according to the above-mentioned conventional method of manufacturing a ferroelectric memory, various problems occur because formation of a capacitor involves a high-temperature process. Further, in order to avoid these problems, restrictions on manufacturing are increased, and characteristics of at least one of a transistor and a capacitor are sacrificed.

For example, when polysilicon is used as the material of the plug 211 and Pt is used as the material of the lower electrode 212 in FIG. 7, Pt is changed by crystallization annealing of the ferroelectric or annealing for recovering damage after electrode processing. It is silicided. The crystallinity of the ferroelectric forming the capacitor insulating film 214 is greatly affected by the crystallinity of the base.
Therefore, when Pt is silicided, the crystallinity of the ferroelectric material is lost, and good characteristics of the capacitor cannot be obtained.

When only a Ti layer is formed as an adhesion layer between the plug 211 and the lower electrode 212, Ti is also silicided. Further, the oxidation of Ti may cause the plug 211 and the lower electrode 212 to be electrically disconnected. Furthermore, since the oxidized Ti moves into Pt, the crystallinity of Pt is lost, and as a result, the crystallinity of the ferroelectric substance is lost. In addition, when oxidized Ti moves into Pt, voids may be generated near the Ti layer.

When a TiN layer is formed as the diffusion barrier layer 213 and has a three-layer structure of Pt / TiN / Ti, T
The movement of i into Pt is suppressed. However, Ti
Since the N layer has a significantly different coefficient of thermal expansion from the other layers, delamination between layers is likely to occur due to high-temperature heat treatment. Further, when a Ta layer is formed as the diffusion barrier layer 213, silicidation of Pt is prevented, but the plug 211 and the lower electrode 212 are not electrically connected because Ta is oxidized in the same manner as Ti.

In order to prevent silicidation or oxidation of the lower electrode or the adhesion layer as described above, Ti is added to the diffusion barrier layer.
It is relatively effective to use a nitride such as Ta or Ta. However, in order to sufficiently suppress silicidation of Pt, it is necessary to form a thick diffusion barrier layer made of nitride, and the problem of delamination due to local concentration of stress cannot be solved. In addition, when the high-temperature heat treatment is performed, the nitride itself is partially silicided or oxidized. Therefore, the contact resistance between the plug 211 and the lower electrode 212 is increased, or Pt is changed according to the degree of silicidation or oxidation.
Or the crystallinity of the material is lost.

If the heat treatment for crystallization of the ferroelectric is performed at a low temperature for the purpose of solving the above problems, the desired crystal structure and crystal orientation cannot be obtained, and the characteristics of the capacitor are degraded.

Further, according to the above-mentioned conventional method for manufacturing a ferroelectric memory, a capacitor insulating film is formed after wiring such as a bit line is formed. When a low melting point metal such as an Al-based alloy is used as a wiring material such as a bit line, the heat treatment temperature for crystallization of the ferroelectric is significantly higher than the melting point of the wiring material. Therefore, in order to prevent an increase in wiring resistance or disconnection due to wiring damage, high-temperature heat treatment after wiring formation is not desirable.

The present invention has been made in view of the above problems, and accordingly, the present invention provides a semiconductor memory device in which a transistor and a capacitor are formed at optimum process temperatures and good characteristics can be obtained. The purpose is to: It is another object of the present invention to provide a method of manufacturing a semiconductor memory device in which a capacitor and a transistor can be formed at optimum process temperatures without deteriorating the characteristics of each other.

[0025]

In order to achieve the above object, a semiconductor memory device of the present invention comprises a field effect transistor formed on a semiconductor substrate, an interlayer insulating film formed on the field effect transistor, A charge storage electrode formed on the interlayer insulating film and electrically connected to the field effect transistor; a capacitor insulating film formed on at least a portion of the surface of the charge storage electrode; At least a part thereof includes a counter electrode formed with the capacitor insulating film interposed therebetween, and a junction surface formed between the field effect transistor and the charge storage electrode.

Preferably, the bonding surface includes a bonding surface formed by cold bonding. Preferably, the capacitor insulating film is made of a ferroelectric material. More preferably, the ferroelectric material includes a ferroelectric material having a perovskite crystal structure, and the ferroelectric material includes PZT, barium titanate, or lead titanate. Alternatively, the ferroelectric material includes a bismuth layered compound, and the ferroelectric material includes SBT.

The semiconductor memory device of the present invention is preferably a plug formed in the interlayer insulating film, wherein the plug connected to the field effect transistor is provided between the plug and the charge storage electrode. The formed diffusion barrier layer further includes the diffusion barrier layer for preventing diffusion or reaction of the capacitor insulating film material and the plug material. Preferably, said plug material comprises polysilicon.

This makes it possible to perform a heat treatment on the capacitor insulating film without affecting the transistor characteristics. Therefore, good crystallinity of the capacitor insulating film is obtained, and a decrease in the capacitance value is prevented. In addition, since the transistor and the capacitor are joined at a normal temperature or a temperature close thereto, and high-temperature heat treatment is not required after the joining, a reaction between the plug material and the lower electrode material in the contact portion is also prevented.

Further, in order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming a field effect transistor on a semiconductor substrate and a step of forming an interlayer insulating film on the field effect transistor. Forming a charge storage electrode, a capacitor insulating film, and a counter electrode on a base material, wherein the counter electrode is formed so as to face the charge storage electrode via the capacitor insulating film; Bonding the semiconductor substrate and the base material so that the field effect transistor and the charge storage electrode are electrically connected to each other.

Preferably, the joining step includes a room temperature joining step. Preferably, the bonding step includes a step of irradiating the bonding surface with ions or atoms to clean the bonding surface, a step of setting the environment of the bonding surface to an ultra-high vacuum, and a step of contacting the bonding surface. And Preferably, the method further includes a step of pressing the bonding surface after the bonding surface is brought into contact with the bonding surface.
Preferably, the method further includes a step of heating the contact surface within a range that does not affect the transistor characteristics after the contact is made.

Preferably, the step of forming the capacitor insulating film includes a step of forming a ferroelectric material and a step of performing a heat treatment for crystallizing the ferroelectric material, wherein the heat treatment includes Done before. Preferably, the step of forming the charge storage electrode, the capacitor insulating film and the counter electrode includes a dry etching step, and after the dry etching, before the bonding, at least the dry etching is applied to the capacitor insulating film by the dry etching. A heat treatment is performed to recover the damaged damage. The method for manufacturing a semiconductor memory device of the present invention preferably further includes a step of removing the base material after the bonding step.

Preferably, in the method of manufacturing a semiconductor memory device according to the present invention, a step of forming a plug connected to the field effect transistor in the interlayer insulating film after forming the interlayer insulating film and before performing the bonding. The bonding step includes a step of electrically connecting the field effect transistor and the charge storage electrode via the plug.

Preferably, in the method of manufacturing a semiconductor memory device according to the present invention, after forming the charge storage electrode and before performing the bonding, the diffusion of the capacitor insulating film material and the plug material is prevented or diffusion is prevented. The method further includes forming a barrier layer on the surface of the charge storage electrode, and the joining step includes a step of electrically connecting the field effect transistor and the charge storage electrode via the diffusion barrier layer.

This makes it possible to prevent the transistor characteristics from being impaired in the heat treatment step of forming the capacitor. Further, since the crystallization of the capacitor insulating film can be performed at an optimum temperature, good capacitor characteristics can be obtained. Further, according to the method of manufacturing a semiconductor memory device of the present invention, a high-temperature heat treatment is not required after joining the transistor and the capacitor, so that the reaction between the plug material and the lower electrode material in the contact portion, the plug material and the diffusion barrier Reaction with the layer material is prevented.

[0035]

Embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1A is a cross-sectional view of the ferroelectric memory according to the present embodiment. As shown in FIG.
1, a switching transistor 102 is formed, and a capacitor 103 is formed thereon. The switching transistor 102 has a source / drain region 104, and a region between them serves as a channel formation region. A gate electrode 106 is formed over the channel formation region with a gate insulating film 105 interposed therebetween. Gate electrode 10
6 is connected to a word line. The source / drain region 104 and the gate electrode 106 are covered with an interlayer insulating film 107.

One of the source / drain regions 104 is connected to a bit line 109 via a plug 108.
The bit line 109 is covered with an interlayer insulating film 110. As the interlayer insulating film, for example, a silicon oxide film is used. The other of the source / drain regions 104 is connected to the capacitor 103 via the plug 111.

The capacitor 103 has a lower electrode 112 in which electric charges are stored. Lower electrode 112 of ferroelectric memory
As a material, for example, noble metals such as Pt, Ru, and Ir and oxides thereof are used, and Pt is often used.
In particular, when Pt is used for the lower electrode 112, Pb, O, and the like, which are component elements of the ferroelectric substance, easily diffuse into the base through Pt. For the purpose of preventing such diffusion, a diffusion barrier layer 113 is provided at the interface between the lower electrode 112 and the underlying interlayer insulating film 110. As a material of the diffusion barrier layer 113, for example, TiN or Ta is used.

Although not shown, the interface between the lower electrode 112 and the interlayer insulating film 110 or the diffusion barrier layer 113 between the interlayer insulating film 110 and the interlayer insulating film 110 is not shown for the purpose of improving the adhesion between SiO 2 of the interlayer insulating film 110 and Pt of the lower electrode. An adhesive layer may be provided at the interface with the insulating film 110. As a material of the adhesion layer, for example, Ti is used.

The capacitor insulating film 11 is formed on the lower electrode 112.
4, an upper electrode 115 is formed. Diffusion barrier layer 113, lower electrode 112, capacitor insulating film 114
In addition, an interlayer insulating film 116 is formed around the upper electrode 115. On upper electrode 115 and interlayer insulating film 11
An insulating film 117 is formed on 6.

As shown in FIG. 1B, the semiconductor memory device of the present embodiment is formed by bonding a switching transistor 102 formed on a semiconductor substrate 101 and a capacitor 103 formed on a base material 118. It is formed by joining. Since the switching transistor 102 and the capacitor 103 are formed separately, the capacitor 1
Even if a high-temperature heat treatment is performed in the process of forming 03, the switching transistor 102 and the bit line 109 are not affected by the heat treatment.

The switching transistor 102
And the contact portion of the capacitor 103 does not cause a reaction due to the high-temperature heat treatment. Specifically, plug 1
Between the lower electrode 112 and the diffusion barrier layer 113
Alternatively, the reaction between the adhesion layer and the lower electrode 112 is suppressed.
Therefore, good crystallinity is obtained in the lower electrode 112, and it is possible to prevent the crystallinity of the capacitor insulating film 114 from being lost due to the crystallinity of the lower electrode 112.

Hereinafter, a method for manufacturing the semiconductor memory device according to the present embodiment will be described. Switching transistor 102
And the capacitor 103 are formed separately. The formation of the switching transistor 102 and the formation of the capacitor 103 can be performed in parallel. 2A to 2D show a method for forming the switching transistor 102. FIG. FIG.
(E) to (f) show an example of a method for forming the capacitor 103.

To form the switching transistor 102, first, as shown in FIG. 2A, a gate electrode 10 is formed on a semiconductor substrate 101 via a gate insulating film 105.
6 is formed. Using the gate electrode 106 as a mask, for example, ion implantation is performed, and the source /
A drain region 104 is formed.

Next, as shown in FIG. 2B, for example, a silicon oxide film is formed as an interlayer insulating film 107 on the gate electrode 106 and the source / drain regions 104.
Further, a contact hole connected to one of the source / drain regions 104 is formed in the interlayer insulating film 107, and a conductor is buried in the contact hole to form a plug 1
08 is formed. As a material of the plug 108, for example, polysilicon or tungsten is used.

Next, as shown in FIG.
A bit line 109 connected to 08 is formed on the interlayer insulating film 107. As the material of the bit line 109, for example, Al or an Al-based alloy is used. The bit line 109 is formed, for example, by forming an Al layer on the entire surface by sputtering and then performing dry etching. Thereafter, a silicon oxide film, for example, is formed as an interlayer insulating film 110 on the bit line 109 and the interlayer insulating film 107.

Next, as shown in FIG.
A contact hole connected to the other of the drain region 104 is formed in the interlayer insulating films 107 and 110, and a conductor is buried in the contact hole to form a plug 111. As the material of the plug 111, for example, polysilicon or tungsten is used.

Alternatively, although not shown, in the step of forming the plug 108, the plug is formed not only in one of the source / drain regions 104 but also in both, and the bit line 109 is formed.
May be formed on the plug of the source / drain region 104 that is not connected to the bit line 109. In this case, after the formation of the interlayer insulating film 110, the plug 1 connected to the source / drain region 104 is formed only by forming a contact hole in the interlayer insulating film 110.
11 is formed. Through the above steps, the semiconductor substrate 101
The switching transistor 102 formed above is
As shown in FIG. 1B, the capacitor 103 is bonded to the capacitor 103 at room temperature.

On the other hand, to form the capacitor 103,
First, as shown in FIG. 3E, an insulating film 117 is formed on a base material 118. The insulating film 117 functions as a protective film for the capacitor 103. Upper electrode 11 on insulating film 117
5 is formed. As the base material 118, for example, a silicon wafer can be used, but it is not limited to a silicon wafer. Any material having sufficient strength for supporting the capacitor 103 and heat resistance to high-temperature heat treatment at the time of forming the capacitor insulating film 114 can be used as the base material 118. For example, a silicon sheet, a ceramic disk, or the like may be used as the base material 118 instead of a silicon wafer.

As the insulating film 117, for example, a silicon oxide film or a silicon nitride film is used. The insulating film 117 is formed, for example, by chemical vapor deposition (CVD).
n). The material of the upper electrode 115 is P
Noble metals such as t, Ru and Ir and oxides thereof are used, but Pt is often used. The upper electrode 115 is formed by forming a layer made of these materials by, for example, sputtering or metal C.
It is formed by performing dry etching after forming a film by VD or the like.

For example, when a silicon oxide film is used as the insulating film 117 and Pt is used as the material of the upper electrode 115, an interface between these layers is formed in order to improve the adhesion between the insulating film 117 and the upper electrode 115. An adhesion layer may be formed. As the adhesive layer material, for example, Ti is used.

Next, as shown in FIG. 3F, a capacitor insulating film 114 is formed on the upper electrode 115. As the material of the capacitor insulating film 114, for example, PZT (PbZ
r x Ti 1-x O 3 ) material having a perovskite crystal structure, such as a system or SBT, (SrBi 2 Ta 2 O 9)
A ferroelectric substance such as a bismuth layered structure compound is used. The capacitor insulating film 114 is made of a ferroelectric material, for example, a sputtering method, MOCVD (metal organic CVD).
Method, sol-gel method, MOD (metal organic decompositio
n) method, after forming a film by laser ablation method,
It is formed by performing dry etching.

When the capacitor insulating film 114 is formed, heating for crystallization of the ferroelectric is performed. Specifically, the substrate is kept at a crystallization temperature or higher at the time of film formation and a desired crystal structure is formed in an as depo state, or a heat treatment for crystallization (crystallization annealing) is performed after forming the film at a low temperature. Apply. The crystallization annealing temperature varies somewhat depending on the film forming method, but is usually 700 ° C. or higher, and particularly about 725 to 750 ° C. Since crystallization annealing is performed independently of the transistor,
There is no need to consider the influence on the characteristics of the transistor, and the operation can be performed at an optimum temperature.

Next, as shown in FIG. 3G, a lower electrode 112 is formed on the capacitor insulating film 114. As the material of the lower electrode 112, P
Noble metals such as t, Ru and Ir and oxides thereof are used, but Pt is often used. The lower electrode 112 is formed by forming a layer made of these materials by, for example, sputtering or metal C.
It is formed by performing dry etching after forming a film by VD.

Further, a diffusion barrier layer 113 is formed on the lower electrode 112. In particular, when Pt is used for the lower electrode 112, Pb, O, etc., which are component elements of the ferroelectric,
It easily diffuses into the interlayer insulating film 110 through t. For the purpose of preventing such diffusion, a diffusion barrier layer 113 is provided at the interface between the lower electrode 112 and the underlying interlayer insulating film 110. As a material of the diffusion barrier layer 113, for example, TiN
And Ta are used. The diffusion barrier layer 113 is formed, for example, by forming a TiN layer or a Ta layer by sputtering,
It is formed by performing dry etching.

Lower electrode 112 and diffusion barrier layer 113
The capacitor insulating film 114 is damaged by the dry etching. Also, when the crystallization annealing of the capacitor insulating film 114 is performed before the dry etching step of the capacitor insulating film 114, the capacitor insulating film 114 is also damaged by etching. In order to recover this, after the diffusion barrier layer 113, a high temperature, for example, 6
A heat treatment at 00 to 700 ° C. may be performed.

The steps of forming the upper electrode 115, the capacitor insulating film 114, the lower electrode 112, and the diffusion barrier layer 113 include a film forming step and a processing step (etching step). Instead of forming the capacitor insulating film 114, the lower electrode 112, and the diffusion barrier layer 113 in this order, a material of each layer is sequentially formed to form a laminate, and then the diffusion barrier layer 113, the lower electrode 112, and the capacitor insulating film are formed. 114, upper electrode 115
May be performed in this order.

Thereafter, after an interlayer insulating film is formed on the entire surface, for example, chemical mechanical polishing (CMP) is performed until the diffusion barrier layer 113 is exposed. Thereby, as shown in FIG. 1B, an interlayer insulating film 116 is formed around the capacitor 103, and a flat bonding surface is obtained.

Next, as shown in FIG. 1B, the transistor 102 formed on the semiconductor substrate 101 and the substrate 1
A normal temperature bonding is performed by facing the capacitor 103 formed on 18. Usually, atoms on the surface of a metal or the like are stabilized by bonding to oxygen. Therefore, an oxide film exists on the surface. In addition, the surface of a substance other than a metal is stabilized by being covered with, for example, an oil film. For example, when the sample surface is irradiated with an ion beam in an ultra-high vacuum of about 10 −3 Torr, such a coating on the surface is removed, and an unstable and active surface is exposed. When the exposed active surfaces are brought into contact with each other, the atoms on the bonding surface can be bonded at room temperature.

Room-temperature bonding is a method in which a material is subjected to large plastic deformation at room temperature to perform bonding, and is known to be applicable to bonding of various substances such as metals, ceramics, and semiconductor materials such as silicon and gallium arsenide. . For example, Japanese Patent Publication No. 8-9108 discloses room-temperature bonding. Japanese Patent Application Laid-Open No. H10-258369 discloses a room temperature bonding method and a bonding apparatus used for the method. Patent No. 25
Japanese Unexamined Patent Publication No. 19273 discloses an ultrahigh vacuum bonding apparatus used for room temperature bonding. These joining methods and joining devices can be applied to the method of manufacturing the semiconductor memory device of the present embodiment.

At room temperature bonding, the transistor 102 and the capacitor 103 are connected to the plug 111 and the diffusion barrier layer 1.
After the connection via 13, the base material 118 is removed as necessary. When a silicon wafer is used as the base material 118, the base material 118 can be removed by bonding at room temperature and then polished by, for example, a back grinding process (BGR). According to BGR, a protective tape is attached to the front surface and the back surface is cut and polished. Through the above steps, the semiconductor memory device shown in FIG. 1A is obtained.

(Embodiment 2) FIG. 4A is a sectional view of a ferroelectric memory according to the present embodiment. The ferroelectric memory according to the present embodiment has the same structure as the ferroelectric memory according to the first embodiment shown in FIG. 1A except that an interlayer insulating film 116 is formed on the bonding surface on the capacitor 103 side. Have.

The ferroelectric memory according to the present embodiment has a structure shown in FIG.
As shown in (b), the interlayer insulating film 116 and the interlayer insulating film 1
10 is formed by bonding at room temperature. Before performing the room temperature bonding, the lower electrode 11 is partially formed on the interlayer insulating film 116.
2 is formed. The plug 111 and the plug 119 are connected by room-temperature bonding. Thereafter, as in the first embodiment, the base material 118 is removed as necessary. As described above, room temperature bonding can be performed even when the diffusion barrier layer 113 of the capacitor 103 is not exposed.

Embodiment 3 In the semiconductor memory device shown in FIG. 1A, the structure of the capacitor 103 can be arbitrarily changed. For example, for the purpose of increasing the electrode area, the upper electrode can be formed not only on the upper portion of the lower electrode but also on the side surface thereof via the capacitor insulating film. FIG. 5A is a sectional view of the ferroelectric memory according to the present embodiment. The ferroelectric memory of the present embodiment has the same structure as that of FIG.
Has the same structure as the ferroelectric memory of the first embodiment shown in FIG.

The ferroelectric memory of the present embodiment is similar to that of FIG.
As shown in (b), the capacitor 103 having the capacitor insulating film 114 and the upper electrode 115 also formed on the side surfaces of the lower electrode 112 is formed by bonding the transistor 103 to the transistor 102 at room temperature. After the room temperature bonding, as in the first embodiment, the base material 118 is removed as necessary.

An example of a method for forming the capacitor 103 of the ferroelectric memory according to the present embodiment will be described with reference to FIG. First, as shown in FIG. 6A, an interlayer insulating film 116 is formed on a base material 118. Next, as shown in FIG. 6B, the interlayer insulating film 116 in the capacitor formation region is etched to form a trench.

Next, as shown in FIG. 6C, the upper electrode material 115a is formed on the interlayer insulating film 116 including the inside of the trench.
Capacitor insulating film material 114a, lower electrode material 112a
And a diffusion barrier layer material 113a are sequentially deposited. Thereafter, as shown in FIG. 6D, etch back or CMP is performed to form the upper electrode 115, the capacitor insulating film 114, the lower electrode 112, and the diffusion barrier layer 1 in the trench.
Leave 13. Also in the present embodiment, crystallization annealing of the capacitor insulating film is performed as in the first embodiment.

The capacitor 103 formed as described above
Is bonded to the transistor 102 as shown in FIG. Thereby, the ferroelectric memory of the present embodiment is formed. According to the semiconductor memory device and the method of manufacturing the same according to the embodiment of the present invention, the transistor characteristics are not impaired by the heat treatment in the process of forming the capacitor, and the transistor and the capacitor are formed at optimum process temperatures.

Further, according to the method of manufacturing the semiconductor memory device of the embodiment of the present invention, since the transistor and the capacitor are formed separately, they need not always be manufactured on the same line. For example, when a cost advantage can be obtained, the transistor and the capacitor can be manufactured at different locations, or at least one of the transistor and the capacitor can be stocked.

Embodiments of the semiconductor memory device and the method of manufacturing the same according to the present invention are not limited to the above description. For example,
The capacitor structure is not limited to the structures described in Embodiments 1 to 3, and may be a structure in which, for example, an upper electrode is formed on a part of the surface of the capacitor insulating film. Further, the present invention can be applied to a capacitor having a complicated three-dimensional structure such as a cylinder type. In addition, various changes can be made without departing from the gist of the present invention.

[0070]

According to the semiconductor memory device of the present invention, good characteristics can be obtained in each of the transistor and the capacitor. Further, according to the method for manufacturing a semiconductor memory device of the present invention, it is possible to form a capacitor and a transistor at optimal process temperatures without deteriorating the characteristics of each other.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view illustrating a bonding surface of FIG. 1A.

FIGS. 2A to 2D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to a first embodiment of the present invention.
The method for forming the portion will be described.

FIGS. 3 (e) to 3 (g) are cross-sectional views showing the manufacturing steps of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and show the method for forming the capacitor 103 shown in FIG. 1 (a). Is shown.

FIG. 4A is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention, and FIG. 4B is a cross-sectional view showing a bonding surface of FIG. 4A.

FIG. 5A is a cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 5B is a cross-sectional view showing a bonding surface of FIG. 5A.

6A to 6D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention, and show a method of forming the capacitor 103 in FIG. 5A. Is shown.

FIG. 7 is a sectional view of a conventional semiconductor memory device.

8A to 8D are cross-sectional views showing a manufacturing process of a conventional method of manufacturing a semiconductor memory device, and show a method of forming a capacitor 203 in FIG.

[Explanation of symbols]

101, 201: semiconductor substrate, 102, 202: switching transistor, 103, 203: capacitor,
104, 204... Source / drain regions, 105, 20
5 gate insulating film, 106, 206 gate electrode, 10
7, 110, 116, 207, 210 ... interlayer insulating film, 1
08, 111, 208, 211 ... plug, 109, 20
9: bit line, 112, 212: lower electrode, 113, 2
13: diffusion barrier layer, 114, 214: capacitor insulating film, 115, 215: upper electrode, 117, 216: insulating film, 118: base material, 119: plug.

Claims (19)

    [Claims]
  1. A field effect transistor formed on a semiconductor substrate; an interlayer insulating film formed on the field effect transistor; formed on the interlayer insulating film and electrically connected to the field effect transistor. A charge storage electrode, a capacitor insulating film formed on at least a part of the surface of the charge storage electrode, a counter electrode formed on at least a part of the surface of the charge storage electrode via the capacitor insulating film, A semiconductor memory device having a junction surface formed between a field effect transistor and the charge storage electrode.
  2. 2. The semiconductor memory device according to claim 1, wherein said bonding surface includes a bonding surface formed by room-temperature bonding.
  3. 3. The semiconductor memory device according to claim 1, wherein said capacitor insulating film is made of a ferroelectric material.
  4. 4. The semiconductor memory device according to claim 3, wherein said ferroelectric material includes a ferroelectric material having a perovskite crystal structure.
  5. 5. The ferroelectric material is PZT (PbZr x T).
    5. The semiconductor memory device according to claim 4, comprising i 1-x O 3 ), barium titanate (BaTiO 3 ), or lead titanate (PbTiO 3 ).
  6. 6. The semiconductor memory device according to claim 3, wherein said ferroelectric material includes a bismuth layered compound.
  7. 7. The ferroelectric material is SBT (SrBi 2 T).
    7. The semiconductor memory device according to claim 6, comprising a 2 O 9 ).
  8. 8. A plug formed in the interlayer insulating film, the plug connected to the field effect transistor, and a diffusion barrier layer formed between the plug and the charge storage electrode, 2. The semiconductor memory device according to claim 1, further comprising: the diffusion barrier layer for preventing diffusion or reaction of the capacitor insulating film material.
  9. 9. The semiconductor memory device according to claim 8, wherein said plug material includes polysilicon.
  10. 10. A step of forming a field-effect transistor on a semiconductor substrate; a step of forming an interlayer insulating film on the field-effect transistor; and forming a charge storage electrode, a capacitor insulating film, and a counter electrode on a base material. A step of forming the counter electrode so as to face the charge storage electrode via the capacitor insulating film; and forming the semiconductor so that the field effect transistor and the charge storage electrode are electrically connected to each other. A method for manufacturing a semiconductor memory device, comprising: a step of bonding a substrate and the base material.
  11. 11. The method according to claim 10, wherein said bonding step includes a room temperature bonding step.
  12. 12. The bonding step includes: a step of irradiating the bonding surface with ions or atoms to clean the bonding surface; a step of setting the environment of the bonding surface to ultra-high vacuum; and a step of bringing the bonding surface into contact. 11. The method for manufacturing a semiconductor memory device according to claim 10, comprising the steps of:
  13. 13. The method of manufacturing a semiconductor memory device according to claim 12, further comprising a step of pressing the bonding surface after bringing the bonding surface into contact.
  14. 14. The method of manufacturing a semiconductor memory device according to claim 12, further comprising the step of heating after contacting said bonding surface within a range that does not affect the transistor characteristics.
  15. 15. The step of forming the capacitor insulating film includes a step of forming a ferroelectric material and a step of performing a heat treatment for crystallizing the ferroelectric material, wherein the heat treatment is performed before the bonding. 11. The method for manufacturing a semiconductor memory device according to claim 10, wherein
  16. 16. The step of forming the charge storage electrode, the capacitor insulating film and the counter electrode includes a dry etching step, and after the dry etching and before the bonding, at least the capacitor insulating film is formed by the dry etching. 11. The method of manufacturing a semiconductor memory device according to claim 10, further comprising a step of performing a heat treatment for recovering the applied damage.
  17. 17. The method for manufacturing a semiconductor memory device according to claim 10, further comprising a step of removing said base material after said joining step.
  18. 18. The method according to claim 18, further comprising, after forming the interlayer insulating film and before performing the bonding, forming a plug connected to the field effect transistor in the interlayer insulating film. 11. The method according to claim 10, further comprising the step of electrically connecting a transistor and the charge storage electrode via the plug.
  19. 19. A step of forming a diffusion barrier layer on the surface of the charge storage electrode for preventing diffusion or reaction of the capacitor insulating film material after forming the charge storage electrode and before performing the bonding. 11. The method of manufacturing a semiconductor memory device according to claim 10, wherein said joining step includes a step of electrically connecting said field effect transistor and said charge storage electrode via said diffusion barrier layer.
JP2001157252A 2001-05-25 2001-05-25 Semiconductor storage device and manufacturing method therefor Pending JP2002353416A (en)

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US9385024B2 (en) 2003-02-07 2016-07-05 Ziptronix, Inc. Room temperature metal direct bonding
US9716033B2 (en) 2005-08-11 2017-07-25 Ziptronix, Inc. 3D IC method and device
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10522499B2 (en) 2017-02-09 2019-12-31 Invensas Bonding Technologies, Inc. Bonded structures

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Cited By (16)

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Publication number Priority date Publication date Assignee Title
US10141218B2 (en) 2003-02-07 2018-11-27 Invensas Bonding Technologies, Inc. Room temperature metal direct bonding
US9385024B2 (en) 2003-02-07 2016-07-05 Ziptronix, Inc. Room temperature metal direct bonding
US9716033B2 (en) 2005-08-11 2017-07-25 Ziptronix, Inc. 3D IC method and device
US10147641B2 (en) 2005-08-11 2018-12-04 Invensas Bonding Technologies, Inc. 3D IC method and device
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10262963B2 (en) 2015-08-25 2019-04-16 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10269708B2 (en) 2015-12-18 2019-04-23 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10607937B2 (en) 2015-12-18 2020-03-31 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10546832B2 (en) 2016-12-21 2020-01-28 Invensas Bonding Technologies, Inc. Bonded structures
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10522499B2 (en) 2017-02-09 2019-12-31 Invensas Bonding Technologies, Inc. Bonded structures

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