JP2002289809A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fine COP structure without causing oxidation of a plug. SOLUTION: This semiconductor device is provided with a semiconductor substrate 1, an interlayer insulating film 7 having a contact hole reaching a source drain layer 2 formed on the semiconductor substrate 1, the plug 10 which is formed in the contact hole and whose main component is Ru, and a capacitor which is formed on the interlayer insulating film 7 and electrically connected to the plug 10. The capacitor has constitution, containing a lower capacitor electrode 11 whose main component is SrRuO3 and which is directly connected with the plug 10, and a ferroelectric substance film 12 and an upper capacitor electrode 13 which are formed on the lower capacitor electrode 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, ferroelectric memories, which are nonvolatile memories using ferroelectric thin films, have been developed. A ferroelectric memory is obtained by replacing a capacitor portion of a DRAM with a dielectric.

It is considered that a COP (Capacitor On Plug) structure is indispensable for miniaturizing a cell of a ferroelectric memory and increasing its capacity. The COP structure is a structure in which a plug made of W or Si connected from an active area of a transistor is located immediately below a capacitor.

FIG. 5 shows a conventional COP structure. In the figure,
81 is a silicon substrate, 82 is a source / drain diffusion layer of a transistor, 83 is a BPSG film, 84 is a laminated insulating film of a silicon nitride film / silicon oxide film, 85 is a plug made of W or polycrystalline Si, 86 is a lower capacitor electrode , 8
7, a PZT film (capacitor insulating film); and 88, an upper capacitor electrode.

When forming this kind of COP structure, a heat treatment in an oxidizing atmosphere is performed a plurality of times after the plug 85 is formed. One of them is a heat treatment for crystallizing the PZT film 87. In addition, RIE (Reactive I
On-etching) heat treatment for recovering the damage of the insulating films 83 and 84 caused by the processing.

Since heat treatment in such an oxidizing atmosphere is required, when W is used as the material of the plug 85, a W oxide is formed and the contact between the plug 85 and the lower capacitor electrode 86 is formed. The plug structure itself is destroyed due to failure or volume expansion of the plug 85. On the other hand, when polycrystalline Si is used as the material of the plug 85, a contact failure similarly occurs because a Si oxide is formed.

Although Pt is a typical material of the lower capacitor electrode 86, Pt has no oxygen barrier property,
The generation of i-oxide cannot be prevented. Therefore, it is conceivable to use Ir, IrO _2, or the like, which is reported to have an oxygen barrier property, as the material of the lower capacitor electrode 86.

However, in this kind of material, the reaction or interdiffusion between Pb and Ir in the PZT film 87 easily occurs, so that the leakage current of the capacitor increases. Such a problem arises because the material of the lower capacitor electrode 86 is R
This occurs when u or RuO ₂ is used.

Further, the Ir film 86 and the laminated insulating film 84 (Si)
Good adhesion of silicon nitride film and silicon nitride film)
Therefore, the interface between the Ir film 86 and the laminated insulating film 84 is not
The plug 85 may be oxidized by an oxidizing species.
IrO instead of the Ir film 86 _TwoSame when using membrane
Problem.

In order to solve such a problem, a lower capacitor electrode structure as shown in FIG. 6 has been proposed. That is, the lower capacitor electrode 86 is formed of a laminated film of an Ir film 86 ₁ (antioxidant film) and a Pt film 86 _2, and further, a Ti film is formed between the Ir film 86 ₁ and the laminated insulating film 84.
It has been proposed to provide a film (adhesion film) 89.

[0011] Ir film 86 ₁ to prevent oxidation of the plug 85, Ti film 89 enhances the adhesion between the Ir film 86 ₁ and the laminated insulating film 84, from the interface between the Ir film 86 ₁ and the laminated insulating film 84 Prevent entry of oxidizing species.

However, the COP structure shown in FIG. 6 has the following problems. That is, since noble metals such as Pt and Ir do not have a compound having a high vapor pressure, the RIE of the Pt film and the Ir film is not performed.
Problems such as reattachment to the side of the capacitor and fence formation during processing occur. Such a problem can be solved by taper etching, but it is difficult to miniaturize the capacitor, and the advantage of the COP structure cannot be sufficiently exhibited.
Further, the introduction of the Ti film 89 further complicates the structure, which also hinders miniaturization. There is also a problem that the Ti film 89 is oxidized by the recovery annealing.

[0013]

As described above, the conventional C
The OP structure has been proposed to use a stacked film of a Ti film / Ir film / Pt film as a lower capacitor electrode structure in order to prevent oxidation of the plug.
Due to the difficulty of the RIE processing of the r film and the multilayer structure, there is a problem that miniaturization of the capacitor becomes difficult.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of easily realizing a fine COP structure and a method of manufacturing the same.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

To achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate having a conductive portion formed thereon, an insulating film having a through hole reaching the conductive portion, and formed in the through hole. A plug mainly formed of Ru, and a capacitor formed on the insulating film and electrically connected to the plug, wherein the capacitor is mainly composed of SrRuO ₃ and is directly connected to the plug; And a ferroelectric film formed on the electrode.

Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor substrate on which a conductive portion is formed, and a step of opening a through hole reaching the conductive portion in the insulating film. Ru in the through hole and on the insulating film
Forming a conductive film containing as a main component, heat-treating the conductive film, removing the conductive film outside the through-hole, and forming the conductive film containing Ru as a main component in the through-hole. Forming a plug on the insulating film, the step of forming a capacitor directly connected to the plug and including a lower capacitor electrode mainly composed of SrRuO ₃ and a ferroelectric film. It is characterized by.

According to the present invention, the structure of the lower capacitor electrode is complicated by employing a capacitor structure in which a plug mainly composed of Ru and a lower capacitor electrode mainly composed of SRO are directly connected. Without this, the oxidation of the plug can be effectively prevented. Since the oxidation of the plug can be prevented, the contact failure and the shape failure due to the oxidation of the plug can be prevented.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are process sectional views showing a method for manufacturing a capacitor having a COP structure according to an embodiment of the present invention.

First, FIG.
As shown in FIG. 1, a MIS transistor is formed on a silicon substrate 1 to form a CMOS structure. The figure shows only one transistor for simplicity. In the figure, 2 is a source / drain diffusion layer, 3 is a gate insulating film, 4 is a gate electrode, and 5 and 6 are silicon nitride films, respectively. A metal silicide layer may be formed on the surface of the source / drain diffusion layer 2.

Next, as shown in FIG. 2A, an SiO ₂ -based interlayer insulating film 7 such as a PSG film or a BPSG film is deposited on the entire surface of the transistor region by a CVD method, and the surface of the interlayer insulating film 7 is formed by CMP. (Chemical Mechanical Polishing)
Interlayer insulating film 7 which has been planarized by
A laminated insulating film 8 of a silicon oxide film and a silicon nitride film is deposited thereon by a CVD method. In the case of the present invention, the order of lamination of the silicon oxide film and the silicon nitride film may be any order.

Next, as shown in FIG. 1B, the interlayer insulating film 7 and the laminated insulating film 8 are etched and the source / drain 2
A barrier metal film 9 is formed on the entire surface so as to cover the inner surface (bottom surface and side surface) of the connection hole, and then a Ru film 10 serving as a Ru plug is formed as a barrier so as to fill the connection hole. It is formed on the metal film 9.

The barrier metal film 9 improves the adhesion between the Ru film 10 and the source / drain diffusion layer 2 and the adhesion between the Ru film 10 and the insulating films 7 and 8 on the side surfaces of the connection holes. And to prevent diffusion between them. That is, the barrier metal film 9 has a role of an adhesion film and a diffusion prevention film.

The material of the barrier metal film 9 is, for example, Ti
It is mainly made of nitrides such as N, TaN, TiAlN and TaSiN. The thickness of the barrier metal film 9 is 20-
It may be about 100 nm. Further, SiN also has a barrier effect of Ru. SiN is an insulator, but if the film thickness is reduced, electrical connection (electric continuity) can be obtained, and thus SiN can be used. A long-throw sputtering method, a CVD method, or the like is used as a method for forming the barrier metal film 9 so that the material can easily enter the connection holes, and the step coverage is improved.

Note that, depending on the state of diffusion and reaction between the Ru film 10 and the source / drain diffusion layer 2 (Si or metal silicide), the barrier metal film 9 is not formed directly (depending on the degree of a heating step in a later step), but is directly formed. It is also possible to form the Ru film 10. That is, the barrier metal film 9 may be formed only on the surface of the side surface of the plug to be formed later. In short, the barrier metal film 9 needs to be formed only on a necessary portion.

The MOCVD method is used for forming the Ru film 10.
To form a blanket Ru film. As a source material
Is, for example, Ru (EtCp)_TwoUse Ru (EtC
p) _TwoIs, for example, Ar and O_TwoPour into mixed gas. This place
In this case, typical deposition conditions are Ar / O_Two100/2 flow rate
Set to 00SCCM and set film formation temperature to around 300 ℃
I do.

In the case of the above film forming conditions, the Ru film 1 in the connection hole is formed.
During 0, a seam is formed. To eliminate seams,
The Ru film 10 is recrystallized by heat treatment. This allows
The barrier property (oxidation resistance) of the Ru film 10 against oxygen and the like can be improved.

The heat treatment is performed at a temperature of 500 ° C. or more, for example, for 10 minutes or more in a vacuum or an inert atmosphere (Ar
Or carried out in N _2). During the heat treatment, the Ru film 1
0, degassing and the like occur, and as a result, the resistance of the Ru film 10
Morphology is improved.

Next, as shown in FIG. 1C, the Ru film 10 and the barrier metal film 9 outside the connection hole are removed by the CMP method to form the Ru plug 10, and the surface is flattened. Although the barrier metal film 9 outside the connection hole is removed in the drawing, it may be left.

Next, as shown in FIG. 2D, a crystalline SRO (Sr
(RuO ₃ ) film 11 is deposited on the entire surface. The SRO film 11 is I
It is preferable to form in the nSitu crystallization step. In this case, the film is formed in Ar using an SRO ceramic target with the substrate temperature set to 500 ° C.

Here, when the substrate temperature is lower than 400 ° C.,
A second phase that does not crystallize exists in the SRO perovskite structure, causing deterioration of characteristics. On the other hand, when the substrate temperature is higher than 600 ° C., phenomena that cause characteristic deterioration such as diffusion at the interface between the SRO film 11 and the laminated insulating film 8 and at the interface between the SRO film 11 and the Ru plug 10 occur. Not desirable.

The thickness of the SRO film 11 is preferably around 50 nm. When the thickness exceeds 100 nm, SRO becomes RI
Since the E-processability is poor, the load on the processing process is increased, for example, it takes a long time for the RIE processing, and it is necessary to devise the processing conditions of the mask material for the RIE processing. From the viewpoint of miniaturization of the capacitor, the thickness of the SRO film 11 is desirably 50 nm or less.

Further, S is formed by using an ExSitu crystallization process.
When the RO film 11 is formed, it is performed as follows. First,
At room temperature, an amorphous SRO film is formed by sputtering in Ar using an SRO ceramic target. Next, the SRO film is crystallized at 600 ° C. in an oxygen stream by RTA.

In the case of ExSitu crystallization, the crystallinity is more likely to be deteriorated (residual Ru and Sr are more likely to be present) than in the case where a crystalline SRO film is formed by the high-temperature sputtering described above. Therefore, during the subsequent step of crystallization of the PZT film, Pb in the PZT film and Rb in the SRO film 11
A conductive oxide is formed by the diffusion reaction of u and Sr, and a leakage current of the capacitor is easily generated. In order to prevent such a leak current, the formation of the amorphous SRO film may be performed a plurality of times.

Other methods for reducing the leakage current include the following: the formation of a Ti film on the surface of the SRO film 11 and the modification of the surface of the SRO film 11 by heat treatment are also effective. . In this case, some SRO films 1
1 becomes STO (SrTiO ₃ ), and the crystallinity is improved. S
Since TO has better reduction resistance than SRO, damage to the interface can be avoided in the subsequent capacitor fabrication process and integration process.

Interdiffusion hardly occurs between the Ru plug 10 and the SRO film 11. Further, an oxide layer is not easily formed on the surface of the Ru plug 10. Therefore, the contact between the Ru plug 10 and the SRO film 11 becomes good.

When SRO and RuO ₂ are compared, SRO is thermodynamically more stable. Therefore, SRO and RuO
SRO is reduced at the interface between ₂ never RuO ₂ is formed.

Therefore, the Ru plug 10 and the SRO film 1
The case where the interface with 1 is oxidized is the case where oxygen diffuses from the outside. However, even if the surface of the Ru plug 10 in contact with the SRO film 11 is somewhat oxidized and a RuO ₂ layer (a region containing oxygen) is formed on the surface of the Ru plug 10, the RuO ₂ layer is a conductive oxide layer. Therefore, the electrical connection between the Ru plug 10 and the SRO film 11 does not matter. In particular, the thickness of the RuO ₂ layer is 100 n
There is no problem if it is less than m.

Since SRO is an oxide, SRO
Good adhesion to insulating films such as iO ₂ . Therefore, S
The adhesion between the RO film 11 and the portion other than the Ru plug 10, that is, the laminated insulating film 8 is also good. For this reason, SRO
Diffusion of oxygen in the lateral direction under the film 11 can be effectively suppressed.

Further, the lower capacitor electrode is connected to the SRO film 11.
, The miniaturization becomes easier as compared with the conventional technology constituted by the laminated film. Further, by using a single film, the plug structure is simplified, and the process is also simplified.

Next, as shown in FIG.
A PZT film 12 as a capacitor insulating film is formed on the substrate 1 by using an RF magnetron sputtering method.

Here, the Pb amount is increased by about 10%.
A ZT ceramic target is used. The composition of the target is Pb _1.10 La _0.05 Zr _0.4 Ti _O.6 O ₃ . P
A ZT ceramic target having a high density has a high sputter rate and has good environmental resistance to moisture and the like. Therefore, a ceramic sintered body having a theoretical density of 98% was used.

At the time of sputtering, the substrate temperature rises due to plasma and there is bombardment due to flying particles.
Evaporation and re-sputtering of Pb from the silicon substrate 1 occur, and the Pb amount in the PZT film 12 is likely to be lost. Excess Pb in the target has been added to compensate for it. Elements such as Zr, Ti, and La are taken into the PZT film 12 in substantially the same amount as the target composition, so that a composition having a desired composition ratio may be used.

The film forming conditions are as follows. For example, when the distance between the target and the substrate is 60 nm, the magnet is a rotary type, the size of the ceramic PZT target is 12 inches, and the input power is 1.0 to 1.5 kW, the sputtering is performed. Gas is Ar gas only, Ar gas pressure is 0.5-2.0 Pa,
The film formation time is about 5 minutes. In this case, the thickness 100-1
A 50 nm amorphous PZT film 12 is formed.

Although the sputtering method is used here as the method for forming the PZT film 12, a coating method such as a sol-gel method or a MOD method may be used.

Solution methods such as sol-gel method and MOD method (CS
In the PZT film forming process formed by the method D), the properties of the PZT film constituent elements such as Pb, Ti, and Zr are considered from the properties of the raw materials, ease of handling and stability, and the reactivity when mixed with other substances. Raw materials are selected first.

In many cases, lead acetate trihydrate is used for Pb, zirconium tetrapropoxide is used for Zr, and titanium tetraisopropoxide is used for Ti. A solution is first prepared. This solution can be stored for a long time by removing water sufficiently. Generally, the water component of the hydrate of lead acetate is removed.

When forming a film, water is added to the above solution to cause a polycondensation reaction. However, an M-0-M crosslinked structure is formed by a dehydration reaction and a dealcoholization reaction. The crosslinked state changes depending on the amount of water added at this time, the reaction time (holding time), the pH, the temperature, the concentration, and the like. Since a different amorphous state is formed as in the case of sputtering, the orientation, crystal grain properties, ferroelectric properties, leak current, fatigue properties, and the like change after crystallization into a PZT perovskite structure. The same applies to the MOD method.

Using Pb, Zr, Ti 2-ethylhexanoic acid, etc., and using an organic solvent xylene,
Prepare solution for D. In the case of the MOD method, a hydrolysis reaction does not occur, and the composition is applied on the substrate in that state (mixed state).

After the film is formed on the substrate, drying and desolvation are carried out at a low temperature of about 250 ° C. to form an amorphous PZT film. In the MOD method, since the raw material has a structure containing a large amount of C, H, and O, the film shrinks greatly during crystallization, and a few
To form a thick film, the coating and crystallization steps are repeated. For crystallization, RTA is often used in the same manner as sputtering. A perovskite single phase can be obtained by heat treatment at 750 ° C. for about 5 minutes.

In the PZT film formed by using such a solution method, the crystal grains are as small as 100 to several hundreds nm, and a grain structure not showing a columnar structure like a film formed by sputtering is often observed.

On the other hand, PZT, SBT
When a film or the like is formed, by optimizing the conditions, a capacitor having good step coverage for forming a three-dimensional capacitor can be obtained. In this case, Bi, Sr, Ba, and the like, which are constituent elements of the composite oxide, do not have a source material having a high vapor pressure.

In this embodiment, unlike the Pt electrode, the SRO film 11 is used as the lower capacitor electrode, so that the PRO is formed at the interface between the SRO film 11 and the PZT film 12.
Oxygen can be supplied to the oxygen vacancies of the ZT film 12. As a result, the fatigue characteristics of the PZT film 12 (a phenomenon of deterioration of the amount of polarization when the polarization inversion is repeated) are improved.

It should be noted that a thin Ti film, Zr film, Nb film, Ta film, or the like having a thickness of about 2 to 5 nm may be formed on the SRO film 11 as a PZT seed layer, and then the PZT film 12 may be formed. Good.

Before the PZT film 12 was formed, pre-sputtering was performed for about one hour under the same sputtering conditions in order to keep the target surface state, temperature and chamber environment constant.
The amount of Pb and the structural and electrical properties after crystallization are greatly changed by the pre-sputtering.

The amorphous PZT film on the SRO film is subjected to RTA (Rapid Thermal Anneal) to obtain a PZT film.
The T film was crystallized. Crystallization temperature is 550-700 ° C
The crystallization time was set to 10 seconds or more. When the crystal structure of the obtained PZT film was examined by X-ray diffraction, it was found to be a perovskite phase. The observation result of the microstructure confirmed that PZT particles having a diameter of 0.5 μm or less were formed on the SRO film.

Next, as shown in FIG. 2E, an SRO film 1 serving as an upper capacitor electrode is formed on the crystallized PZT film 12.
3 is formed by a DC magnetron sputtering method. In this case, it may be formed by high-temperature sputtering as described above, or may be formed by SRO by ExSitu crystallization at room temperature.
A film may be formed. The thickness of the upper SRO film 13 is 50
nm.

The conductive film serving as the upper capacitor electrode is made of a crystal.
Formed on the converted PZT film 12, the SRO film 13
Not only IrO_Two/ Ir laminated film, Ir film, Ru film, R
uO_Two / Ru laminated film, RuO_TwoIt is possible to use a membrane etc.
it can. Considering workability, a Ru-based film is desirable.

Conventionally, SRO has been used as a capacitor electrode.
Although a laminated film of the film and Pt has been formed, the Pt film has a catalytic action and forms active hydrogen, so that the PZT film is easily deteriorated. If there is a reductive damage in the integration process, remove the Pt film from the electrode and
Use a single membrane.

Finally, as shown in FIG.
The film 13, the PZT film 12, and the SRO film 11 are patterned by RIE, and thereafter, the upper capacitor electrode 13 and the PZT are subjected to annealing heat treatment to obtain ferroelectric characteristics.
The capacitor is completed by improving the adhesion to the T film 12 and the matching of the crystal. The RIE is oxygen, chlorine or A
r, in a mixed gas of chlorine. Also, the mask is SiO
Use a hard mask consisting of _two . SRO film 13, P
When performing RIE processing on the ZT film 12 and the SRO film 11,
Since it is not necessary to etch a noble metal film such as a Pt film or an Ir film, a processed shape close to vertical can be obtained. This allows
Miniaturization of the capacitor is facilitated.

As a result of examining the ferroelectricity of the ferroelectric capacitor thus obtained by the hysteresis characteristic of the charge amount Q-applied voltage V, the polarization amount was 2Pr (residual polarization sites × 2) when 2.5 V was applied. Shows about 30 uC / cm ² and 8 inches S
PZT with the same amount of polarization and coercive field over the entire surface of i-wafer
It turned out to be a membrane. The coercive voltage was as low as about 0.6 V.

Further, the fatigue characteristics of the ferroelectric capacitor were evaluated. Evaluation of the fatigue characteristics was performed using an array corresponding to an area of 50 μm × 50 μm. As a result, 1 × 10
^No change in polarization amount up to ¹² cycles and leakage current of 3 V
The value was as low as 10 ⁻⁸ A / cm ^{2 on} application.

The contact from the upper capacitor electrode 13 uses an ordinary LSI manufacturing process. That is, a step of depositing an interlayer insulating film, a step of opening a connection hole by RIE, a recovery annealing step in an oxygen atmosphere, and a wiring step are performed, and wiring is drawn from the capacitor. In the wiring process, the contact with the upper capacitor electrode 13 is TiN
Upper capacitor electrode 13 directly with film (barrier metal film)
Then, an Al wiring is formed.

Thus, according to the present embodiment, by using a Ru film which is conductive even if oxidized as a material of the Ru plug 10, it is possible to prevent oxidation of the Ru10 plug and associated contact defects and shape defects. Become. Further, the lower capacitor electrode structure is a Ru plug 10
And the lower capacitor electrode 11 are directly connected, and the capacitor does not include a noble metal film, so that miniaturization is easy.

The lower capacitor electrode (SRO film) 1
1 and the underlying laminated insulating film (silicon oxide film / silicon nitride film) 8 both contain oxygen as the same material, so that the adhesion between the lower capacitor electrode 11 and the laminated insulating film 8 is good. This prevents oxidation of the Ru plug 10 due to oxidizing species entering from the interface between the lower capacitor electrode 11 and the laminated insulating film 8.

Further, a lower capacitor electrode (SRO film)
Since the crystal structures of the PZT film 11 and the PZT film 12 are the same perovskite, there is no problem of reaction or mutual diffusion between them. Also, by using an SRO film as the lower capacitor electrode 11, fatigue characteristics, imprint characteristics,
Improvements in retention characteristics can be expected.

The present invention is not limited to the above embodiment. For example, in the above embodiment, FIG.
In the step (c), the barrier metal film 9 outside the connection hole is removed, but may be left. In this case, when the RIE processing is performed on the SRO film 13 and the like in the step of FIG. 2F, the RIE processing is also performed on the barrier metal film 9.

FIG. 4 shows a COP structure when the barrier metal film 9 is left. In the case of the COP structure shown in FIG. 4, since the barrier metal film 9 exists at the interface between the laminated insulating film 7 and the lower capacitor electrode 11, it is possible to more effectively prevent the oxidation from the lateral direction below the lower capacitor electrode 11. it can.

In the case of the COP structure shown in FIG. 4, if the recovery annealing performed after the step of taking contact from the upper capacitor electrode 13 is performed in an oxygen atmosphere in the same manner as in the related art, there is a disadvantage that the barrier metal film 9 is oxidized.

In order to solve such inconvenience, activation annealing may be performed in an inert gas such as nitrogen. As another method, an oxide film such as an Al ₂ O ₃ film or a TiO ₂ film or a nitride film such as a TiN film is used as an interlayer insulating film, and the capacitor is formed on the oxide film or the nitride film on the upper capacitor electrode 13. After forming an opening for making contact with the capacitor electrode 13 by RIE, recovery annealing may be performed in oxygen. Thereafter, the contact with the upper capacitor electrode 13 is directly connected to the upper capacitor electrode 13 with a TiN film (barrier metal film),
After that, an Al wiring is formed.

In the above embodiment, the case where the PZT film is used as the capacitor insulating film has been described.
Other ferroelectric films such as SBT films can be used.

In the above embodiment, the case of the plug electrically connected to the source / drain diffusion layer of the MIS transistor has been described. However, the present invention relates to the wiring electrically connected to the source / drain diffusion layer. The present invention can be similarly applied to a plug electrically connected to the plug.

The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, if the problem described in the section of the problem to be solved by the invention can be solved, the configuration in which the components are deleted is Can be extracted as an invention. In addition, various modifications can be made without departing from the scope of the present invention.

[0076]

As described above, according to the present invention, a semiconductor device which can easily realize a fine COP structure and a method for manufacturing the same can be realized.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method of manufacturing the semiconductor device of the embodiment, following FIG. 1;

FIG. 3 is an exemplary sectional view showing a modification of the COP structure of the embodiment;

FIG. 4 is a sectional view showing a conventional COP structure.

FIG. 5 is a sectional view showing another conventional COP structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Source / drain diffusion layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Silicon nitride film (gate upper insulating film) 6 ... Silicon nitride film (gate side wall insulating film) 7 ... Interlayer insulating film 8 ... Lamination Insulating film 9 ... Barrier metal film 10 ... Ru plug 11 ... Lower capacitor electrode (SRO film) 12 ... PZT film (capacitor insulating film) 13 ... Upper capacitor electrode (SRO film)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/316 H01L 21/316 P 27/10 444B F term (Reference) 5F058 BA11 BD02 BD04 BD05 BD10 BF02 BF06 BF12 BF46 5F083 FR02 GA21 JA15 JA38 JA40 JA43 JA45 MA05 MA06 MA17 PR34 PR40

Claims (10)

[Claims] A semiconductor substrate having a conductive portion formed thereon; an insulating film having a through hole reaching the conductive portion; a plug formed in the through hole and containing Ru as a main component; And a capacitor electrically connected to the plug. The capacitor includes SrRuO ₃ as a main component, an electrode directly connected to the plug, and a ferroelectric formed on the electrode. And a film. 2. The semiconductor device according to claim 1, wherein said conductive portion is a source / drain diffusion layer of a MIS type transistor or a wiring electrically connected to said source / drain diffusion layer. . 3. The semiconductor device according to claim 1, wherein a nitride film is formed on at least part of the side and bottom surfaces of said plug. 4. The semiconductor device according to claim 3, wherein said nitride film is also formed at an interface between said insulating film and said lower capacitor electrode. 5. The material of said nitride film is TiN, TaN,
The semiconductor device according to claim 4, wherein the semiconductor device is TiAlN, TaSiN, or SiN. 6. The semiconductor device according to claim 1, wherein a region of said plug contacting said electrode contains oxygen. 7. The semiconductor device according to claim 6, wherein the thickness of the region containing oxygen is 100 nm or less. 8. The semiconductor device according to claim 1, wherein the capacitor does not include a metal film containing a noble metal as a main component. 9. The semiconductor device according to claim 8, wherein said noble metal is Pt or Ir. 10. A step of forming an insulating film on a semiconductor substrate on which a conductive portion is formed, a step of opening a through hole reaching the conductive portion in the insulating film, and forming a through hole in the through hole and on the insulating film. Forming a conductive film containing Ru as a main component; performing a heat treatment on the conductive film; removing the conductive film outside the through-hole; Forming a plug to be directly connected to the plug on the insulating film;
A method of manufacturing a semiconductor device, comprising: forming a capacitor including a lower capacitor electrode mainly composed of uO ₃ and a ferroelectric film.