JPH11135749A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage circuit for preferably allowing hydrogen atoms to surely reach an interface between a gate electrode and a semiconductor substrate by preventing increase in the leakage current of a metal oxide film and the deterioration of a dielectric polarization characteristic due to heat treatment in a hydrogen atmosphere. SOLUTION: The lower electrode of a capacitor, consisting of a titanium nitride film 14, a ruthenium film 15 and a ruthenium oxide film 16, is provided on a part, and the titanium silicide layer 13 of a silicon nitride film 11. In addition, a metal oxide film 17 which is the capacitance insulated film of the capacitor is provided by covering the capacitor layer electrode and a titanium nitride film 18 to be a capacitor upper electrode is provided by covering this film 17. In addition, the film 11 and the titanium nitride film are provided only within a memory cell array region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which one memory cell is composed of a transistor and a capacitor, and which has a plurality of such memory cells. The present invention relates to a semiconductor memory device having an insulating film and preventing deterioration of dielectric characteristics of the capacitive insulating film.

[0002]

2. Description of the Related Art High integration of a semiconductor memory device, for example, a dynamic random access memory (DRAM) comprising one transistor and one capacitor has been advanced year by year. As the degree of integration increases, the area of the memory cell is reduced and the size of the capacitor is also reduced. The capacitance value of the capacitor is proportional to the surface area of the capacitor and the relative dielectric constant of the capacitive insulating film, and is inversely proportional to the thickness of the capacitive insulating film. When the capacitance value of the capacitor decreases, soft errors are likely to occur, and the reliability is impaired. Therefore, in order to increase the surface area of the capacitor, a stack type capacitor, a trench type capacitor, a cylindrical type capacitor, and the like, which can use the side surface of the electrode, have been used instead of the conventionally used planar type capacitor. Further, from the viewpoint of increasing the relative dielectric constant of the capacitor insulating film, the material of the capacitor insulating film is changed from a silicon oxide film (SiO ₂ ) to a silicon nitride film (Si ₃ N ₄ ). Further, a tantalum pentoxide film (Ta ₂ O ₅ ) having a higher relative dielectric constant than these has been used, and recently, a metal oxide film having a higher relative dielectric constant, such as barium strontium titanate and titanic acid, has been used. Films made of lead or the like have been used. It has been reported that the relative dielectric constant of these metal oxide films is several tens to several hundred times that of a silicon oxide film.

[0003] In a normal silicon-based semiconductor memory device manufacturing process, after a wiring or the like is formed, a heat treatment in a hydrogen atmosphere is performed as a final process. This is MO
This is performed to saturate the dangling bonds of covalent bonds at the interface between the gate insulating film of the S transistor and the semiconductor substrate with hydrogen atoms to compensate for the interface state.

However, when a metal oxide film is used as a capacitor insulating film, hydrogen treatment causes hydrogen atoms to diffuse into the capacitor insulating film, and the hydrogen atoms in the capacitor insulating film move when an electric field is applied. To generate space charge. This allows
There is a drawback that the dielectric characteristics deteriorate, the leak current increases, and the life is shortened.

Therefore, a method of manufacturing a semiconductor memory device that suppresses deterioration of dielectric characteristics due to hydrogen atoms has been proposed (JP-A-8-8404). FIG.
FIG. 14 is a cross-sectional view showing a method for manufacturing the semiconductor storage device described in Japanese Patent Publication No. 04-2004. In the conventional method of manufacturing a semiconductor memory device described in this publication, first, a silicon substrate 20
1, a field oxide film 202, a gate oxide film 212,
After forming the gate electrode 203, the diffusion layer 204, and the first interlayer insulating film 205, a lower electrode 206, a capacitor insulating film 207, and an upper electrode 208 are formed over the first interlayer insulating film 205. Next, after forming a second interlayer insulating film 209 covering the entire surface, an opening reaching the upper electrode 208 and an opening reaching the diffusion layer 204 are formed. And
A heat treatment at 300 to 800 ° C. is performed in an atmosphere of an oxygen gas or an inert gas or a mixed gas thereof, and the heat treatment is performed in an atmosphere of a hydrogen gas or a mixed gas of a hydrogen gas and an inert gas.
Heat treatment at 50 to 500 ° C. is performed, and heat treatment at 300 to 450 ° C. is performed in an atmosphere of an oxygen gas, an inert gas, or a mixed gas thereof. After that, the diffusion barrier film 211 and the electrode wiring 210 are buried in the opening to complete the semiconductor memory device.

In this conventional technique, hydrogen treatment of a transistor is performed by a second heat treatment, and hydrogen atoms in the capacitor insulating film are released by a third heat treatment. Thus, the hydrogen density in the capacitive insulating film is set to 10 ¹¹ (units / cm ⁻² ) or less.

[0007]

However, even in the above-mentioned prior art, there is a problem that the deterioration of the capacitance insulating film is still caused when the hydrogen partial pressure of the mixed gas of the hydrogen gas and the inert gas is raised.

The present invention has been made in view of the above problems, and can prevent an increase in leak current of a metal oxide film and a deterioration in dielectric polarization characteristics due to a heat treatment in a hydrogen atmosphere. It is an object to provide a semiconductor memory device in which hydrogen atoms can reliably reach an interface between a gate electrode and a semiconductor substrate.

[0009]

According to the present invention, there is provided a semiconductor memory device comprising: a semiconductor substrate; a memory cell including a transistor and a capacitor formed on the semiconductor substrate; Wherein the capacitor has a lower electrode, an upper electrode having a first titanium nitride film, and a capacitor insulating film formed between the lower electrode and the upper electrode. And characterized in that:

In the present invention, since the capacitance insulating film of the capacitor has a structure sandwiched between the silicon nitride film and the titanium nitride film of the upper electrode, the hydrogen invading the semiconductor memory device by the heat treatment in the hydrogen atmosphere. Before the atoms reach the capacitance insulating film, the atoms are blocked from passing through the capacitance insulating film by the silicon nitride film or occluded by the titanium nitride film. For this reason, reduction of the capacitive insulating film by hydrogen atoms is prevented, so that an increase in leak current and deterioration of dielectric polarization characteristics are prevented.

In the present invention, a memory cell array region having a plurality of the memory cells may be provided, and the silicon nitride film may be provided only in the memory cell array region. Further, the first titanium nitride film may be provided only in the memory cell array region.

By forming the silicon nitride film and the titanium nitride film only in the memory array region, during heat treatment in a hydrogen atmosphere, hydrogen atoms penetrate from outside the memory cell array region into the semiconductor memory device, and the gate electrode is formed. And the semiconductor substrate can be reliably reached.

The memory cell may include a contact hole having an opening in contact with the transistor and the capacitor, a conductor layer buried in the contact hole, and a gap between the lower electrode and the conductor layer. And a second titanium nitride film provided. Further, it is preferable that the second titanium nitride film covers the opening, and an area of the second titanium nitride film is smaller than an area of the lower electrode. By covering the opening of the contact hole with the second titanium nitride film, diffusion of hydrogen atoms into the capacitor insulating film can be further suppressed.

[0014] The contact hole may be located below the lower electrode.

[0015] The semiconductor device may further include a titanium silicide layer provided between the conductor layer and the second titanium nitride film. By providing the titanium silicide layer, the resistance between the transistor and the capacitor can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The inventors of the present invention have conducted intensive experiments and researches to solve the above-mentioned problems. As a result, the structure of a semiconductor memory device is isolated from hydrogen atoms by a silicon nitride film and a titanium nitride film. With such a structure, it has been found that deterioration of characteristics of a metal oxide film used as a capacitor insulating film can be prevented.

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings.
FIG. 1 is a sectional view showing a memory cell of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device according to the present embodiment is a DRAM on which a stacked capacitor is mounted.

In this embodiment, two field oxide films 2 are provided on a silicon substrate 1. And
On the surface of the silicon substrate 1 between the field oxide films 2, three diffusion layers 5 are provided. A gate oxide film 3 and a gate electrode 4 are provided on the silicon substrate 1 between the diffusion layers 5. On these, a first interlayer insulating film 7, a second interlayer insulating film 10, and a silicon nitride film 11 are sequentially provided. In the first interlayer insulating film 7, the second interlayer insulating film 10, and the silicon nitride film, a capacity contact hole 12 reaching the diffusion layer 5 located at both ends is formed, and a polycrystal doped with impurities is formed. A silicon layer is buried. Note that a titanium silicide layer 13 is buried in a surface portion of the polycrystalline silicon layer. A bit line 9 is connected to the diffusion layer 5 located at the center via a bit contact hole 8.

Each titanium silicide layer 13 has
A capacitor lower electrode composed of the second titanium nitride film 14, the ruthenium film 15, and the ruthenium oxide film 16 is connected. Further, the metal oxide film 1 covering the lower electrode of the capacitor
7 is provided, and a first covering metal oxide film 17 is provided.
A titanium nitride film 18 is provided. The first titanium nitride film 18 serves as a capacitor upper electrode, and the metal oxide film 1
7 becomes a capacitive insulating film. Then, a third interlayer insulating film 19 covering the first titanium nitride film 18 is provided.

In the semiconductor memory device thus configured, the metal oxide film 17 is covered with the silicon nitride film 11 and the titanium nitride films 14 and 18. The silicon nitride film has a property of blocking the passage of hydrogen, and the titanium nitride film has a property of absorbing hydrogen. Therefore, even if heat treatment is performed in a hydrogen atmosphere, the metal oxide film 1
7 is prevented from being reduced by hydrogen, and an increase in leak current is prevented.

In this embodiment, in the memory cell array having a plurality of the above-mentioned memory cells, the silicon nitride film 11 is provided on the entire surface of the memory cell array except for the portion where the capacitor contact hole 12 is formed.
The first titanium nitride film 18 is provided on the entire surface of the memory cell array.

FIG. 2 is a plan view showing a chip of the semiconductor memory device according to the first embodiment of the present invention. In the semiconductor memory device chip having the above-described memory cell array,
Memory cell array region 1 in which a memory cell array is formed
01 and the sense amplifier region 102 provided therearound.
And a word driver area 103. In this embodiment, the silicon nitride film 11 and the first titanium nitride film 18 are formed only in the memory cell array region 101, and are provided in the peripheral circuits, the sense amplifier region 102, the word driver region 103, and other array portions. Not. This is because if the silicon nitride film 11 and the first titanium nitride film 18 are provided on the entire surface of the chip, hydrogen atoms do not reach the interface between the gate oxide film 3 and the semiconductor substrate 1 during heat treatment in a hydrogen atmosphere. It is.

Therefore, in the chip configured as described above, the hydrogen atoms are supplied from the array portion outside the memory array portion 101 by the heat treatment in the hydrogen atmosphere, and the hydrogen atoms are supplied to the second interlayer insulating film 10 and the second interlayer insulating film 10. Through one interlayer insulating film 7, it can reach the interface between gate oxide film 3 and semiconductor substrate 1.

Next, a method of manufacturing the above-described semiconductor memory device will be described. 3A to 3C are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps. First, as shown in FIG.
For example, an element isolation field oxide film 2 having a thickness of 300 nm is selectively formed on the surface of a p-type silicon substrate 1 by a thermal oxidation method. Next, a gate oxide film 3 having a thickness of 10 nm is formed.
Is formed between the field oxide films 2 by a thermal oxidation method. A polycrystalline silicon film doped with phosphorus or an amorphous silicon film doped with phosphorus is entirely
It is formed with a thickness of 00 nm. Next, the gate electrode 4 is formed by removing unnecessary portions of the polycrystalline silicon film or the amorphous silicon film by photolithography and anisotropic dry etching. Note that the gate electrode is not limited to a single-layer silicon film,
A stacked film of a silicon film and a tungsten silicide film or a stacked film of a silicon film and a titanium silicide film may be used.

Next, a diffusion layer 5 is formed on the surface of the silicon substrate 1 by ion-implanting phosphorus with an acceleration energy of, for example, 30 (keV) and a dose of 3 × 10 ¹³ (cm ⁻² ). After that, a first interlayer insulating film 7 having a thickness of 500 nm made of a PSG film or a BPSG film is formed by a CVD method. A bit contact hole 8 reaching the diffusion layer 5 is formed in the first interlayer insulating film 7 by photolithography and anisotropic dry etching.
Next, a polycrystalline silicon film doped with phosphorus is formed on the entire surface by the CVD method, and unnecessary portions are etched back by the anisotropic dry etching technique to bury the polycrystalline silicon layer in the bit contact hole 8. I do.
Then, a tungsten silicide film is formed to a thickness of 100 nm over the entire surface by sputtering, and unnecessary portions are removed by photolithography and anisotropic dry etching to form bit lines 9.

Next, a PSG film or a BPS
Second interlayer insulating film 10 made of G film and having a thickness of 400 nm
Is formed on the entire surface. Further, a film thickness of 100
A silicon nitride film 11 of nm is formed on the second interlayer insulating film 10. A capacitive contact hole 12 reaching the diffusion layer 5 is formed in the silicon nitride film 11 and the second interlayer insulating film 10 by photolithography and anisotropic dry etching. Next, a polycrystalline silicon film doped with phosphorus is formed on the entire surface by a CVD method, and unnecessary portions are etched back by anisotropic dry etching technology to bury the polycrystalline silicon layer in the capacity contact hole 12. After that, a film thickness of 5
A 0 nm titanium film 20 is formed.

Next, as shown in FIG. 3B, the surface of the polycrystalline silicon layer buried in the capacity contact hole 12 and the titanium film are heated by a lamp at 650 ° C. for 30 seconds in a nitrogen atmosphere. 20 to form a titanium silicide layer 13 above the capacitor contact hole 12. Then, the unreacted titanium film 20 and the nitrided titanium film 20 are removed. Next, a second titanium nitride film 14 having a thickness of 100 nm, a ruthenium film 15 having a thickness of 100 nm, and a ruthenium oxide film 16 having a thickness of 400 nm are sequentially formed by a sputtering method. Thereafter, an oxide film (not shown) having a thickness of 400 nm is formed on the entire surface. Unnecessary portions of the oxide film are removed by a photolithography technique and an anisotropic dry etching technique to leave the oxide film only in a region where a lower electrode of the capacitor is to be formed. Then, using this oxide film as a mask, the ruthenium oxide film 16, the ruthenium film 15, and the second titanium nitride film 1 are used.
Unnecessary portions of No. 4 are removed by anisotropic dry etching. Next, the oxide film is removed with hydrofluoric acid or the like. Thereafter, a metal oxide film 17 made of barium, strontium, titanium, and oxide and having a thickness of 50 nm is formed on the entire surface by CVD.

Next, as shown in FIG. 3C, a first titanium nitride film 18 having a thickness of 150 nm is formed on the metal oxide film 17 by a CVD method. This first titanium nitride film 18
Becomes the upper electrode of the capacitor. Thereafter, an oxide film (not shown) is formed to a thickness of 400 nm, and unnecessary portions of the oxide are removed by photolithography and anisotropic dry etching, thereby forming a region where the upper electrode of the capacitor is to be formed. An oxide film is left only in the memory cell array region. Since the memory cell shown in FIG. 3C is in the memory cell array region, an oxide film remains on the entire surface in the figure. Then, unnecessary portions of the first titanium nitride film 18, the metal oxide film 17, and the silicon nitride film 11 are removed by anisotropic dry etching using the oxide film as a mask. Further, the oxide used as the mask is removed with hydrofluoric acid or the like. Then, a silicon oxide film having a thickness of 400 nm is formed as the third interlayer insulating film 19 by a CVD method. Thus, the semiconductor memory device according to the first embodiment shown in FIG. 1 is completed.

Next, a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention will be described. FIG. 4 (a)
7A and 7B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention in the order of steps. In the method of manufacturing the semiconductor memory device according to the present embodiment, the capacitance contact hole 1 is formed by the same steps as in the first embodiment.
After the formation of 2, a process is performed until a polycrystalline silicon layer doped with phosphorus is formed on the entire surface. Next, FIG.
As shown in FIG. 3, the polycrystalline silicon layer is etched back over the entire surface and
The polycrystalline silicon layer in the capacitor contact hole 12 is etched to a depth of 0 nm. Next, a titanium film 30 having a thickness of 50 nm and a thickness of 1
A second titanium nitride film 31 having a thickness of 00 nm is sequentially formed. Thereby, the titanium film 30 is also formed in the capacity contact hole 12.
Then, a second titanium nitride film 31 is formed. Thereafter, the surface of the polycrystalline silicon layer buried in the capacity contact hole 12 reacts with the titanium film 30 by performing lamp heating at a temperature of 650 ° C. for 30 seconds in a nitrogen atmosphere to form an upper portion of the polycrystalline silicon layer. A titanium silicide layer 13 is formed.

Next, as shown in FIG. 4B, the second step is performed until the surface of the silicon nitride film 11 is exposed by the CMP technique.
The titanium nitride film 31 and the titanium film 30 are polished. As a result, the titanium nitride layer 31 remains on the capacitor contact hole 12. Further, a ruthenium film 15 and a ruthenium oxide film 16 are sequentially formed by a sputtering method.
Thereafter, by the same steps as in the first embodiment, the electrodes of the capacitor were formed, the first titanium nitride film 18 and the metal oxide film 17 were formed only in the memory cell array region, and the silicon nitride film 11 was left. Thereafter, the semiconductor memory device is completed by the same steps as in the conventional method.

The semiconductor memory device according to the present embodiment manufactured as described above has the structure shown in FIG. 4B, and the metal oxide film 17 is a silicon nitride film 11 and a titanium nitride film 18.
And 31. Further, similarly to the first embodiment, the silicon nitride film 11 and the first titanium nitride film 18 are formed only in the memory cell array region.

Therefore, even if heat treatment is performed in a hydrogen atmosphere, reduction of the metal oxide film 17 by hydrogen is prevented, and an increase in leak current is prevented. Further, since the first titanium nitride film 18 and the silicon nitride film 11 are not formed outside the memory cell array region,
Hydrogen atoms can reach the interface between gate oxide film 3 and semiconductor substrate 1 through second interlayer insulating film 10 and first interlayer insulating film 7.

[0033]

As described in detail above, according to the present invention,
Due to the property of blocking the passage of hydrogen of the silicon nitride film and the property of absorbing hydrogen of the titanium nitride film, the leakage current increases due to the heat treatment in a hydrogen atmosphere of the metal oxide film used as the capacitive insulating film, and the dielectric polarization property is reduced. Deterioration can be prevented. As a result, it is possible to prevent the storage time of the DRAM from being shortened, thereby improving the reliability of the operation of the DRAM. Further, since it is not necessary to shorten the refresh cycle, an increase in the standby current can be prevented and the performance can be improved. Further, by forming the silicon nitride film and the titanium nitride film only in the memory array region, hydrogen atoms can enter the semiconductor memory device from outside the memory cell array region during heat treatment in a hydrogen atmosphere. ,
It is possible to reliably reach the interface between the gate electrode and the semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a memory cell of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a chip of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor memory device described in Japanese Patent Application Laid-Open No. 8-8404.

[Explanation of symbols]

 Reference Signs List 1: silicon substrate 2: field oxide film 3: gate oxide film 4: gate electrode 5: diffusion layer 7, 10, 19; interlayer insulating film 8; bit contact hole 9; bit line 11; silicon nitride film 12; 13; titanium silicide films 14, 18, 31; titanium nitride film 15; ruthenium film 16; ruthenium oxide film 17; metal oxide films 20, 30; titanium film 101; memory cell array region 102; sense amplifier region 103;

Claims (7)

[Claims] A semiconductor substrate, a memory cell including a transistor and a capacitor formed on the semiconductor substrate, and a silicon nitride film formed between the semiconductor substrate and the capacitor; The semiconductor memory device according to claim 1, wherein the capacitor includes a lower electrode, an upper electrode having a first titanium nitride film, and a capacitor insulating film formed between the lower electrode and the upper electrode. 2. The semiconductor memory device according to claim 1, further comprising a memory cell array region having a plurality of said memory cells, wherein said silicon nitride film is provided only in said memory cell array region. . 3. The semiconductor memory device according to claim 2, wherein said first titanium nitride film is provided only in said memory cell array region. 4. The memory cell, comprising: a contact hole having an opening in contact with the transistor and the capacitor; a conductive layer buried in the contact hole;
4. The semiconductor memory device according to claim 1, further comprising a second titanium nitride film provided between said lower electrode and said conductor layer. 5. The semiconductor memory according to claim 4, wherein the second titanium nitride film covers the opening, and an area of the second titanium nitride film is smaller than an area of the lower electrode. apparatus. 6. The semiconductor memory device according to claim 1, wherein said contact hole is located below said lower electrode. 7. The semiconductor memory device according to claim 4, further comprising a titanium silicide layer provided between said conductor layer and said second titanium nitride film. .