JPH11274431A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology wherein a capacitor with a sufficient capacity is realized in a limited flat area. SOLUTION: A titanium nitride film 56 constitutes a lower part electrode 60, which is etched to form a irregularity 80 on its surface for a larger surface area. An upper part electrode 62 is formed on the lower part electrode 60 through a capacity insulating film comprising a tantalic oxide film 61 of large permittivity, constituting a capacitor (information-accumulation capacity element) C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a DRAM (Dynami
The present invention relates to a technology effective when applied to the realization of a capacitor that secures a sufficient capacity in a limited plane area in a random access memory (c).

[0002]

2. Description of the Related Art A memory cell of a DRAM is arranged at an intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. Insulator Semiconductor Fie
ld Effect Transistor) and one information storage capacitor (capacitor) connected in series to the ld effect transistor. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. Have been. The bit line is arranged above the memory cell selecting MISFET, and is electrically connected to one of a source and a drain shared by two memory cell selecting MISFETs adjacent in the extending direction. The capacitor is also arranged above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

The capacity of DRAMs has been increasing with the improvement of semiconductor manufacturing technology. Recently, DRAMs having a large capacity of 256 megabits have been developed. In order to manufacture such a large-capacity DRAM, it is necessary to miniaturize the element, and the area of the memory cell is inevitably reduced. For this reason, it is difficult to sufficiently secure the capacitance of the capacitor. In order to increase the capacitance of the capacitor, the planar area for forming the capacitor on the semiconductor substrate (here, the planar area refers to the projected area on the substrate surface) may be increased, but the area of the memory cell is reduced. This is not possible given the fact that That is, the capacitor cannot be simply enlarged in a planar manner. Therefore, it is necessary to increase the surface area of the capacitor by forming the capacitor three-dimensionally. In addition, it is necessary to select a material having a large dielectric constant as the capacitance insulating film forming the capacitor in order to increase the capacitance of the capacitor.

[0004] In response to such demands, examples of techniques for increasing the capacity of a capacitor are disclosed in Japanese Patent Application Laid-Open Nos. 1-187847 and 64-42161. In these publications, in a DRAM having a stacked capacitance type (STC) capacitor, the surface area of a lower electrode made of polycrystalline silicon constituting the capacitor is made uneven to increase the electrode area. The capacity is increased by forming a capacitor by forming an upper electrode through a capacity insulating film made of a silicon oxide film and a silicon nitride film.

In this case, in order to form irregularities on the surface of the lower electrode, polycrystalline silicon is formed by CVD (Chemical Vapor Depth).
Osition) A phenomenon in which granular silicon grows in the initial stage depending on the surface condition of the base when forming a film, or a phenomenon in which unevenness occurs when wet etching of polycrystalline silicon does not proceed uniformly. Utilizing the above, the processing conditions under which the unevenness of the surface of the lower electrode becomes large are selected and formed.

[0006]

However, the above-mentioned prior art has the following problems.

[0007] In the technology described in JP-A-1-187847 and JP-A-64-42161,
Materials consisting of a silicon oxide film and a silicon nitride film are used for the capacitor insulating film that composes the capacitor, but since these materials have a small dielectric constant, it is impossible to secure a sufficient capacitance in a limited plane area. Have difficulty. In this regard, recently, tantalum oxide (Ta ₂ O ₅ ) having a large dielectric constant is used as the capacitive insulating film.

[0008] Here, tantalum oxide is formed by a CVD method excellent in embedding property and step coverage, but when tantalum oxide is simply deposited by the CVD method (so-called as-deposited state), there are many oxygen defects. Since a film is formed, a leak current becomes remarkable. For this,
Heat treatment in oxidizing atmosphere (oxidation reforming treatment) for the purpose of improving the film quality of tantalum oxide after film deposition by CVD method
Is required. However, the lower electrode made of polycrystalline silicon, which is the base, is oxidized by this oxidation reforming treatment, and a silicon oxide film (SiO
₂ ) is formed. This silicon oxide film
Since the dielectric constant is low and this silicon oxide film also acts as a part of the capacitive insulating film, the apparent dielectric constant of the entire capacitive insulating film is lowered, and the film thickness is increased. There is a problem that it is difficult to increase the capacity.

Further, in the conventional technique described in the above publication, when a process for forming an unevenness on the surface of the lower electrode to increase the electrode area is performed, a processing condition under which the unevenness on the surface of the lower electrode becomes large is set. It is not easy to select, and as a result, the manufacturing process becomes complicated, so that there is a problem that an increase in manufacturing cost cannot be avoided.

An object of the present invention is to provide a technique capable of realizing a capacitor which secures a sufficient capacitance in a limited plane area.

Another object of the present invention is to provide a technique capable of realizing a capacitor having a lower electrode having excellent oxidation resistance.

It is another object of the present invention to provide a technique capable of securing a sufficient capacitance in a limited plane area and realizing a capacitor having a lower electrode having excellent oxidation resistance.

Another object of the present invention is to provide a semiconductor integrated circuit device in which a refresh margin is increased by increasing a stored charge amount by realizing a capacitor which secures a sufficient capacitance in a limited plane area. To provide.

Another object of the present invention is to provide a semiconductor integrated circuit device which realizes low voltage and low power by increasing the amount of stored charge.

Another object of the present invention is to provide a technique for preventing collapse of a capacitor electrode during a capacitor manufacturing process.

It is another object of the present invention to provide a technique for simplifying a process of forming irregularities on the surface of a lower electrode and realizing a capacitor which secures a sufficient capacitance in a limited plane area. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention provides a memory cell selecting MISF formed on a main surface of a semiconductor substrate.
ET, a lower electrode connected in series to the memory cell selecting MISFET and connected to a source or drain of the memory cell selecting MISFET, a capacitive insulating film formed in contact with the lower electrode, and the capacitive insulating film. The lower electrode is formed so as to cover the lower electrode.

(2) In the semiconductor integrated circuit device according to the present invention, the metal film is a transition metal film, and the metal compound film is a compound film of the transition metal film. .

(3) The semiconductor integrated circuit device of the present invention
In the semiconductor integrated circuit device according to (1) or (2), the metal film is a titanium film, a tungsten film, a ruthenium film, or an iridium film, and the metal compound film is a titanium nitride film, a tungsten nitride film, a ruthenium oxide film, It is an iridium oxide film.

(4) The semiconductor integrated circuit device of the present invention
(1) In the semiconductor integrated circuit device according to any one of (1) to (3), the lower electrode includes an oxide film of the metal film formed on a surface thereof.

(5) The semiconductor integrated circuit device of the present invention
(1) In the semiconductor integrated circuit device according to any one of (1) to (4), the lower electrode includes a ruthenium film or a ruthenium oxide film formed on a surface of the metal film, the metal compound film, or the oxide film. .

(6) The semiconductor integrated circuit device of the present invention
(1) In the semiconductor integrated circuit device according to any one of (1) to (5), the lower electrode is formed in a cylindrical shape having an opening above.

(7) The semiconductor integrated circuit device of the present invention
(6) In the semiconductor integrated circuit device described in (6), a reinforcing member is formed on an outer wall of the cylindrical lower electrode.

(8) The semiconductor integrated circuit device of the present invention
(6) In the semiconductor integrated circuit device according to (7), the semiconductor integrated circuit device is a memory cell selecting M.
Including a plug conductor connected to the source or drain of the ISFET, a titanium silicide film is formed at an interface of the plug conductor in contact with the lower electrode.

(9) The semiconductor integrated circuit device according to the present invention
In the semiconductor integrated circuit device according to any one of (1) to (8), the capacitance insulating film is a tantalum oxide film or a BST.
The upper electrode is a single-layer film selected from titanium nitride, ruthenium or ruthenium oxide, or a laminated film thereof.

(10) The semiconductor integrated circuit device of the present invention
(1) In the semiconductor integrated circuit device according to any one of (1) to (9), the average value h of the height difference of the unevenness of the lower electrode is 0.5d ≦ h, where d is the thickness of the capacitive insulating film. ≦ 5d
Is selected in the range that satisfies.

(11) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) a MISFET for selecting a memory cell and a MISFET for selecting the memory cell on a main surface of a semiconductor substrate;
Forming an insulating film covering the insulating film, and depositing a metal film or a metal compound film having a polycrystalline structure on the insulating film, (b)
(C) forming a lower electrode by patterning the metal film or the metal compound film to form irregularities on the surface of the metal film or the metal compound film by etching, and (c) capacitively insulating the surface of the lower electrode. (C) forming an upper electrode on the capacitive insulating film after depositing a film, and (d) forming an upper electrode on the capacitive insulating film; and an information storage capacitive element comprising the lower electrode, the capacitive insulating film, and the upper electrode. Is formed.

(12) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) a MISFET for selecting a memory cell and a MISFET for selecting the memory cell on a main surface of a semiconductor substrate;
Forming an insulating film covering the insulating film, and depositing a metal film or a metal compound film having a polycrystalline structure on the insulating film, (b)
After patterning the metal film or metal compound film,
Forming a lower electrode by forming irregularities on the surface by etching the patterned metal film or metal compound film, and (c) depositing a capacitor insulating film on the surface of the lower electrode, (D) forming an upper electrode on the capacitive insulating film,
A step of forming an information storage capacitance element including the lower electrode, the capacitance insulating film, and the upper electrode.

(13) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) forming a memory cell selecting MISFET on a main surface of a semiconductor substrate;
Forming an insulating film having an opening on the ET, and then depositing a metal film or a metal compound film having a polycrystalline structure in the opening of the insulating film so as not to fill the opening, (b) (C) forming irregularities on the surface of the metal film or the metal compound film by etching the metal film or the metal compound film, and then removing the metal film or the metal compound film on the upper surface of the insulating film to form a cylindrical lower electrode; A) a step of oxidizing and reforming the capacitive insulating film after depositing a capacitive insulating film on the surface of the lower electrode; (d) forming an upper electrode on the capacitive insulating film; The method includes a step of forming an information storage capacitor composed of an upper electrode.

(14) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) forming a memory cell selecting MISFET on a main surface of a semiconductor substrate;
Forming a first insulating film having an opening on the ET, and then depositing a metal film or a metal compound film having a polycrystalline structure in such a thickness that the opening is not filled in the opening of the first insulating film. (B) after embedding a second insulating film in the opening of the first insulating film, removing the metal film or the metal compound film on the second insulating film and the first insulating film;
Etching the first insulating film and the second insulating film to expose a cylindrical structure having an opening above the metal film or the metal compound film; and (c) etching the surface of the cylindrical structure. Forming a cylindrical lower electrode by forming irregularities on the surface of the lower electrode, (d) depositing a capacitive insulating film on the surface of the lower electrode, and then subjecting the capacitive insulating film to oxidative reforming; A) forming an upper electrode on the capacitive insulating film and forming an information storage capacitive element including the lower electrode, the capacitive insulating film, and the upper electrode.

(15) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the method for manufacturing a semiconductor integrated circuit device according to any one of claims 11 to 14, the unevenness on the surface of the lower electrode may be as follows: The metal film or the metal compound film is formed using a difference in etching rate at a crystal grain boundary.

(16) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of claims 11 to 15, wherein the unevenness on the surface of the lower electrode is excessive. It is formed using a wet etching solution containing hydrogen oxide water.

(17) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a semiconductor integrated circuit device according to any one of claims 11 to 16, the metal film or the metal compound film is formed. The metal is a transition metal.

(18) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of claims 11 to 17, wherein the metal film is a titanium film, a tungsten film, A ruthenium film or an iridium film is deposited, and a titanium nitride film, a tungsten nitride film, a ruthenium oxide film, or an iridium oxide film is deposited as the metal compound film.

(19) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal film or the metal compound film is formed on a surface of the metal film or the metal compound film. A step of forming an oxide film of a constituent metal.

(20) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to claim 18 or 19, wherein a ruthenium film is formed on a surface of the metal film, the metal compound film or the oxide film. Alternatively, a step of forming a ruthenium oxide film is included.

(21) The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to any one of (13) to (20), wherein in the step (a), the metal film or Before depositing the metal compound film,
Forming a reinforcing member in advance in a region around the region where the lower electrode is formed on the semiconductor substrate.

(22) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of (11) to (21), wherein in the step (a), the metal film or Before depositing the metal compound film,
Forming a plug conductor connected to a source or a drain of the memory cell selection MISFET, and forming a titanium silicide film on a surface of the plug conductor.

[0041]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to the present embodiment is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WL _n−1 , WL _n , WL _{n + 1} ...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell that stores one bit of information is composed of one information storage capacitor element (capacitor) C and one memory cell selection MISFET Qs connected in series to it. One of the source and the drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is connected to a sense amplifier SA.

Next, an example of a method for manufacturing the memory cell configured as described above will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 2 having a thickness of about 10 nm on its surface. CV is formed on the silicon oxide film 2
A silicon nitride film 3 having a thickness of about 140 nm is deposited by the method D. The silicon oxide film 2 is formed in order to reduce stress applied to the substrate when sintering (burning) the silicon oxide film embedded in the element isolation trench in a later step. Since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the substrate surface below (the active region).

Next, as shown in FIG. 4, the silicon nitride film 3, the silicon oxide film 2, and the semiconductor substrate 1 are dry-etched using the photoresist film 4 as a mask, so that the semiconductor substrate 1 in the element isolation region is deeply etched. 300-400
A groove 5a of about nm is formed. In order to form the groove 5a, the silicon nitride film 3 is dry-etched using the photoresist film 4 as a mask, the photoresist film 4 is removed, and then the silicon oxide film 2 and the semiconductor substrate are etched using the silicon nitride film 3 as a mask. 1 may be dry-etched.

Next, after removing the photoresist film 4,
As shown in FIG. 5, in order to remove a damaged layer generated on the inner wall of the groove 5a by the etching, the semiconductor substrate 1 is
After a thin silicon oxide film 6 having a thickness of about 10 nm is formed on the inner wall of the groove 5a by wet oxidation at about 0 to 900 [deg.] C., as shown in FIG.
0 to 400 nm).
Then, the semiconductor substrate 1 is dry-oxidized at about 1000 ° C. to perform sintering (burning) for improving the film quality of the silicon oxide film 7 buried in the trench 5a. The silicon oxide film 7 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 7, a silicon nitride film 8 having a thickness of about 100 nm is deposited on the silicon oxide film 7 by the CVD method, and then, as shown in FIG. Then, the silicon nitride film 8 is dry-etched, so that the silicon nitride film 8 is left only on the upper portion of the groove 5a having a relatively large area, for example, at the boundary between the memory array and the peripheral circuit. The silicon nitride film 8 remaining on the groove 5a is formed by polishing the silicon oxide film 7 in the next step by chemical mechanical polishing (Chemical Mechanical).
When polishing and flattening by polishing (CMP), the silicon oxide film 7 inside the groove 5a having a relatively large area is polished deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area. Phenomenon (dish; dish
ing).

Next, after removing the photoresist film 9,
As shown in FIG. 9, the element isolation groove 5 is formed by polishing the silicon oxide film 7 by a CMP method using the silicon nitride films 3 and 8 as stoppers and leaving the silicon oxide film 7 inside the groove 5a.

Next, after removing the silicon nitride films 3 and 8 by wet etching using hot phosphoric acid, as shown in FIG. 10, an n-type semiconductor substrate 1 in a region (memory array) where a memory cell is to be formed is formed. An n-type semiconductor region 10 is formed by ion-implanting an impurity, for example, P (phosphorus), and a p-type impurity, for example, B (boron) is added to a part of the memory array and peripheral circuits (a region for forming an n-channel MISFET). The p-type well 11 is formed by ion implantation, and n is formed in another part of the peripheral circuit (the region where the p-channel MISFET is formed).
N-type well 1 by ion implantation of a p-type impurity, for example, P
Form 2 Following this ion implantation, M
An impurity for adjusting the threshold voltage of the ISFET, for example, BF ₂ boron fluoride)) is added to the p-type wells 11 and n
The mold well 12 is ion-implanted. n-type semiconductor region 1
0 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit or the like through the semiconductor substrate 1.

Next, the p-type well 11 and the n-type well 1
After removing the silicon oxide film 2 on each surface of the semiconductor substrate 1 using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a p-type well 11 and an n-type well 1.
Then, a clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of No. 2.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is subjected to a heat treatment in a NO (nitrogen oxide) or N ₂ O (nitrogen oxide) atmosphere to form the gate oxide film 13. Nitrogen may be segregated at the interface with the semiconductor substrate 1 (oxynitridation treatment). When the thickness of the gate oxide film 13 is reduced to about 7 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Nitrogen segregated at the interface with the semiconductor substrate 1 alleviates this distortion, so that the above oxynitridation can improve the reliability of the ultra-thin gate oxide film 13.

Next, as shown in FIG. 11, gate electrodes 14A, 14B and 14C are formed on the gate oxide film 13. The gate electrode 14A is provided with a memory cell selecting MISF.
It forms a part of the ET, and functions as a word line WL in a region other than the active region. The width of the gate electrode 14A (word line WL), that is, the gate length is the memory cell selection M
It has a minimum dimension (for example, 0.24 μm) within an allowable range in which the short channel effect of the ISFET can be suppressed and the threshold voltage can be secured to a certain value or more. The distance between two adjacent gate electrodes 14A (word lines WL) is the minimum dimension determined by the resolution limit of photolithography (for example, 0.22 μm).
m). The gate electrode 14B and the gate electrode 14C constitute each part of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

For the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C, a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) is formed on the semiconductor substrate 1 by the CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering, and a silicon nitride film 15 having a thickness of about 150 nm is further deposited thereon. After deposition by the CVD method, these films are formed by patterning these films using the photoresist film 16 as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN (titanium nitride) film or the like can be used in addition to the WN film.

When a part of the gate electrode 14A (word line WL) is made of low-resistance metal (W), its sheet resistance can be reduced to about 2 to 2.5 Ω / □, so that the word line delay is reduced. Can be reduced. Also, the gate electrode 1
Since the word line delay can be reduced without backing 4 (word line WL) with an Al wiring or the like, the number of wiring layers formed above the memory cells can be reduced by one.

Next, after removing the photoresist film 16, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. When this wet etching is performed, the gate oxide film 13 in a region other than the region under the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is formed.
At the same time that the gate oxide film 1 under the gate sidewall is removed.
3 is also isotropically etched and an undercut occurs, so that the breakdown voltage of the gate oxide film 13 is reduced as it is. Therefore, the quality of the cut gate oxide film 13 is improved by oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, as shown in FIG.
A p ^- type semiconductor region 17 is formed in the n-type well 12 on both sides of the gate electrode 14C by ion implantation of a p-type impurity, for example, B (boron) into the gate electrode 14C. In addition, the p-type well 11 has n
An n ^- type semiconductor region 18 is formed in the p-type well 11 on both sides of the gate electrode 14B by ion-implanting a p-type impurity, for example, P (phosphorus), and an n ^- type semiconductor region 19 is formed in the p-type well 11 on both sides of the gate electrode 14A. To form As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG.
After a silicon nitride film 20 having a thickness of about 50 nm is deposited thereon by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21 as shown in FIG. By performing isotropic etching, sidewall spacers 20a are formed on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do. Further, in order to minimize the amount of the silicon nitride film 15 shaved on the gate electrodes 14B and 14C, the amount of over-etching is minimized.

Next, after removing the photoresist film 21, as shown in FIG. 15, the n-type well 1 in the peripheral circuit region is formed.
2 is ion-implanted with a p-type impurity, for example, B (boron) to form ap ⁺ -type semiconductor region 22 of a p-channel MISFET.
(Source, drain) are formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type semiconductor region 23 (source, drain) of the n-channel MISFET. I do. This allows
P channel type MISFETs Qp and n
A channel type MISFET Qn is formed.

Next, as shown in FIG.
After spin coating an SOG (spin-on-glass) film 24 having a thickness of about 300 nm on the semiconductor substrate 1,
The heat treatment is performed for about a minute, and the SOG film 24 is sintered (sintered).

Next, as shown in FIG.
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 25, the silicon oxide film 25 is polished by a CMP method to flatten the surface. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 18, a silicon oxide film 26 having a thickness of about 100 nm
Is deposited. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. Silicon oxide film 2
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. A PSG (Phospho Silicate Glass) film may be deposited on the silicon oxide film 25 instead of the silicon oxide film 26.

Next, as shown in FIG. 19, the silicon oxide films 26, 25 on the n-type semiconductor region 19 (source, drain) of the memory cell selection MISFET Qs are dry-etched using the photoresist film 27 as a mask. The SOG film 24 is removed. This etching is performed under such a condition that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased, and the silicon nitride film covering the n-type semiconductor region 19 and the upper part of the element isolation trench 5 is formed. 20 is not completely removed.

Subsequently, as shown in FIG. 20, the n-type semiconductor region 19 of the memory cell selecting MISFET Qs is dry-etched using the photoresist film 27 as a mask.
By removing the silicon nitride film 20 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed. This etching is performed under conditions such that the etching rate of the silicon nitride film 20 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. Make sure that 5 is not sharpened. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, after removing the photoresist film 27, as shown in FIG. 21, contact holes 28 and 29 are formed.
A plug (conductor) 30 is formed inside the substrate. Plug 30
Is an n-type impurity (for example, P
After depositing a polycrystalline silicon film doped with (phosphorus)) by a CVD method, the polycrystalline silicon film is polished by a CMP method and left inside the contact holes 28 and 29 to form the film.

Next, as shown in FIG. 22, a silicon oxide film 31 having a thickness of about 200 nm is formed on the silicon oxide film 26.
Is deposited, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. Further, by this heat treatment, n-type impurities in the polycrystalline silicon film forming plug 30 diffuse from the bottoms of contact holes 28 and 29 into n-type semiconductor region 19 (source, drain) of MISFET Qs for memory cell selection, and n The resistance of the type semiconductor region 19 is reduced.

Next, as shown in FIG. 23, the silicon oxide film 31 above the contact hole 28 is removed by dry etching using the photoresist film 32 as a mask to expose the surface of the plug 30. Next, after removing the photoresist film 32, as shown in FIG. 24, the silicon oxide films 31, 26, 25 and the SOG film 24 in the peripheral circuit region are dry-etched using the photoresist film 33 as a mask.
By removing the gate oxide film 13 and contact holes 34 and 35 above the n ⁺ -type semiconductor region 23 (source and drain) of the n-channel MISFET Qn, the p ⁺ -type semiconductor region 22 of the p-channel MISFET Qp Contact holes 36 and 37 are formed above (source, drain).

Next, after removing the photoresist film 33, as shown in FIG. 25, a bit line BL and first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. The bit line BL and the first layer wirings 38 and 39 are
For example, a T film having a thickness of about 50 nm is formed on the silicon oxide film 31.
An i film and a TiN film having a thickness of about 50 nm are deposited by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are formed by patterning these films using the film 41 as a mask.

After a Ti film is deposited on the silicon oxide film 31, the semiconductor substrate 1 is subjected to a heat treatment at about 650 ° C., whereby the Ti film reacts with the Si substrate, and the n-channel type M
A low-resistance TiSi ₂ (titanium silicide) layer 42 is formed on the surface of the n ⁺ type semiconductor region 23 (source, drain) of the ISFET Qn and the surface of the p ⁺ type semiconductor region 22 (source, drain) of the p-channel MISFET Qp. You. Thereby, the contact resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to n ⁺ -type semiconductor region 23 and p ⁺ -type semiconductor region 22 can be reduced. Further, since the bit line BL is composed of the W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the bit line BL and the first layer wirings 38 and 39 of the peripheral circuit are connected. They can be formed simultaneously in the same step.

Next, after removing the photoresist film 41, as shown in FIG. 26, a sidewall spacer 43 is formed on the side wall of the bit line BL and the first layer wirings 38 and 39. The side wall spacer 43 is connected to the bit line BL
After a silicon nitride film 40 is deposited on the first layer wirings 38 and 39 by the CVD method, the silicon nitride film 40 is formed by anisotropic etching.

Next, as shown in FIG.
After spin-coating an SOG film 44 having a thickness of about 300 nm on the first layer wirings 38 and 39, the semiconductor substrate 1 is
The SOG film 44 is subjected to heat treatment at 00 ° C. for about 1 minute to sinter (sinter) the SOG film 44.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the substrate, the silicon oxide film 45 is polished by a CMP method to flatten the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 29, a silicon oxide film 46 having a thickness of about 100 nm is formed on the silicon oxide film 45.
Is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. Silicon oxide film 4
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 30, the silicon oxide films 46 and 45 over the contact holes 29 are removed by dry etching using the photoresist film 47 as a mask.
After removing the film 44 and the silicon oxide film 31, the plug 30
Is formed to reach the surface of the substrate. This etching is performed on the silicon oxide films 46, 45, 31 and SO
The etching is performed under such a condition that the etching rate of the silicon nitride film with respect to the G film 44 becomes small.
To prevent the silicon nitride film 40 and the sidewall spacers 43 on the upper portion from being etched deeply. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after removing the photoresist film 47, a plug 49 is formed inside the through hole 48 as shown in FIG. The plug 49 is made of the silicon oxide film 4
6 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) by CVD, and then etching back the polycrystalline silicon film to leave inside the through hole 48. .

Next, as shown in FIG. 32, a silicon nitride film 51 having a thickness of about 100 nm is formed on the silicon oxide film 46.
Is deposited by the CVD method, and the silicon nitride film 51 in the peripheral circuit region is removed by dry etching using the photoresist film 52 as a mask. The silicon nitride film 51 remaining in the memory array is used as an etching stopper when etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of an information storage capacitor (capacitor) described later.

Next, after removing the photoresist film 52, as shown in FIG. 33, a silicon oxide film 53 having a thickness of about 1.0 μm is deposited on the silicon nitride film 51, and the photoresist film 54 is masked. By removing the silicon oxide film 53 and the silicon nitride film 51 by the dry etching described above, a groove 55 is formed above the through hole 48, and the upper surface of the plug 49 is exposed. At the same time, a frame-shaped groove 5 surrounding the memory array is formed around the memory array.
5a is formed. The silicon oxide film 53 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, after removing the photoresist film 54, as shown in FIG. 34, a titanium nitride film (TiN) 56 having a thickness of about 100 nm is formed on the silicon oxide film 53 including the grooves 55 and 55a by the CVD method. Is deposited. Titanium nitride film 5
Since the film thickness of No. 6 is about 100 nm, the groove 55 is not buried. This titanium nitride film 56 is used as a lower electrode material of the capacitor. Subsequently, the semiconductor substrate 1 is immersed in a hydrogen peroxide solution for about 5 minutes to form irregularities 80 on the surface (inner surface) of the titanium nitride film 56. FIG. 45 is a cross-sectional view showing a part of the titanium nitride film 56 on the silicon oxide film 46 in an enlarged manner. By forming the irregularities 80 on the surface of the titanium nitride film 56 in this manner, the titanium nitride film 56
, The surface area of the lower electrode composed of the lower electrode can be increased.

When the titanium nitride film 56 formed on the substrate by the CVD method is observed with a transmission electron microscope, the cross-sectional structure is schematically shown in FIG. 44 (a). A plurality of grain boundaries exist in a columnar polycrystalline state. FIG. 44 schematically shows the planar structure.
It is observed as shown in (b), which is composed of a relatively wide amorphous grain boundary 56a and a relatively narrow amorphous grain boundary 56b. When the titanium nitride film 56 having such amorphous grain boundaries having different widths is immersed in a hydrogen peroxide solution, this titanium nitride film 56
Is selectively etched based on the difference in the etching rate at the crystal grain boundaries on the surface of the substrate, so that large unevenness 80 having a large difference in height can be formed, and as a result, the surface area of the titanium nitride film 56 can be increased. it can.

In this case, the selectivity in the selective etching depends on the film forming temperature of the titanium nitride film 56, and the higher the film forming temperature, the higher the crystallinity of each crystal grain and the larger the selectivity. However, this film formation temperature has already been
There is a certain limit because it is related to the heat resistance of the memory cell selecting MISFETs Qs and the like formed in the above. Generally, the film forming temperature is suitably from 400 to 800 ° C., and in practice, preferably 650 ± 50 ° C. In some cases, such an immersion treatment may be effectively performed using a solution made alkaline by adding ammonia water or the like to a hydrogen peroxide solution.

Next, as shown in FIG. 35, an S film having a thickness larger than the depth of the grooves 55 and 55a is formed on the titanium nitride film 56.
After spin coating the OG film 57, as shown in FIG.
The SOG film 57 is etched back, and the titanium nitride film 56 on the silicon oxide film 53 is etched back, so that the S (inner wall and bottom) is formed inside the grooves 55 and 55a.
The OG film 57 is left.

Next, as shown in FIG. 37, with the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region as a mask, the SOG film 57 inside the groove 55 and the silicon oxide film 53 in the gap between the groove 55 are wetted. Etching is performed to form a cylindrical (crown-shaped) lower electrode 60 constituting a capacitor. The unevenness 80 exists only on the inner surface of the cylindrical lower electrode 60. At this time, since the silicon nitride film 51 remains in the gap between the trenches 55, the silicon oxide film 46 thereunder is not etched. Further, since the silicon nitride film 51 remains around the lower electrode 60 so as to be in contact with the lower electrode 60, the silicon nitride film 51 acts to reinforce the lower electrode 60 from the periphery. The effect of preventing collapse is obtained.
Further, one end of the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region is disposed at the boundary between the lower electrode 60 formed on the outermost side of the memory array and the peripheral circuit region, that is, above the groove 55a. . In this way, even when misalignment occurs at the end of the photoresist film 58, the SOG film 57 remains inside the groove 55 of the lower electrode 60 formed on the outermost side of the memory array, The silicon oxide film 53 is not etched.

Next, the photoresist film 58 is removed, and as shown in FIG. 38, a tantalum oxide (Ta ₂ O ₅ film 61) having a thickness of about 20 nm is deposited on the lower electrode 60 by a CVD method. The substrate 1 is heat-treated in an oxidizing atmosphere at a temperature of 600 ° C. or higher to oxidize and reform the tantalum oxide film 61. The tantalum oxide film 61 is used as a capacitor insulating film material of a capacitor.

In this oxidation reforming process, oxygen as an oxidizing agent passes through the tantalum oxide film 61 and reaches the surface of the lower electrode 60. Since the lower electrode 60 is made of a titanium nitride film,
An insulating film having a low dielectric constant such as a silicon oxide film is not formed on the interface between the lower electrode 60 and the tantalum oxide film 61.
Therefore, the dielectric constant of the capacitor insulating film of the capacitor is not substantially reduced, and the thickness of the capacitor insulating film is not substantially increased. Therefore, the capacity of the capacitor can be maintained large. Even if oxygen reaches the lower electrode 60 as described above, the generated titanium oxide has conductivity and does not contribute to an increase in the thickness of the capacitor insulating film. Therefore, the capacitance of the capacitor can be maintained large.

Next, as shown in FIG. 39, a titanium nitride (TiN) film 62 having a thickness of about 100 nm is deposited on the tantalum oxide film 61 by the CVD method.
3 by dry etching using titanium as a mask.
By patterning the tantalum oxide film 61, a cylinder made of an upper electrode made of the titanium nitride film 62, a capacitor insulating film (dielectric film) made of the tantalum oxide film 61, and a titanium nitride film 56 having an uneven surface 80 is formed. The lower electrode 60 forms a capacitor C. FIG.
Is a sectional view showing an enlarged structure of a part of the capacitor C. In FIG. 46, the thickness of the titanium nitride film 62 is actually relatively large, but is schematically shown for simplicity. Thus, a DRAM memory cell including the memory cell selecting MISFET Qs and the capacitor C connected in series thereto is completed.

The upper electrode made of the titanium nitride film 62 is formed at a high temperature, which may damage the already formed tantalum oxide film 61 and increase the leak current. It is desirable to form at low temperature. Since the tantalum oxide film 61 and the titanium nitride film 62 constituting the capacitor C are both formed by the CVD method, they have excellent step coverage. Therefore, even if the lower electrode 60 has the irregularities 80, the irregularities 80 can be completely covered, and there is no problem in terms of flatness.

Here, as shown in FIG. 46, the irregularities 80 of the cylindrical lower electrode 60 constituting the capacitor C are represented by p at the top, v at the valley, and d at the thickness of the capacitive insulating film 61. When expressed, the average value h of the height difference (p−v) is 0.5d ≦ h ≦
5d is selected. If the average h is 0.5
If d does not reach d, the degree of the irregularities 80 becomes small, making it difficult to increase the electrode area, and it becomes difficult to secure a sufficient capacitance in a limited plane area. On the other hand, if the average value h exceeds 5d, the degree of the irregularities 80 becomes too large, and considering that the thickness d of the capacitive insulating film 61 is about 20 nm, the mechanical properties of the cylindrical lower electrode 60, especially the side wall, are considered. It is difficult to maintain the target strength.

It should be noted that the degree of the irregularities 80 is related to the grain size of the crystal grains of the titanium nitride film 56, and this grain size can be changed by the film formation conditions, the film thickness, etc. of the titanium nitride film 56. It can be controlled by such film forming conditions and the like.

Next, after removing the photoresist film 63, as shown in FIG.
A silicon oxide film 64 of about 00 nm is deposited. The silicon oxide film 64 is made of, for example, plasma C using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.
Deposit by VD method. Subsequently, the first layer wiring 3 of the peripheral circuit is formed by dry etching using the photoresist film 65 as a mask.
8, silicon oxide films 64, 53, 46, 45, S
By removing the OG film 44 and the silicon nitride film 40, a through hole 66 is formed.

Next, after removing the photoresist film 65, as shown in FIG. 41, a plug 67 is formed inside the through hole 66, and then second layer wirings 68 and 69 are formed on the silicon oxide film 64. To form The plug 67 is formed on the silicon oxide film 64 with a thickness of 100 by a sputtering method.
A TiN film having a thickness of about nm is deposited, and a W film having a thickness of about 500 nm is further deposited thereon by a CVD method. Then, these films are etched back and left inside the through-hole 66. The second layer wirings 68 and 69 are formed on the silicon oxide film 64 by sputtering to a thickness of about 50 nm.
an iN film, an Al (aluminum) film having a thickness of about 500 nm,
After a Ti film having a thickness of about 50 nm is deposited, these films are formed by patterning by dry etching using a photoresist film as a mask.

Next, as shown in FIG.
An interlayer insulating film is deposited on the upper portions of 8 and 69. The interlayer insulating film includes, for example, a silicon oxide film 71 having a thickness of about 300 nm, an SOG film 72 having a thickness of about 400 nm, and a silicon oxide film 73 having a thickness of about 300 nm. Silicon oxide film 7
Reference numerals 1 and 73 denote plasma CVs using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as source gases.
Deposit by D method.

Next, as shown in FIG.
Then, a through hole 74 is formed in the interlayer insulating film on the upper portion of the semiconductor device, a through hole 75 is formed in the interlayer insulating film on the second layer wiring 69 of the peripheral circuit, and a plug 76 is formed in the through holes 74 and 75. Then, a third layer is formed on the interlayer insulating film.
The layer wirings 77, 78, 79 are formed. Through hole 7
4 and 75 are obtained by removing the silicon oxide film 73, the SOG film 72, and the silicon oxide film 71 by dry etching using a photoresist film as a mask, and further removing the silicon oxide film 64 from the through hole 74. Form. The plug 76 is formed by depositing a TiN film having a thickness of about 100 nm on the interlayer insulating film by sputtering.
Further, a W film having a thickness of about 500 nm is deposited thereon by a CVD method, and then these films are etched back and left inside the through holes 74 and 75. The third layer wirings 77 to 79 are formed by sputtering a TiN film having a thickness of about 50 nm and an A film having a thickness of about 500 nm on the interlayer insulating film.
After depositing a 1-layer film and a Ti film having a thickness of about 50 nm, these films are patterned and formed by dry etching using a photoresist film as a mask.

After that, a passivation film composed of a silicon oxide film and a silicon nitride film is deposited on the third layer wirings 77 to 79, but illustration thereof is omitted. Through the above steps, the DRAM of the present embodiment is substantially completed.

According to the present embodiment, titanium nitride film 56
The surface area is increased by forming irregularities 80 on the surface (inner surface) of the lower electrode 60 made of a titanium nitride film 62 on the lower electrode 60 via a capacitance insulating film made of a tantalum oxide film 61 having a large dielectric constant. Since the capacitor is formed by forming the upper electrode, it is possible to realize a capacitor having a sufficient capacitance within a limited plane area on the substrate, and to increase the capacitance.

In addition, the irregularities 80 correspond to the titanium nitride film 5.
6 has a polycrystalline structure, and is formed using a difference in etching rate due to aqueous hydrogen peroxide at a crystal grain boundary (a difference in etching rate between a bulk crystal part and an amorphous state grain boundary part). Therefore, it can be formed stably and easily, and can be formed easily under an enlarged process margin. For this reason, a remarkable increase in manufacturing cost can be avoided.

Further, since the lower electrode 60 is made of the titanium nitride film 56, a low-dielectric-constant insulating film such as silicon oxide is not formed when the tantalum oxide film 61 is oxidized and reformed. Large capacity can be maintained. Further, since the titanium nitride film 62 having a small internal stress is used for the upper electrode, the leakage current of the capacitor C can be reduced without applying an undesired stress to the tantalum oxide film 61. Further, since the silicon nitride film 51 is formed as a member for preventing the lower electrode 60 from collapsing, the mechanical strength of the lower electrode 60 can be increased, and the reliability of the semiconductor integrated circuit device can be improved.

(Embodiment 2) In the present embodiment, a DRAM is formed in which not only the inner surface of the cylindrical lower electrode constituting the capacitor but also the side surfaces thereof are formed with irregularities to further increase the surface area of the lower electrode. Here is an example. The method of manufacturing the DRAM of the present embodiment will be described with reference to FIGS.

FIG. 47 shows a step corresponding to FIG. 33 of the first embodiment. After plug 49 is formed in through hole 48 of silicon oxide film 46, silicon oxide film 81 is formed by CVD.
Oxide film 81 to be deposited and formed with a lower electrode
A groove 82 is formed in the region of FIG. Next, as shown in FIG. 48, a titanium nitride film 83 is formed on the entire surface by a CVD method. Next, as shown in FIG. 49, after the SOG film 84 is spin-coated in the trench 82 and buried, the titanium nitride film 83 on the SOG film 84 and the silicon oxide film 81 is polished and removed by the CMP method.

Next, as shown in FIG. 50, the SOG film 84 and the silicon oxide film 81 inside the groove 82 are dry-etched to expose the titanium nitride film 83. The SOG film 8
4 and the silicon oxide film 81 can be removed by a wet etching method. However, in this case,
It is necessary to form a silicon nitride film on the surface of the silicon oxide film 46 as an etching stopper for wet etching. Next, the substrate is immersed in a hydrogen peroxide solution, and, like the titanium nitride film 56 in the first embodiment,
The lower electrode 85 is formed by forming the unevenness 80 on the inner surface and the side surface of the titanium nitride film 83.

Next, as shown in FIG.
A tantalum oxide (Ta ₂ O ₅ film 86 is deposited on the upper surface of the substrate by a CVD method, and then the substrate is subjected to a heat treatment at 600 ° C. or more in an oxidizing atmosphere to oxidize the tantalum oxide film 86.
Next, the titanium nitride film 8 is formed so as to cover the tantalum oxide film 86.
7 is deposited by a CVD method to form a titanium nitride film 87.
, A capacitor insulating film made of a tantalum oxide film 86, and a cylindrical lower electrode 8 made of a titanium nitride film 83
5 is formed. The formation of the tantalum oxide film 86 and the titanium nitride film 87 is the same as in the first embodiment. According to the present embodiment, in addition to the effect of the first embodiment, irregularities 80 are formed not only on the inner surface of cylindrical lower electrode 85 but also on the side surfaces, so that the surface area of lower electrode 85 is increased. can do. Therefore, the capacity of the capacitor can be further increased.

(Embodiment 3) In the present embodiment, as in Embodiment 2, irregularities are formed on the inner surface and side surfaces of a cylindrical lower electrode constituting a capacitor to further increase the surface area of the lower electrode. In the DRAM, an example will be described in which the lower electrode is actively prevented from collapsing particularly when the height of the lower electrode is increased. FIGS. 52 to 52 show the manufacturing method of the present embodiment.
This will be described with reference to FIG.

FIG. 52 shows a step corresponding to FIG. 33 of the first embodiment. After a plug 49 is formed in the through hole 48 of the silicon oxide film 46, a silicon nitride film 88 and a silicon oxide film 89 are formed by, for example, a CVD method, and finally a groove 90 is formed in a region where a lower electrode is to be formed. The film thickness obtained by adding the silicon nitride film 88 to the silicon oxide film 89 is the same as that in Embodiment 1, and the thickness of the silicon nitride film 88 is 30
It can be about 0 to 500 nm. The specific thickness of the silicon nitride film 88 is determined in relation to the height of the lower electrode. The means for forming the silicon nitride film 88 can be formed using the method for forming a silicon nitride film described in the series of steps of the first embodiment. In this embodiment, the thickness of the silicon nitride film 88 is set to be larger than the thickness of the silicon nitride film 51 in the first embodiment.

Next, as shown in FIG. 53, a titanium nitride film 91 is formed on the entire surface by the CVD method, and then, as shown in FIG. , The titanium nitride film 91 on the SOG film 92 and the silicon oxide film 89 are polished and removed by the CMP method. At this time, the surface is flattened.

Next, as shown in FIG. 55, the SOG film 92 and the silicon oxide film 89 inside the trench 90 are dry-etched to expose the titanium nitride film 91. Note that dry etching can be replaced with wet etching. During this wet etching, the silicon nitride film 88 functions as an etching stopper. Thereafter, the substrate is immersed in a hydrogen peroxide solution to form irregularities 80 on the inner surface and side surfaces of the titanium nitride film 91, thereby forming the lower electrode 93.
Next, tantalum oxide (Ta ₂ O _{5) is formed on} the lower electrode 93.
The film 94 is deposited by the CVD method, and then the substrate is subjected to a heat treatment at 600 ° C. or more in an oxidizing atmosphere to oxidize and modify the tantalum oxide film 94.

Thus, the leakage current of the capacitor can be reduced. Further, as in the first embodiment, an insulating film having a low dielectric constant is not formed at the interface between the lower electrode 93 and the tantalum oxide film 94 by the oxidation reforming process.

Next, as shown in FIG. 56, a titanium nitride film 95 is deposited by a CVD method so as to cover the tantalum oxide film 94, whereby an upper electrode made of the titanium nitride film 95 and a tantalum oxide film 94 are formed. A capacitor composed of a capacitor insulating film and a cylindrical lower electrode 93 made of a titanium nitride film 91 is formed.

According to the present embodiment, cylindrical lower electrode 9
In order to further increase the surface area of the lower electrode 93 by forming the unevenness 80 on the inner surface and side surface of the lower electrode 3 to increase the surface area of the lower electrode 93, the lower part is previously placed at a position around the lower electrode 93 made of the titanium nitride film 91. Since the silicon nitride film 88 having a large thickness was formed so as to be in contact with the electrode 93,
Since the silicon nitride film 88 functions as an insulating film for preventing the lower electrode 93 from collapsing, the lower electrode 93 can be prevented from collapsing. Thereby, the capacitance of the capacitor can be increased with stability. The unevenness 80 is a cylindrical lower electrode 93.
May be formed only on the inner surface. The effect can be obtained in the same manner as in the first or second embodiment.

(Embodiment 4) This embodiment shows an example of a DRAM in which a reaction between a titanium nitride film forming a lower electrode and polycrystalline silicon forming a plug in contact with the titanium nitride film is prevented. . The manufacturing method according to the present embodiment will be described with reference to FIGS.

As shown in FIG. 57, when a tantalum oxide film 102 serving as a capacitive insulating film is formed on a titanium nitride film 99 serving as a lower electrode 101 by a CVD method and then subjected to a heat treatment for oxidative reforming, At the contact portion between the titanium nitride film 99 and the polycrystalline silicon as the plug 49, the two react with each other to form a titanium silicide 96, and the shape may change as shown in FIG. If the shape changes after the formation of the tantalum oxide film 102 serving as the capacitive insulating film, the tantalum oxide film 102 receives mechanical stress, and this portion becomes a path, which causes an increase in leakage current. In order to prevent this, it is effective to form titanium silicide on the surface of polycrystalline silicon (plug 49) in advance.

That is, as shown in FIG. 58, after a plug 49 made of polycrystalline silicon is formed in the through hole 48 of the silicon oxide film 46, a titanium silicide 96 is formed on the plug 49. For this, a titanium film is deposited on the entire surface after the formation of the plug 49 by a CVD method, and then the substrate is subjected to a heat treatment at about 600 ° C. or more, so that
And the titanium immediately above the titanium silicide 96
To form Next, after removing the unreacted titanium film by etching, similarly to the process of FIG. 52, the silicon oxide film 9 in which the groove 97 is finally formed in the region where the lower electrode is to be formed is formed.
8 is formed with a silicon nitride film 88 interposed therebetween.

Next, as shown in FIG. 59, after a titanium nitride film 99 is formed on the entire surface by the CVD method, as shown in FIG. The titanium nitride film 99 on the film 100 and the silicon oxide film 89 is polished and removed by a CMP method, and the surfaces thereof are planarized. Next, as shown in FIG. 61, the SOG film 100 and the silicon oxide film 98 inside the groove 97 are removed by dry etching or wet etching to expose the titanium nitride film 99, and then the substrate is immersed in a hydrogen peroxide solution. do it,
The unevenness 80 is formed on the inner surface and the side surface of the titanium nitride film 99 to form the lower electrode 101.

Next, a tantalum oxide (Ta ₂ O ₅ film 102) is deposited on the lower electrode 101 by a CVD method, and the substrate is heat-treated at 600 ° C. or more in an oxidizing atmosphere to oxidize the tantalum oxide film 102. After the treatment, as shown in FIG. 62, the titanium nitride film 1 is formed so as to cover the tantalum oxide film 102.
03 is deposited, an upper electrode made of a titanium nitride film 103, a capacitor insulating film made of a tantalum oxide film 102, and a cylindrical lower electrode 101 made of a titanium nitride film 99 are formed.
Is formed.

According to the present embodiment, the tantalum oxide film 1
In the oxidation reforming process of No. 02, a heat treatment at 600 ° C. or more is performed. Since the titanium silicide 96 is formed on the plug 49 immediately below the titanium nitride film 99 serving as the lower electrode 101, the titanium nitride film 99 is formed. The reaction between the tantalum oxide film 102 and the plug 49 is prevented, so that new titanium silicide is not formed, and undesired stress of the tantalum oxide film 102 due to the generation of titanium silicide after the formation of the tantalum oxide film 102 is prevented. Generation can be suppressed and leakage current of the capacitor can be reduced.

(Embodiment 5) In this embodiment, an example of a DRAM that improves the oxidation resistance of a lower electrode will be described. A DRAM according to the present embodiment will be described with reference to FIG.

In the case where the lower electrode is only a titanium nitride film, a tantalum oxide film serving as a capacitive insulating film is formed thereon by a CVD method and then subjected to an oxidation reforming treatment at about 600 ° C. or more. The titanium nitride film is remarkably oxidized by the generated oxygen, and titanium oxide is formed on the surface. As a result, the volume of the lower electrode expands, and in extreme cases, a problem arises in that the tantalum oxide film covering the lower electrode peels off. Further, even if the tantalum oxide film does not peel off, a leak current may increase due to stress on the tantalum oxide film. Therefore, when the lower electrode is made of the titanium nitride film, the tantalum oxide film must be oxidized at a temperature low enough to prevent the tantalum oxide film from peeling off. As a result, the reforming effect of the tantalum oxide film becomes insufficient and the capacitor or D
The characteristics of the RAM may not be stable. In order to improve such instability, it is effective to configure the lower electrode with a material that is not easily oxidized and perform the oxidation reforming treatment of the tantalum oxide film at a higher temperature.

In this regard, since ruthenium is a material that is generally hard to be oxidized as a metal, using ruthenium as a material for the lower electrode can be a means for solving the above problem. However, since it is generally not easy to form irregularities on ruthenium itself, after increasing the surface area by forming irregularities in advance using a titanium nitride film that easily forms irregularities,
By forming ruthenium on this surface, the tantalum oxide film can be modified at a high temperature while maintaining an enlarged surface area.

That is, as shown in FIG. 63, after forming the unevenness 80 on the inner surface and the side surface of the titanium nitride film 104 constituting the lower electrode, the surface of the unevenness 80 has a thickness of 5 to 20 nm.
A ruthenium film 105 of about nm is formed by a CVD method to form a lower electrode 106. Next, a tantalum oxide film 107 is formed on the ruthenium film 105 by CVD. FIG. 66 shows an enlarged sectional structure of a part of the lower electrode 106 at this time. Subsequently, after performing an oxidation reforming process on the tantalum oxide film 107 at about 600 ° C. or more, the tantalum oxide film 10
7, a titanium nitride film 108 is formed by CVD.

Thus, the upper electrode made of the titanium nitride film 108, the capacitance insulating film made of the tantalum oxide film 107, and the titanium nitride film 104 covered with the ruthenium film 105
And a lower electrode 106 having a cylindrical shape.

According to the present embodiment, the lower electrode 106 is formed by covering the titanium nitride film 104 on which the irregularities 80 are formed by using the ruthenium film 105 which is hardly oxidized.
The oxidation resistance of the lower electrode 106 can be improved. Thereby, compared to the case where the ruthenium film 105 is not provided,
Volume expansion due to the formation of the titanium oxide film on the surface of the titanium nitride film 104 in the oxidation reforming process can be suppressed, and leakage current can be reduced. Further, it is possible to prevent the tantalum oxide film 107, which is a capacitance insulating film, from peeling off while maintaining the advantage of increasing the surface area of the lower electrode 106, thereby realizing a capacitor with high stability and large capacitance.
In addition, since the oxidation resistance of the lower electrode 106 is improved, the tantalum oxide film 107 serving as a capacitance insulating film can be subjected to an oxidation reforming process at a higher temperature, and the insulation of the tantalum oxide film 107 can be improved. Thereby, the leakage current of the capacitor can be reduced.

It is more effective to use a ruthenium oxide film in place of the ruthenium film 105. That is, since the ruthenium oxide film contains oxygen as compared with the ruthenium film, the ruthenium oxide film has an excellent function of suppressing the diffusion of oxygen during the oxidation reforming treatment. This ruthenium oxide film is CV
It can be formed by the D method, or can be formed by forming a ruthenium film by the CVD method and then oxidizing the same.

(Embodiment 6) In this embodiment, as shown in Embodiment 5, when a part of the lower electrode is formed of a ruthenium film or a ruthenium oxide film, the oxidation resistance of the lower electrode is reduced. An example of a DRAM that is further improved will be described. The DRAM of this embodiment will be described with reference to FIG. As described in the fifth embodiment, when a part of the lower electrode is formed of a ruthenium film or a ruthenium oxide film, the thickness of the ruthenium film or the ruthenium oxide film is extremely small (generally, as described above). About 5-20nm)
Therefore, fine pinholes are formed and the film quality tends to deteriorate. For this reason, for the same reason as described in the fifth embodiment, the temperature of the oxidation reforming treatment of the tantalum oxide film may be limited. In order to solve such a problem, it is effective to form titanium oxide on the titanium nitride film before forming the ruthenium film or the ruthenium oxide film in order to compensate for the deterioration of the film quality of the ruthenium film or the ruthenium oxide film. Becomes

That is, as shown in FIG. 64, after forming the irregularities 80 on the inner surface and side surfaces of the titanium nitride film 108 forming the lower electrode, the titanium nitride film 108 is oxidized to oxidize the surface of the irregularities 80 in advance. A titanium film 109 is formed. Next, a ruthenium film 110 is formed on the titanium oxide film 109 by CVD to form a lower electrode 111. Next, a tantalum oxide film 112 is formed on the ruthenium film 110 by CVD. FIG. 67 shows an enlarged cross-sectional structure of a part of the lower electrode 111 at this time. Subsequently, after performing an oxidation reforming process on the tantalum oxide film 112 at about 600 ° C. or more in an oxidizing atmosphere, a titanium nitride film 113 is formed by CVD so as to cover the tantalum oxide film 112.

As a result, a cylindrical electrode made of an upper electrode made of a titanium nitride film 113, a capacitor insulating film made of a tantalum oxide film 112, and a titanium nitride film 108 covered with a ruthenium film 110 via a titanium oxide film 109 is formed. Lower electrode 1
11 is formed.

According to the present embodiment, a titanium oxide film 109 is formed in advance on a titanium nitride film 108, and this titanium oxide film 109 is covered with a ruthenium film 110 to form a lower electrode 11.
With the configuration 1, even if the film quality of the ruthenium film 110 is deteriorated, it can be compensated for by the titanium oxide film 109, so that the oxidation resistance of the lower electrode can be further improved. Thus, the oxidation reforming treatment of the tantalum oxide film 107 serving as the capacitance insulating film can be performed at a higher temperature. That is, since the lower electrode 111 is formed by forming the ruthenium film 110 on the titanium oxide film 109 formed in advance, even if the oxidation modification treatment of the tantalum oxide film 107 is performed at about 600 ° C. or more, the tantalum oxide film 107 and Ruthenium film 11
Oxygen that diffuses 0 is suppressed by the titanium oxide film 109, so that the volume expansion of the lower electrode 111 is prevented. This eliminates the problem that the tantalum oxide film 107 peels off.

The formation of the titanium oxide film 109 may be performed by a CVD method without using the oxidation method. It is also effective to use a ruthenium oxide film instead of the ruthenium film 110.

(Embodiment 7) In this embodiment, a DRAM in which the oxidation resistance of not only the lower electrode but also the upper electrode is improved.
Here is an example. The DRAM of this embodiment will be described with reference to FIG.

That is, as shown in FIG. 65, after forming unevenness 80 on the inner surface and side surface of the titanium nitride film 114 constituting the lower electrode, a ruthenium film 115 is formed on the surface of the unevenness 80 by CVD. The lower electrode 116 is used.
Next, a tantalum oxide film 117 is formed on the ruthenium film 115. FIG. 68 shows the lower electrode 116 at this time.
3 shows an enlarged structure of a part of. Subsequently, after performing an oxidation reforming process at about 600 ° C. or more in an oxidizing atmosphere, a ruthenium film 118 is formed by a CVD method so as to cover the tantalum oxide film 117 to form an upper electrode.

According to the present embodiment, not only is the ruthenium film 115 used as a part of the lower electrode 116, but also the upper electrode is formed using the ruthenium film 118. Can also be improved. Thus, when the titanium nitride film is used for the upper electrode, it is possible to solve a problem that a leak current increases in a subsequent heat treatment. Also, the ruthenium film 1
It is effective to use a ruthenium oxide film instead of 15 and 118.

(Embodiment 8) In this embodiment, an example of a DRAM in which the capacity is increased by adopting a simple STC structure as a capacitor will be described. A method of manufacturing the DRAM will be described with reference to FIGS. I do.

As shown in FIG. 69, the silicon oxide film 46
After the plug 49 is formed in the through hole 48 of FIG.
A titanium nitride film 121 of about 00 nm is formed on the entire surface by a CVD method. Next, as shown in FIG. 70, the substrate is immersed in a hydrogen peroxide solution for about 5 minutes to form irregularities 80 on the surface (upper surface) of the titanium nitride film 121.

Next, as shown in FIG. 71, after a region of the titanium nitride film 121 where a lower electrode is to be finally formed is masked with a photoresist film 122, the unmasked titanium nitride film 121 is dry-etched. Then, the lower electrode 123 is formed using the remaining titanium nitride film 121.
Next, after removing the photoresist film 122, a cleaning process is performed.

Next, as shown in FIG.
Tantalum oxide (Ta ₂ O ₅ film 124 on top of CVD 3)
Then, the substrate is heat-treated at 600 ° C. or more in an oxidizing atmosphere to oxidize and modify the tantalum oxide film 124. Next, by depositing a titanium nitride film 125 so as to cover the tantalum oxide film 124, the titanium nitride film 125 is deposited.
, An upper electrode made of a tantalum oxide film 124, and a lower electrode 12 made of a titanium nitride film 121
3 is formed.

According to the present embodiment, the unevenness 80 is formed on the surface of the lower electrode 123 to constitute a capacitor having a simple STC structure.
In the capacitor having the C structure, the electrode area of the lower electrode 123 can be increased, and the capacitance can be further increased.

(Embodiment 9) In this embodiment, an example of a DRAM in which the upper and lower surfaces of a lower electrode constituting a capacitor having a simple STC structure are provided with irregularities to further increase the capacitance will be described. The manufacturing method is shown in FIG.
This will be described with reference to FIGS.

As shown in FIG. 73, a silicon oxide film 46 is formed.
A titanium nitride film 126 having a thickness of about 100 nm is formed on the entire surface so as to cover the plug 49 formed in the through hole 48 of FIG.
After the formation by the VD method, a region of the titanium nitride film 126 where a lower electrode is to be finally formed is masked with a photoresist film 127. Next, the unmasked titanium nitride film 12
After the substrate 6 is removed by dry etching, the substrate is immersed in a hydrogen peroxide solution for about 5 minutes to form irregularities 80 on the surface (upper surface) and side surfaces of the titanium nitride film 126, as shown in FIG. An electrode 128 is formed.

Next, the photoresist film 127 is removed,
After performing the cleaning process, as shown in FIG.
Tantalum oxide (Ta ₂ O ₅ film 1)
29 is deposited by a CVD method, and then the substrate is heat-treated in an oxidizing atmosphere at a temperature of 600 ° C. or higher to oxidize and modify the tantalum oxide film 129. Next, by depositing a titanium nitride film 130 so as to cover the tantalum oxide film 129, an upper electrode made of the titanium nitride film 130 and the tantalum oxide film 129 are formed.
A capacitor composed of a capacitive insulating film made of and a lower electrode 128 made of a titanium nitride film 126 is formed.

According to the present embodiment, in addition to the effect of the eighth embodiment, the upper and lower surfaces of lower electrode 128 have unevenness 80.
Is formed to form a capacitor having a simple STC structure, so that the electrode area of the lower electrode 128 can be further increased, and the capacitance of the capacitor can be further increased.

(Embodiment 10) In this embodiment, an example of a DRAM for improving the oxidation resistance of a lower electrode constituting a capacitor having a simple STC structure will be described with reference to FIG.

In the case of a capacitor having a simple STC structure,
If the lower electrode is made of a titanium nitride film, the problem described in the fifth embodiment occurs. Therefore, the simple S
Also in the TC structure, by forming the lower electrode using a ruthenium film or a ruthenium oxide film as a material that is hardly oxidized, it becomes effective to perform the oxidation reforming treatment of the tantalum oxide film at a higher temperature.

That is, as shown in FIG. 76, plugs 49 formed in through holes 48 of silicon oxide film 46 are formed.
Is formed on a region where a lower electrode is to be finally formed, so that a thickness of 5 to 20 nm is formed on the surface of the unevenness 80.
A ruthenium film 132 is formed by the CVD method so as to form a lower electrode 133. FIG. 78 shows an enlarged sectional structure of a part of the lower electrode 133 at this time.

Subsequently, as in the case of the fifth embodiment, a tantalum oxide film is formed as a capacitive insulating film on the ruthenium film 132 by CVD, and then an oxidation reforming process is performed to cover the tantalum oxide film. A capacitor is formed by forming an upper electrode made of a titanium nitride film.

According to the present embodiment, even in the case of a capacitor having a simple STC structure, the ruthenium film 1 which is hardly oxidized is formed.
Since the lower electrode 133 is formed by using 32, the oxidation resistance of the lower electrode can be improved, and the same effect as that of the fifth embodiment can be obtained. In other words, the leakage current can be further reduced and the tantalum oxide film, which is a dielectric material, is prevented from peeling off while maintaining the advantage of increasing the surface area of the lower electrode, realizing a highly stable, large-capacity capacitor. can do. In addition,
It is also effective to use a ruthenium oxide film instead of the ruthenium film 132.

(Embodiment 11) In this embodiment, when a part of the lower electrode constituting the capacitor having the simple STC structure is formed of a ruthenium film or a ruthenium oxide film, the oxidation resistance of the lower electrode is improved. An example of a DRAM will be described with reference to FIG.

Even in the case of a capacitor having a simple STC structure,
If a part of the lower electrode is formed of a ruthenium film or a ruthenium oxide film, the problem described in the sixth embodiment occurs. Therefore, even in the simple STC structure, it is effective to form titanium oxide on the titanium nitride film before forming ruthenium oxide.

That is, as shown in FIG. 77, plugs 49 formed in through holes 48 of silicon oxide film 46 are formed.
Is formed in a region where a lower electrode is to be finally formed, so that a titanium oxide film 1 is formed on the surface of the unevenness 80.
35 is formed by an oxidation treatment or formed by a CVD method,
Next, a ruthenium film 136 is formed on the titanium oxide film 135 by a CVD method to form a lower electrode 137. Fig. 79
Shows an enlarged sectional structure of a part of the lower electrode 137 at this point.

Subsequently, in the same manner as in the sixth embodiment, after forming a tantalum oxide film as a capacitive insulating film on the ruthenium film 136, an oxidation reforming process is performed, and titanium nitride is formed so as to cover the tantalum oxide film. A capacitor is formed by forming an upper electrode made of a film.

According to the present embodiment, even in the case of a capacitor having a simple STC structure, a titanium oxide film 135 is previously formed on a titanium nitride film 134, and this titanium oxide film 135 is covered with a ruthenium film 136 so as to cover the lower electrode 137. With this configuration, the oxidation resistance of the lower electrode can be further improved. It is also effective to use a ruthenium oxide film instead of the ruthenium film 136.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, an example was described in which a titanium nitride film was used as a material forming the lower electrode. However, the lower electrode is not limited to a titanium nitride film, and at least a metal film having a polycrystalline structure. Alternatively, a metal compound film can be used. These metal films or metal compound films can include a transition metal film or a compound film thereof. As such a metal film, titanium (Ti)
Film, a tungsten (W) film, a metal material such as a ruthenium (Ru) film or an iridium (Ir) film, and as a metal compound film, a titanium nitride (TiN) film, a tungsten nitride (WN) film, ruthenium oxide (RuOx)
Compounds such as a film or an iridium oxide (IrOx) film can be given.

In the above embodiment, the ruthenium film or the ruthenium oxide film is exemplified as the lower electrode which is hardly oxidized. However, an iridium film or an iridium oxide film can be used similarly.

Furthermore, in the above-described embodiment, an example was described in which a tantalum oxide film was used as the capacitive insulating film. However, the present invention is not limited to this, and BST (barium strontium titanate) having a high dielectric constant may be used. Thereby, the capacity of the capacitor can be further increased.

[0152]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A semiconductor integrated circuit device having a capacitor that secures a sufficient capacitance in a limited plane area can be obtained.

(2) A capacitor having a lower electrode having excellent oxidation resistance can be obtained.

(3) A capacitor having a lower electrode which can secure a sufficient capacitance in a limited plane area and has excellent oxidation resistance can be obtained.

(4) By realizing a capacitor that secures a sufficient capacitance within a limited plane area, a semiconductor integrated circuit device with an increased refresh margin by increasing the amount of accumulated charge can be obtained.

(5) A semiconductor integrated circuit device which realizes low voltage and low power by increasing the amount of accumulated charge can be obtained.

(6) The collapse of the capacitor electrode during the capacitor manufacturing process can be prevented.

(7) The process of forming irregularities on the surface of the lower electrode can be simplified, and a capacitor can be manufactured that secures sufficient capacitance in a limited plane area.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 39 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 40 is an essential part cross sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 41 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 42 is a fragmentary cross-sectional view of the semiconductor substrate showing the DRAM according to the first embodiment of the present invention;

FIG. 43 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 44 (a) is a cross-sectional view schematically showing a principle of forming irregularities on a lower electrode constituting a DRAM capacitor in the present invention, and FIG. 44 (b) is a sectional structural view showing a principle of forming a DRAM capacitor in the present invention; FIG. 3 is a plan view schematically illustrating the principle of forming the irregularities.

FIG. 45 is a partial cross-sectional view of the semiconductor substrate showing a partially enlarged structure of FIG. 34;

FIG. 46 is a partial cross-sectional view of the semiconductor substrate showing a partially enlarged structure of FIG. 39;

FIG. 47 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 48 is a partial cross-sectional view of the semiconductor substrate showing the DRAM according to the second embodiment of the present invention;

FIG. 49 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 50 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 51 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 52 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the third embodiment of the present invention;

FIG. 53 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the third embodiment of the present invention;

FIG. 54 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the third embodiment of the present invention;

FIG. 55 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the third embodiment of the present invention;

FIG. 56 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the third embodiment of the present invention;

FIG. 57 is a partial cross-sectional view of a semiconductor substrate for describing the background upon which the method of manufacturing a DRAM according to the fourth embodiment of the present invention was invented;

FIG. 58 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fourth embodiment of the present invention;

FIG. 59 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fourth embodiment of the present invention;

FIG. 60 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fourth embodiment of the present invention;

FIG. 61 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fourth embodiment of the present invention;

FIG. 62 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fourth embodiment of the present invention;

FIG. 63 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 64 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the sixth embodiment of the present invention;

FIG. 65 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the seventh embodiment of the present invention;

FIG. 66 is an enlarged sectional view showing a part of FIG. 63;

FIG. 67 is an enlarged sectional structural view showing a part of FIG. 64;

FIG. 68 is an enlarged sectional view showing a part of FIG. 65;

FIG. 69 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 70 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 71 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 72 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 73 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the ninth embodiment of the present invention;

FIG. 74 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the ninth embodiment of the present invention;

FIG. 75 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the ninth embodiment of the present invention;

FIG. 76 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the tenth embodiment of the present invention.

FIG. 77 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to Embodiment 11 of the present invention;

FIG. 78 is an enlarged sectional structural view showing a part of FIG. 76;

FIG. 79 is an enlarged sectional view showing a part of FIG. 77;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A semiconductor chip 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 thin silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p-type well 12 n-type well 13 gate oxide film 14, 14A, 14B, 14C gate electrode 15 silicon nitride film 16 photoresist film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacer 21 the photoresist film 22 p ⁺ -type semiconductor region 23 n ⁺ -type semiconductor region 24 SOG film 25 a silicon oxide film 26 a silicon oxide film 27 a photoresist film 29 contact hole 30 plug 31 a silicon oxide film 32 a photoresist film 33 Fotore Strike film 34, 35, 36, 37 contact hole 38, 39 first layer wiring 40 silicon nitride film 41 photoresist film 42 titanium silicide layer 43 sidewall spacer 44 SOG film 45 silicon oxide film 46 silicon oxide film 47 photoresist film 48 Through hole 49 Plug 51 Silicon nitride film 52 Photoresist film 53 Silicon oxide film 54 Photoresist film 55 Groove 55a Frame-shaped groove 56 Titanium nitride film 56a Relatively wide amorphous grain boundary 56b Relatively narrow non-crystalline Grain boundaries in a crystalline state 57 SOG film 58 Photoresist film 60 Lower electrode (TiN film) 61 Capacitive insulating film (Ta ₂ O ₅ film) 62 Upper electrode (TiN film) 63 Photoresist film 64 Silicon oxide film 65 Photoresist film 66 , 66a, 66b Through Ho 67 Plug 68, 69 Second layer wiring 70 Metal plug 71 Silicon oxide film 72 SOG film 73 Silicon oxide film 74, 75 Through hole 76 Plug 77, 78, 79 Third layer wiring 80 Unevenness 81 Silicon oxide film 82 Groove 83 Titanium nitride Film 84 SOG film 85 lower electrode 86 tantalum oxide film 87 titanium nitride film 88 silicon nitride film 89 silicon oxide film 90 groove 91 titanium nitride film 92 SOG film 93 lower electrode 94 tantalum oxide film 95 titanium nitride film 96 titanium silicide 97 groove 98 oxidation Silicon film 99 Titanium nitride film 100 SOG film 101 Lower electrode 102 Tantalum oxide film 103 Titanium nitride film 104 Titanium nitride film 105 Ruthenium film 106 Lower electrode 107 Tantalum oxide film 108 Titanium nitride film 109 Titanium oxide film 110 L Ruthenium film 111 Lower electrode 112 Tantalum oxide film 113 Titanium nitride film 114 Titanium nitride film 115 Ruthenium film 116 Lower electrode 117 Tantalum oxide film 118 Ruthenium film 121 Titanium nitride film 122 Photoresist film 123 Lower electrode 124 Tantalum oxide film 125 Titanium nitride film 126 Titanium nitride film 127 Photoresist film 128 Lower electrode 129 Tantalum oxide film 130 Titanium nitride film 131 Titanium nitride film 132 Ruthenium film 133 Lower electrode 134 Titanium nitride film 135 Titanium oxide film 136 Ruthenium film 137 Lower electrode BL Bit line C Information storage capacitor Element MARY Memory array Qn N-channel MISFET Qp P-channel MISFET Qs MISFET for selecting memory cell SA Sense amplifier WD Word driver Bas

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Misuzu Kanai 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd.

Claims (22)

[Claims] 1. A memory cell selecting MISFET formed on a main surface of a semiconductor substrate, and the memory cell selecting MISFET.
FET connected in series with the FET,
A lower electrode connected to the source or drain of the FET,
A semiconductor integrated circuit device comprising: a capacitance insulating film formed in contact with the lower electrode; and an information storage capacitance element including an upper electrode formed to cover the lower electrode with the capacitance insulating film interposed therebetween. The lower electrode includes a metal film or a metal compound film having a polycrystalline structure, and has irregularities formed on its surface using a difference in etching rate at a crystal grain boundary of the metal film or the metal compound film. A semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said metal film is a transition metal film, and said metal compound film is a compound film of said transition metal film. apparatus. 3. The semiconductor integrated circuit device according to claim 1, wherein said metal film is a titanium film, a tungsten film, a ruthenium film or an iridium film, and said metal compound film is a titanium nitride film or a tungsten nitride film. And a ruthenium oxide film or an iridium oxide film. 4. The semiconductor integrated circuit device according to claim 1, wherein said lower electrode includes an oxide film of said metal film formed on a surface thereof. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein the lower electrode is a ruthenium film formed on a surface of the metal film, the metal compound film, or the oxide film. Alternatively, a semiconductor integrated circuit device including a ruthenium oxide film. 6. The semiconductor integrated circuit device according to claim 1, wherein said lower electrode is formed in a cylindrical shape having an upper opening. Integrated circuit device. 7. The semiconductor integrated circuit device according to claim 6, wherein a reinforcing member is formed on an outer wall of the cylindrical lower electrode. 8. The semiconductor integrated circuit device according to claim 6, wherein said semiconductor integrated circuit device is said memory cell selecting MIS.
A semiconductor integrated circuit device including a plug conductor connected to a source or a drain of an FET, wherein a titanium silicide film is formed at an interface of the plug conductor in contact with the lower electrode. 9. The semiconductor integrated circuit device according to claim 1, wherein said capacitance insulating film is made of a tantalum oxide film or a BST film, and said upper electrode is made of titanium nitride, ruthenium or oxide. A semiconductor integrated circuit device comprising a single layer film selected from ruthenium or a laminated film thereof. 10. The semiconductor integrated circuit device according to claim 1, wherein the average value h of the difference in height of the unevenness of the lower electrode is d with the thickness of the capacitive insulating film. The semiconductor integrated circuit device is selected in a range satisfying 0.5d ≦ h ≦ 5d. 11. A memory cell selecting MISFET and a memory cell selecting MIS on a main surface of a semiconductor substrate.
Forming an insulating film covering the FET, depositing a metal film or a metal compound film having a polycrystalline structure on the insulating film,
(B) forming irregularities on the surface by etching the metal film or the metal compound film, and then patterning the metal film or the metal compound film to form a lower electrode; (c) a surface of the lower electrode Depositing a capacitive insulating film on the capacitor insulating film;
(D) forming an upper electrode on the capacitive insulating film, and forming an information storage capacitive element comprising the lower electrode, the capacitive insulating film, and the upper electrode. Method. 12. A MISFET for selecting a memory cell and a MIS for selecting the memory cell on a main surface of a semiconductor substrate.
Forming an insulating film covering the FET and depositing a metal film or a metal compound film having a polycrystalline structure on the insulating film; (b) patterning the metal film or the metal compound film and then patterning the patterned metal Forming a lower electrode by forming irregularities on the surface of the film or the metal compound film by etching, (c) depositing a capacitive insulating film on the surface of the lower electrode;
(D) forming an upper electrode on the capacitor insulating film, and forming an information storage capacitor element including the lower electrode, the capacitor insulating film, and the upper electrode. A method for manufacturing a semiconductor integrated circuit device, comprising: 13. A memory cell selecting MISFET is formed on a main surface of a semiconductor substrate, and said memory cell selecting MISFET is formed.
Forming an insulating film having an opening on the ISFET, and then depositing a metal film or a metal compound film having a polycrystalline structure in the opening of the insulating film so as not to fill the opening, (b) (C) forming irregularities on the surface of the metal film or the metal compound film by etching the metal film or the metal compound film, and then removing the metal film or the metal compound film on the upper surface of the insulating film to form a cylindrical lower electrode; A) a step of oxidizing and reforming the capacitive insulating film after depositing a capacitive insulating film on the surface of the lower electrode; (d) forming an upper electrode on the capacitive insulating film; Forming a capacitance element for information storage composed of an upper electrode. 14. (a) A memory cell selecting MISFET is formed on a main surface of a semiconductor substrate, and the memory cell selecting MISFET is formed.
Forming a first insulating film having an opening on the ISFET, and then depositing a metal film or a metal compound film having a polycrystalline structure in the opening of the first insulating film so as not to fill the opening. (B) after embedding a second insulating film in the opening of the first insulating film, removing the metal film or the metal compound film on the second insulating film and the first insulating film; Etching the insulating film and the second insulating film to expose a cylindrical structure having an opening above the metal film or the metal compound film; and (c) etching the surface of the cylindrical structure by etching the surface. Forming a cylindrical lower electrode by forming irregularities on the lower electrode, (d) depositing a capacitive insulating film on the surface of the lower electrode, and then oxidizing and reforming the capacitive insulating film; Forming an upper electrode on the insulating film, Serial lower electrode, manufacturing method of a semiconductor integrated circuit device, which comprises a step, of forming the information storage capacitor comprising a capacitor insulating film and the upper electrode. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the unevenness on the surface of the lower electrode is at a crystal grain boundary of the metal film or the metal compound film. A method for manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is formed by utilizing a difference in etching rate. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the unevenness on the surface of the lower electrode is formed by using a wet etching solution containing a hydrogen peroxide solution. Forming a semiconductor integrated circuit device. 17. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein the metal forming the metal film or the metal compound film is a transition metal. Of manufacturing a semiconductor integrated circuit device. 18. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the metal film is a titanium film, a tungsten film, a ruthenium film, or an iridium film, and the metal compound film is a metal compound film. A titanium nitride film, a tungsten nitride film, a ruthenium oxide film, or an iridium oxide film. 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of forming an oxide film of a metal forming the metal film or the metal compound film on a surface of the metal film or the metal compound film is performed. A method for manufacturing a semiconductor integrated circuit device, comprising: 20. The method for manufacturing a semiconductor integrated circuit device according to claim 18, further comprising a step of forming a ruthenium film or a ruthenium oxide film on a surface of the metal film, the metal compound film, or the oxide film. A method for manufacturing a semiconductor integrated circuit device, comprising: 21. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein, in the step (a), the step of depositing the metal film or the metal compound film comprises: A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a reinforcing member in advance in a region around a region where the lower electrode is formed on a semiconductor substrate. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein in the step (a), before depositing the metal film or the metal compound film, MISFET for memory cell selection
Forming a plug conductor to be connected to the source or drain of the semiconductor device, and forming a titanium silicide film on the surface of the plug conductor.