JP2000299444A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent peeling in oxidation-reforming process by using a polycrystalline tantalum oxide film as a capacitor insulating film. SOLUTION: MISFETQs Qn, Qp, a plug 30, a bit line BL, and a plug 49 are sequentially formed on the main surface of a semiconductor substrate 1, a silicon nitride film 50 and a silicone oxide film 51 are deposited on a silicon oxide film 46, a lower part electrode 55 of, for example, titanium nitride is formed in a groove 52 formed at the silicon nitride film 50 and silicon oxide film 51, and then a silicon nitride film 56 is formed over the entire surface of the semiconductor substrate 1 through, for example, LPCVD method. Furthermore, an amorphous tantalum oxide film 57 is deposited by CVD method, and the tantalum oxide film 57 is thermally processed in an oxidizing atmosphere to form a polycrystaline tantalum oxide film. At this heat treatment, the silicon nitride film 50 functions as an oxygen diffusion preventing film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a DRAM (Dynamic Random Access Memory).
The present invention relates to a technology that is effective when applied to a semiconductor device having an access memory.

[0002]

2. Description of the Related Art As described in, for example, Japanese Patent Application Laid-Open No. H11-26712, there is known a DRAM having a capacitor over bit line structure in which an information storage capacitor is arranged above a bit line. Have been. This publication discloses a cylindrical lower electrode formed in a deep groove (hole) and a capacitor insulating film formed on the lower electrode as a capacitor (information storage capacitance element) for storing information as electric charge. And an upper electrode. The lower electrode is made of a polycrystalline silicon film, the capacitor insulating film is made of a polycrystalline tantalum oxide film, and the upper electrode is made of a titanium nitride film.
In general, even if the element is miniaturized, a storage capacitance value equal to or higher than a certain value is required regardless of the element size from the viewpoint of maintaining and improving the operational reliability such as anti-α rays. In such a capacitor as described above, the surface area of the electrode is increased by forming the lower electrode into a cylindrical shape in a deep groove, thereby coping with a decrease in the occupied area due to miniaturization of the element.

[0003] For example, on November 10, 1996
Published by the Japan Society of Applied Physics, “Applied Physics” Vol. 65, No. 11
As described in pp. 1106 to 113, the surface of the silicon as the lower electrode is formed with fine irregularities and roughened, and the surface area can be substantially increased without increasing the size of the lower electrode. Technology, so-called HSG (He
A technique of a mispherical silicon grain structure has been proposed.

[0004]

The HSG described in the above document
If the technique is applied to the cylindrical lower electrode described in the above-mentioned publication, it is expected that a substantial electrode surface area can be further increased without increasing a planar occupied area, and a capacitance value corresponding to miniaturization can be secured.

However, as the miniaturization is further advanced, the plane size of the deep groove (hole) itself decreases, and the size of the HSG itself causes the space inside the groove (hole) to be narrowed. If there is not enough space in the hole after the HSG is formed, a capacitor insulating film and an upper electrode having good covering properties cannot be formed, and normal formation of a capacitor is hindered. When the groove diameter is smaller than the HSG particle diameter, it is impossible to form a normal capacitor.

Therefore, in the study of further miniaturization,
A structure of a capacitor that can secure a required capacitance value without using HSG is desired. An example of such a capacitor structure is an MIM (Metal Insulator Metal) structure. MIS (Metal) using silicon as the lower electrode material
In the case of an Insulator Semiconductor) structure, the substantial thickness of the capacitor insulating film increases due to depletion of silicon, and it is difficult to secure a sufficient capacitance value. However, there is no concern about depletion in the MIM structure in which the lower electrode is made of metal.

In the study of the MIM structure of the present inventors, a dielectric material (capacitor insulating film) is made of BST (strontium-containing barium titanate crystal material: (Ba, Sr) T
iO ₃ ), and a capacitor structure using a platinum or ruthenium-based material excellent in compatibility with BST for the upper and lower electrodes.
BST has a high relative dielectric constant of 100 or more, and is expected to be a material capable of realizing high capacitor capacity in a small occupied area. However, the material development target of BST is high, and it is difficult to easily form a BST thin film as a high quality capacitor insulating material. Therefore, there is a tantalum oxide film (TaO) as a capacitor insulating film whose development goal is more realistic. In this case, platinum or ruthenium-based material is applied to the upper and lower electrodes. However, the platinum or ruthenium-based material is a new material that has not been used so far in the semiconductor device field, and it is necessary to newly develop not only the material but also the process of the processing step. Therefore, a technique of applying a material which has been frequently used in the past to the upper and lower electrodes is desired.

[0008] As such a commonly used electrode material, there is tungsten. An example in which a capacitor is formed by applying a tantalum oxide film as an insulating film and applying tungsten to an electrode material is described in, for example, July 2, 1988.
Published on 2nd, IEICE Journal, SDM88-44, p
25 to p30. This document states that tungsten and tantalum oxide have low thermal reactivity and can realize a capacitor having resistance to high-temperature heat treatment.

However, the present inventors have studied that heat treatment (annealing) in an oxidizing atmosphere such as oxygen is necessary to reduce the leak current of the tantalum oxide film to a practical level. When applied to the tantalum oxide film having the above-described structure, there is a problem that tungsten, which is a base of the tantalum oxide film, is oxidized. When such oxidation occurs, separation occurs between the underlying tungsten and the tantalum oxide film, causing a problem that a capacitor cannot be formed. Even in the case where separation does not occur, formation of a metal oxide having a low dielectric constant is unavoidable, resulting in a decrease in the capacitance value, and as a result, desired capacitor characteristics cannot be obtained.

On the other hand, a modification treatment of the tantalum oxide film so as not to oxidize the underlying electrode can be considered. For example, ozone (O ₃ ) plasma or low-temperature heat treatment in an ozone atmosphere. In such a reforming process, while the oxidizing power is strong,
The processing temperature can be reduced to 300 to 400 degrees. From this, the underlying metal is not oxidized to such an extent that the tantalum oxide film is peeled off, and the film quality of the tantalum oxide film can be improved such that the initial leak current is suppressed to a sufficiently low level. But,
Since the reforming temperature is low, the tantalum oxide film is in the same amorphous state as the as-deposited state and cannot be crystallized.
The amorphous tantalum oxide film has a problem that it has a low dielectric constant, poor heat resistance, and low mechanical strength. Therefore, it is difficult to obtain a capacitor having stable and good characteristics.

It has been confirmed that the lower electrode is similarly oxidized and peeled even when a metallic conductive material other than tungsten, such as titanium nitride, tungsten nitride or tantalum nitride, is used.

An object of the present invention is to use a metal or a metal compound material, such as tungsten, which has been widely used in the past for the lower electrode,
To provide a capacitor structure or a technology for manufacturing a capacitor using a tantalum oxide film as a capacitor insulating film, which can suppress occurrence of peeling or formation of a metal oxide having a low dielectric constant during oxidation heat treatment of the tantalum oxide film. It is in.

It is another object of the present invention to provide a stable lower electrode configuration and improve the production yield and reliability of a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

1. The semiconductor device of the present invention includes a lower electrode made of a metal or a metal compound formed so as to cover an inner surface in a hole of an insulating film, an upper electrode disposed to face the lower electrode, and an upper electrode and a lower electrode. What is claimed is: 1. A semiconductor device including an information storage capacitor comprising a capacitor insulating film formed therebetween, wherein the capacitor insulating film includes a polycrystalline tantalum oxide film and a metal and oxygen diffusion preventing film. Are formed between the lower electrode and the polycrystalline tantalum oxide film.

According to such a semiconductor device, since the diffusion preventing film is included between the lower electrode and the polycrystalline tantalum oxide film, the heat treatment in the oxidizing atmosphere when forming the polycrystalline tantalum oxide film is performed. In, the diffusion prevention film acts as a blocking film of oxygen that has passed through the tantalum oxide film,
Oxygen can be prevented from reaching the lower electrode. Thereby, oxidation of the lower electrode can be suppressed, and peeling of the polycrystalline tantalum oxide film can be suppressed. Further, it is possible to prevent the metal element forming the lower electrode from diffusing into the polycrystalline tantalum oxide film.

Incidentally, a silicon oxynitride film can be exemplified as the oxygen diffusion preventing film.

Further, a silicon nitride film can be arranged between the tantalum oxide film and the upper electrode. In this case, the leakage current when the upper electrode side is relatively positively biased can be reduced.

The polycrystalline tantalum oxide film can be composed of a plurality of layers. In this case, since the polycrystalline tantalum oxide film is composed of two layers, the leakage current can be reduced. That is,
According to the study of the present inventors, the occurrence of a leak current or a decrease in withstand voltage often occurs at a grain boundary portion of a tantalum oxide crystal. In such a case, when the crystal grain boundary penetrates from the front surface to the back surface of the polycrystalline tantalum oxide film, a leak current is likely to occur. However, when the polycrystalline tantalum oxide film is composed of two layers, the crystal grain boundaries do not penetrate from the front surface to the back surface of the polycrystalline tantalum oxide film, thereby reducing the leak current. In addition, when the polycrystalline tantalum oxide film is composed of two layers, each layer can be formed thinner as compared with the case where it is composed of one layer. In the case of a thin tantalum oxide film, good film quality can be obtained even if the load of the heat treatment is reduced, so that the total thermal load is reduced, and peeling of the tantalum oxide film hardly occurs. Further, since each layer is formed thin, the crystal grains can be formed uniformly and the grain size can be small and dense.

The lower electrode may be made of any material selected from titanium nitride, tungsten, tungsten nitride or tantalum nitride or a compound thereof, and the upper electrode may be made of titanium nitride. Thus MIM
By configuring the structure, the problem of depletion unlike when a silicon material is employed does not occur, and good capacitor characteristics can be obtained.

The lower electrode is formed in a groove of the first insulating film formed above the bit line of the DRAM, and the height of the tip of the lower electrode is higher than the height of the surface of the first insulating film. can do. In this case, since the lower electrode is formed so as to protrude above the first insulating film, a large surface area of the lower electrode can be utilized.

Alternatively, the lower electrode is formed in a groove of the first insulating film and the second insulating film formed above the bit line of the DRAM, and the height of the tip of the lower electrode is equal to the height of the surface of the second insulating film. Can be the same. In this case, since the lower electrode is formed without protruding into the grooves of the first insulating film and the second insulating film, the mechanical strength of the lower electrode is improved,
The yield and reliability of the DRAM can be improved.

2. According to the method of manufacturing a semiconductor device of the present invention, there is provided a MISFET on a main surface of a semiconductor substrate, a bit line on a first insulating film covering the MISFET, and a capacitor for storing information formed on a second insulating film on the bit line. (A) forming a third insulating film on a second insulating film and forming a groove in the third insulating film, and (b) a metal film covering an inner surface of the groove. Alternatively, a metal compound film is formed over the entire surface of the semiconductor substrate, a fourth insulating film that fills the groove is formed on the metal film or the metal compound film, and the fourth insulating film other than the groove and the metal film or the metal compound film are removed. (C) removing the fourth insulating film in the trench and exposing the lower electrode of the information storage capacitor made of a metal film or a metal compound film;
(D) forming a silicon nitride film on the entire surface of the semiconductor substrate, (e) depositing an amorphous tantalum oxide film on the silicon nitride film, and (f) forming the amorphous tantalum oxide film in an oxidizing atmosphere. Performing a heat treatment to crystallize the amorphous tantalum oxide film to form a polycrystalline tantalum oxide film; and (g) forming a metal film or a metal compound film on the polycrystalline tantalum oxide film.

According to such a method of manufacturing a semiconductor device, the above-described semiconductor device can be manufactured.

Further, after the step (f), a step of forming a second polycrystalline tantalum oxide film may be further provided. Thus, the first polycrystalline tantalum oxide film can be formed thin, and the heat load during the formation can be reduced. Also, the second
When the polycrystalline tantalum oxide film is formed, the first polycrystalline tantalum oxide film is previously formed as a base, so that a kind of epitaxial growth occurs when depositing the film for forming the second polycrystalline tantalum oxide film, and as-deposition occurs. A film crystallized to some extent in the state is obtained. Therefore, the heat load for forming the second polycrystalline tantalum oxide film can be reduced. Therefore, the heat treatment in the oxidizing atmosphere for the second polycrystalline tantalum oxide film can be performed at a lower temperature or in a shorter time than the heat treatment for the amorphous tantalum oxide film.

Further, before the step (g), a step of forming a silicon nitride film on the polycrystalline tantalum oxide film or the second polycrystalline tantalum oxide film may be further provided.

In the step (a), the etching rate is lower on the third insulating film than on the third insulating film, or
Forming a fifth insulating film having a low polishing rate by the CMP method,
In the step of removing the fourth insulating film and the metal film or the metal compound film in the step (b), the fifth insulating film can be used as a stopper film for etching or polishing by the CMP method.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to a first embodiment is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM of the first embodiment. As shown, the memory array (MARY) of the DRAM includes a plurality of word lines WL (WL0, WL1, WLn...) And a plurality of bit lines BL arranged in a matrix and a plurality of bit lines BL arranged at intersections thereof. It is composed of memory cells (MC). One memory cell that stores one bit of information is composed of one information storage capacitor C and one memory cell selection MISFET Qs connected in series to the capacitor C. One of the source and the drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is connected to a sense amplifier SA.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to the drawings. 3 to 19 are cross-sectional views showing an example of a manufacturing process of the DRAM of the first embodiment in the order of processes.

First, as shown in FIG. 3, an element isolation region and a well region into which impurities are introduced are formed.

That is, a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 10 Ωcm is prepared, and a film thickness of 10 nm formed by wet oxidation at about 850 ° C.
A thin silicon oxide film (not shown) and a silicon nitride film (not shown) having a thickness of about 140 nm formed by, for example, a CVD (Chemical Vapor Deposition) method are deposited on the semiconductor substrate 1. Here, a semiconductor substrate 1 made of single crystal silicon is exemplified, but an SOI (Silicon On Insulator) substrate having a single crystal silicon layer on the surface or a dielectric substrate such as glass or ceramics having a polycrystalline silicon film on the surface is used. You may.

Next, using the photoresist film (not shown) as a mask, the silicon nitride film and the silicon oxide film in the region where the groove 5 is to be formed are patterned, and the semiconductor substrate 1 is formed using the silicon nitride film as a mask. A groove 5 having a depth of about 300 to 400 nm is formed in the semiconductor substrate 1 in the element isolation region by dry etching.

Next, after removing the photoresist film, in order to remove a damaged layer formed on the inner wall of the groove 5 by the etching, a thin film (about 10 nm in film thickness) is formed by wet oxidation at about 850 to 900 ° C. A silicon oxide film 6) is formed on the inner wall of the groove 5 and is deposited by a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas (not shown). Is deposited in a thickness of about 300 to 400 nm. This silicon oxide film may be sintered (baked) at about 1000 ° C. by dry oxidation.

Next, the silicon oxide film is polished by a CMP method to remove the silicon oxide film in a region other than the groove 5.
An element isolation region is formed with the silicon oxide film 7 left inside the groove 5. Before polishing by the CMP method, grooves 5
By forming a silicon nitride film in the region of the above, dishing in which the silicon oxide film in the region of the groove 5 is polished excessively deep can be prevented.

Next, after the silicon oxide film and the silicon nitride film remaining on the surface of the semiconductor substrate 1 are removed by wet etching using, for example, hot phosphoric acid, the semiconductor in a region (memory array) where a memory cell is to be formed is formed. Substrate 1 with n
Type impurity, for example, P (phosphorus) is ion-implanted into n
The semiconductor region 10 is formed, and p is formed in a part of the memory array and the peripheral circuit (region for forming the n-channel MISFET).
A p-type well 11 is formed by ion-implanting a B-type impurity, for example, B (boron), and an N-type impurity, for example, P (phosphorus) is ion-implanted in another part of the peripheral circuit (a region for forming a p-channel MISFET). Driving and n-type well 12
To form Following this ion implantation, MI
An impurity for adjusting the threshold voltage of the SFET, for example, BF ₂ (boron fluoride) is added to the p-type wells 11 and n.
The mold well 12 is ion-implanted. n-type semiconductor region 1
0 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit or the like through the semiconductor substrate 1.

Next, the surface of the semiconductor substrate 1 is
After cleaning using a (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C., and a clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of the p-type well 11 and the n-type well 12. To form Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is
Nitrogen may be segregated at the interface between the gate oxide film 13 and the semiconductor substrate 1 by performing a heat treatment in a (nitrogen oxide) atmosphere or an N ₂ O (nitrous oxide) atmosphere (oxynitridation treatment). When the gate oxide film 13 is thinned to about 7 nm,
Distortion occurring at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to the difference in thermal expansion coefficient becomes apparent, and induces generation of hot carriers. Since the nitrogen segregated at the interface with the semiconductor substrate 1 relaxes the distortion, the oxynitridation can improve the reliability of the extremely thin gate oxide film 13.

Next, as shown in FIG. 4, a gate electrode, a cap insulating film, and a low-concentration impurity semiconductor region are formed.

That is, the gate electrodes 14A, 14B and 14C are formed on the gate oxide film 13. The gate electrode 14A forms a part of the memory cell selecting MISFET, and is used as a word line WL in a region other than the active region. The width of the gate electrode 14A (word line WL), that is, the gate length, is a minimum dimension (for example, an allowable range) that can suppress the short channel effect of the memory cell selecting MISFET and ensure a threshold voltage of a certain value or more. 0.24μm
Degree). Also, the adjacent gate electrode 14A
The interval between the (word lines WL) is constituted by a minimum dimension (for example, 0.22 μm) determined by the resolution limit of photolithography. Gate electrode 14B and gate electrode 14C
Constitute part of each of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

The gate electrode 14A (word line WL) and the gate electrodes 14B and 14C are formed by forming a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) on the semiconductor substrate 1 by a CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by a sputtering method, and a silicon nitride film 15 having a thickness of about 150 nm is further formed thereon. After deposition by the CVD method, these films are formed by patterning these films using a photoresist film as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN (titanium nitride) film or the like can be used in addition to the WN film.

Next, after removing the photoresist film, a dry etching residue, a photoresist residue, and the like remaining on the surface of the semiconductor substrate 1 are removed using an etching solution such as hydrofluoric acid. After the wet etching, the semiconductor substrate 1 may be wet-oxidized at about 900 ° C. to improve the quality of the cut gate oxide film 13.

Next, a p-type impurity, for example, B (boron) is ion-implanted into n-type well 12 to form gate electrode 14.
Ap ⁻ type semiconductor region 17 is formed in the n type well 12 on both sides of C. Further, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 11 to form an n ^- type semiconductor region 18 in the p-type well 11 on both sides of the gate electrode 14B.
An n-type semiconductor region 19 is formed in the p-type well 11 on both sides of the gate electrode 14A. As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG. 5, sidewall spacers are formed on both sides of the gate electrode, and a high-concentration impurity semiconductor region is formed.

That is, after a silicon nitride film 20 having a thickness of about 50 to 100 nm is deposited on the semiconductor substrate 1 by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film, and the silicon nitride film 20 of the peripheral circuit is formed. Is anisotropically etched to form sidewall spacers 20a on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do. In order to minimize the amount of the silicon nitride film 15 on the gate electrodes 14B and 14C, the amount of over-etching is kept to a minimum.

Next, after removing the photoresist film, a p-type impurity such as B
P-channel type MISF by ion implantation of (boron)
An ET p ⁺ -type semiconductor region 22 (source, drain) is formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type MISFET n ⁺ -type semiconductor region. 23 (source, drain) are formed. As a result, LDD (L
ightly Doped Drain) p-channel MIS with structure
The FET Qp and the n-channel MISFET Qn are formed.

Next, as shown in FIG. 6, a first interlayer insulating film and a plug are formed.

That is, a film thickness of 300 nm is formed on the semiconductor substrate 1.
After spin-coating about SOG (Spin On Glass) film 24, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to form S
The OG film 24 is sintered (baked). Also, S
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the OG film 24, the silicon oxide film 25 is polished by a CMP method to flatten the surface. Further, a silicon oxide film 2 having a thickness of about 100 nm is formed on the silicon oxide film 25.
6 is deposited. The silicon oxide film 26 is deposited to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. The silicon oxide films 25 and 26 are deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. PS instead of silicon oxide film 26
A G (Phospho Silicate Glass) film or the like may be deposited.

Next, the silicon oxide films 26, 25 and the SOG film 24 above the n-type semiconductor region 19 (source, drain) of the memory cell selecting MISFET Qs are removed by dry etching using a photoresist film as a mask.
This etching is performed under such conditions that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased.
9 and the silicon nitride film 2 covering the upper part of the isolation trench 5
Ensure that 0 is not completely removed. Subsequently, the n-type semiconductor region 19 of the MISFET Qs for memory cell selection is dry-etched using the photoresist film as a mask.
By removing the silicon nitride film 20 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed. This etching is performed under such conditions that the etching rate of the silicon nitride film 15 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. Make sure that 5 is not sharpened. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, after removing the photoresist film, dry etching residues and photoresist residues on the substrate surface exposed at the bottoms of the contact holes 28 and 29 are etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. Is removed.

Next, a plug 30 is formed inside the contact holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by a CVD method, and polishing the polycrystalline silicon film by a CMP method to form a contact hole. It is formed by leaving inside of 28 and 29.

Next, as shown in FIG. 7, a bit line and a first layer wiring (M1) are formed.

That is, after depositing a silicon oxide film 31 having a thickness of about 200 nm on the silicon oxide film 26, the semiconductor substrate 1 is heat-treated at about 800.degree. The silicon oxide film 31 is formed, for example, by a plasma CV using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.
Deposit by D method. As a result of this heat treatment, n-type impurities in the polycrystalline silicon film forming plug 30 are removed from the bottoms of contact holes 28 and 29 by MISFE for memory cell selection.
The TQs diffuses into the n-type semiconductor region 19 (source, drain), and the resistance of the n-type semiconductor region 19 is reduced.

Next, the silicon oxide film 31 above the contact hole 28 is removed by dry etching using a photoresist film as a mask to expose the surface of the plug 30.

Next, after removing the photoresist film, a new photoresist film is formed, and the silicon oxide films 31, 26, 25, the SOG film 24 and the gate of the peripheral circuit region are formed by dry etching using the photoresist film as a mask. Oxide film 1
3 is removed. Thereby, the n-channel MISFET
Contact holes 34 and 35 are formed above the n ⁺ -type semiconductor region 23 (source and drain) of Qn, and the p ⁺ -type semiconductor region 22 (source and drain) of the p-channel type MISFET Qp is formed.
Contact holes 36 and 37 are formed above the drain).

Next, after removing the photoresist film, the bit line BL and first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. Bit line B
To form the L and first layer wirings 38 and 39, first, a Ti film having a thickness of about 50 nm is deposited on the silicon oxide film 31 by a sputtering method, and the semiconductor substrate 1 is heat-treated at about 800.degree. Next, a TiN film having a thickness of about 50 nm is deposited on the Ti film by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are patterned using the photoresist film as a mask.

After a Ti film is deposited on the silicon oxide film 31, the semiconductor substrate 1 is heat-treated at about 800 ° C., so that the Ti film reacts with the underlying Si to form an n-channel type M.
Surface of n ⁺ -type semiconductor region 23 (source, drain) of ISFET Qn, surface of p ⁺ -type semiconductor region 22 (source, drain) of p-channel MISFET Qp, and plug 3
0 surface and low resistance TiSi ₂ (titanium silicide)
Layer 42 is formed. Thereby, the n ⁺ type semiconductor region 2
3. The contact resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to p ⁺ type semiconductor region 22 and plug 30 can be reduced. In addition, bit line B
By configuring L with a W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the information reading speed and the writing speed can be improved, and the bit line BL and the periphery can be improved. Since the first layer wirings 38 and 39 of the circuit can be formed simultaneously in one step, the DRAM manufacturing steps can be shortened.
Further, when the first layer wirings (38, 39) of the peripheral circuit are formed of the same layer as the bit line BL, the peripheral wiring is more peripheral than the case where the first layer wiring is formed of the upper layer Al wiring of the memory cell. MISFET (n-channel MISFETQ)
Since the aspect ratio of the contact holes (34 to 37) connecting the n-channel and p-channel MISFETs Qp) to the first layer wiring is reduced, the connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width. The interval between the bit lines BL is, for example, about 0.24 μm, and the width is, for example, about 0.22 μm.

Next, after removing the photoresist film, sidewall spacers 43 are formed on the side walls of the bit lines BL and the side walls of the first layer wirings 38 and 39. The sidewall spacer 43 is formed by depositing a silicon nitride film on the bit line BL and the first layer wirings 38 and 39 by the CVD method, and then anisotropically etching the silicon nitride film.

Next, as shown in FIG. 8, a second interlayer insulating film and a plug are formed.

That is, an SOG film 44 having a thickness of about 300 nm is spin-coated on the bit lines BL and the first layer wirings 38 and 39. Next, the semiconductor substrate 1 is heated at 800 ° C.,
The heat treatment is performed for about a minute, and the SOG film 44 is sintered (sintered). The SOG film 44 has a higher reflow property than the BPSG film and an excellent gap fill property between fine wirings, so that the gap between the bit lines BL miniaturized to the resolution limit of the photolithography can be improved. Can be embedded.

Next, a 600 nm thick film is formed on the SOG film 44.
After the silicon oxide film 45 is deposited to a degree, the silicon oxide film 45 is polished by a CMP method to planarize the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, a film thickness of 1
A silicon oxide film 46 of about 00 nm is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. The silicon oxide film 46 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, the silicon oxide films 46 and 45, the SOG film 44 and the silicon oxide film 31 above the contact hole 29 are removed by dry etching using a photoresist film as a mask, and the through hole 48 reaching the surface of the plug 30 is formed. To form This etching is performed under such a condition that the etching rate of the silicon nitride film with respect to the silicon oxide films 46, 45, 31 and the SOG film 44 becomes small. Silicon nitride film 4 above BL
0 and the side wall spacer 43 are not cut deeply. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after removing the photoresist film, a dry etching residue and a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. Is removed.

Next, the plug 4 is inserted into the through hole 48.
9 is formed. Plug 49 is made of, for example, a silicon oxide film. The plug 49 is formed by depositing, for example, a polycrystalline silicon film on the silicon oxide film 46 by a CVD method, etching back the film, and leaving it inside the through hole 48. The etch-back method may be replaced with the CMP method.

Next, as shown in FIG. 9, an insulating film for forming a capacitor (capacitive element for storing information) is formed, and a groove for forming a capacitor is formed in the insulating film.

That is, a silicon nitride film 50 and a silicon oxide film 51 are sequentially deposited on the silicon oxide film 46. The silicon nitride film 50 and the silicon oxide film 51
For example, it can be formed by a CVD method.

The silicon nitride film 50 is formed in a groove 5 described later.
It also functions as an etching stopper in the processing of No. 2 and the film thickness necessary to fulfill the stopper function can be selected. The thickness of the silicon nitride film 50 can be, for example, 200 nm.

The silicon oxide film 51 is formed for processing the lower electrode of the capacitor.
Lower electrode surface area (electrode area) that can secure required capacitance value
Can be calculated from The electrode area required for the lower electrode depends on the area occupied by the capacitor, or the thickness and dielectric constant of the capacitor insulating film.

Next, a photoresist film is patterned on the silicon oxide film 51 and the plug 4
A groove 52 is formed so that 9 is exposed. The groove 52 is processed by a dry etching method having anisotropy. First, the first etching is performed under selective etching conditions in which the etching rate of the silicon oxide film is high and the etching rate of the silicon nitride film is low. At this time, since the silicon nitride film 50 is hard to be etched, it functions as an etching stopper in the first etching. Next, a second etching is performed under the condition that the silicon nitride film is easily etched. Thereby, the silicon nitride film 50 is etched to form the groove 52. By using such two-stage etching, excessive etching of the silicon oxide film 46 can be prevented.

After the formation of the groove 52, it is preferable to remove the damaged layer on the surface of the plug 49 which has been subjected to the etching.

Next, as shown in FIG. 10, a metal compound film 53 made of, for example, titanium nitride (TiN) is deposited. The metal compound film 53 is electrically connected to the plug 49. The metal compound film 53 is to be a lower electrode of the capacitor as described later, and is deposited along the inner surface of the groove 52 as shown. Since the groove 52 is generally finely processed, it is necessary to form the metal compound film 53 with excellent step coverage (step coverage). For the formation of the metal compound film 53, for example, in the case of titanium nitride, titanium tetrachloride (TiCl ₄ ) and ammonia (NH ₃ ) are used as source gases,
It can be formed by a CVD method under a temperature condition of 700 degrees or less. By using the CVD method, a titanium nitride film having excellent step coverage can be formed.

Further, since the metal compound film 53 needs to be formed along the inner surface of the groove 52 as described above, that is, since the surface of the metal compound film 53 in the groove 52 needs to be concave, As the film thickness, a film thickness satisfying the above requirements is selected. For example, 40 nm can be exemplified.

As described above, since the metal compound film 53 is formed as a conductive film to be a lower electrode later, the problem of depletion does not occur as compared with a conventionally used polycrystalline silicon film.
Thereby, the capacitor characteristics can be improved. When a polycrystalline silicon film is used, heat treatment at a high temperature (impurity activation) is required to suppress the problem of depletion. In this embodiment, the heat treatment at a high temperature is not performed. It is not necessary, and it is possible to reduce the problem of the diffusion of the impurity semiconductor region already formed and the heat resistance of the contact portion.

The metal compound film 53 is made of tungsten (W) or tungsten nitride (W) instead of titanium nitride.
N) or tantalum nitride (TaN) can be used.

Next, as shown in FIG. 11, an insulating film 54 is formed so as to fill the groove 52. The insulating film 54 can be, for example, an SOG film. In the case of using the SOG film, the insulating film 5 is removed when the insulating film 54 described later is removed.
4 can be selectively removed. The burying of the insulating film 54 can be performed by forming the insulating film 54 over the entire surface of the semiconductor substrate 1 and then removing the insulating film 54 by an etch-back method or the like. In addition,
As the insulating film 54, a resist film or the like can be used instead of the SOG film.

Next, as shown in FIG. 12, the metal compound film 53 other than the region of the groove 52 is removed by using the CMP method.
Thereby, the lower electrode 55 of the capacitor made of the metal compound film 53 is formed in the groove 52. An etch-back method can be used to remove the metal compound film 53. However, when the etch-back method is used, the tip of the lower electrode 55 tends to be formed into a sharp shape, and the reliability of the insulating film is reduced. This is not preferable from the viewpoint of alleviating the electric field concentration. This point, CMP
When the method is used, the tip of the lower electrode 55 is formed flat, and the above-mentioned problems of electric field concentration and lowering of the reliability of the insulating film hardly occur.

Next, as shown in FIG. 13, the insulating film 54 is removed by, for example, a wet etching method. At this time, the surface of the silicon oxide film 51 is also partially etched, so that the upper end of the lower electrode 55 is partially protruded.
As described above, since the upper end of the lower electrode 55 is formed so as to partially protrude, both surfaces of the front surface and the back surface of the lower electrode 55 contribute to the electrode area in this protruding portion. This allows
When the same occupied plane area and the same height are used, the electrode area can be increased and the capacitor capacitance can be increased as compared with the case where the lower electrode 55 is almost completely embedded in the groove 52.

Next, as shown in FIG.
A silicon nitride film 56 is formed on the entire surface of the substrate. The silicon nitride film 56 functions as an oxygen diffusion preventing film for suppressing the lower electrode 55 from being oxidized when the tantalum oxide film is subsequently heat-treated in an oxidizing atmosphere. Further, it has a function of preventing the metal constituting the lower electrode from diffusing into the polycrystalline tantalum oxide film by the heat treatment.
The silicon nitride film 56 is formed, for example, by LPCVD (Low Pressu).
re Chemical Vapor Deposition) method can be used. As a forming condition, the raw material gas is dichlorosilane (S
iH ₂ Cl ₂ ) and ammonia, the temperature can be 700 ° C., and the atmosphere can be a pressure lower than the atmospheric pressure. The thickness of the silicon nitride film 56 is 3 nm or less, preferably 1 to 1.5
nm. As a film forming device, the residual oxygen concentration is low,
Further, a single-wafer (including two-wafer) processing apparatus having a small heat load is preferable.

Next, as shown in FIG.
A tantalum oxide film 57 having a thickness of about 10 nm is deposited on the entire surface of the substrate. The tantalum oxide film 57 is deposited by, for example, pentaethoxy tantalum (Ta (C ₂ H ₅ O) ₅ ) and oxygen (O ₂ ).
Is used as a raw material gas and is 500 ° C. or less (for example, 450 ° C. to 5
00 ° C.) and reduced pressure below atmospheric pressure (eg,
(00 mTorr) by a thermal CVD method.

As described above, the tantalum oxide film 57 is heated CV
By depositing by the D method, a tantalum oxide film 57 having excellent step coverage can be obtained.

The tantalum oxide film 57 formed at this stage
Is an amorphous thin film. In addition, in the as-deposited state, there are many oxygen vacancies, so that the leakage current is large and cannot be practically used as a capacitor insulating film.

Next, as shown in FIG. 16, a heat treatment is applied to the tantalum oxide film 57 (the heat treatment is indicated by a white down arrow in the figure) to form a polycrystalline tantalum oxide film 58. The heat treatment of the tantalum oxide film 57 is performed in an oxidizing atmosphere (for example, an oxygen atmosphere) at 820 ° C. or lower (for example, at about 800 ° C. for 3 minutes). By such an oxidizing heat treatment, the amorphous tantalum oxide film 57 can be crystallized to form the polycrystalline tantalum oxide film 58. This oxidation heat treatment is a means for replenishing oxygen to oxygen defects to recover the defects, and a means for crystallizing the amorphous tantalum oxide film. Since the crystallized tantalum oxide film has a large dielectric constant and can reduce the surface area of the capacitor, high integration is possible.

In this embodiment, since the silicon nitride film 56 is formed at the interface between the lower electrode 55 and the tantalum oxide film 57, oxygen from an oxidizing atmosphere (this oxygen is thermally activated and reacts However, the active oxygen does not reach the surface of the lower electrode 55 because the silicon nitride film 56 impedes (blocks) the permeation of the tantalum oxide film 57 even though it permeates the tantalum oxide film 57. As a result, the titanium nitride forming the lower electrode 55 is not oxidized, and the tantalum oxide film 57 (polycrystalline tantalum oxide film 58)
And no metal oxide (for example, TiO) having a low dielectric constant is formed. Thereby, a high-performance capacitor can be formed.

The permeated oxygen reacts with the silicon nitride film 56. At this stage, the silicon nitride film 56 is converted into a silicon oxynitride (SiON) film 59.

Although the silicon nitride film 56 is illustrated here, any other film is not limited to the silicon nitride film as long as it has a function of preventing diffusion of oxygen. At this time, it is advantageous that the dielectric constant of the coating is large.

Next, as shown in FIG. 17, a titanium nitride film 60 is deposited on the polycrystalline tantalum oxide film 58. For the deposition of the titanium nitride film 60, the above-described method and conditions can be selected.
The titanium nitride film 60 is to be the upper electrode of the capacitor later. By forming the upper electrode with the titanium nitride film 60 in this manner, the lower electrode 55
(For example, titanium nitride) does not cause the problem of depletion.

Next, as shown in FIG. 18, a photoresist film is formed on titanium nitride film 60, and using this photoresist film as a mask, titanium nitride film 60, polycrystalline tantalum oxide film 58 and silicon oxynitride film 59 are formed. Is etched to form a capacitor insulating film composed of a polycrystalline tantalum oxide film 58 and a silicon oxynitride film 59 and an upper electrode 61 composed of a titanium nitride film 60. In this manner, an information storage capacitor C composed of a lower electrode 55 made of, for example, titanium nitride, a capacitor insulating film made of a polycrystalline tantalum oxide film 58 and a silicon oxynitride film 59 and an upper electrode 61 made of titanium nitride is formed. I do. This allows
A memory cell of the DRAM constituted by the memory cell selection MISFET Qs and the information storage capacitor C connected in series to the MISFET Qs is completed.

As a material for forming the upper electrode 61, a tungsten film or the like can be used instead of the titanium nitride film.

Next, a silicon oxide film 62 having a thickness of about 40 nm is deposited on the information storage capacitor C. The silicon oxide film 62 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. Further, the region where the memory cell is formed is flattened by applying the SOG film 63, and at the same time, the level difference from the peripheral circuit region is reduced.

Next, as shown in FIG. 19, first etching of the peripheral circuit is performed by dry etching using a photoresist film as a mask.
By removing the SOG film 63 and the like above the layer wiring 38, a through hole 64 is formed. Similarly, a through hole 65 is formed by removing the SOG film 63 and the silicon oxide film 62 on the upper electrode 61. After that, a plug 66 is formed inside the through holes 64 and 65, and then a second layer wiring 67 is formed above the SOG film 63. The plug 66 is formed by depositing a TiN film having a thickness of about 100 nm on the SOG film 63 by a sputtering method and further depositing a W film having a thickness of about 500 nm on the TiN film by a CVD method. Through hole 6
4 and 65 are formed by leaving them inside. The second layer wiring 67 is formed by depositing a TiN film having a thickness of about 50 nm, an Al (aluminum) film having a thickness of about 500 nm, and a Ti film having a thickness of about 50 nm on the SOG film 63 by sputtering.
These films are formed by patterning by dry etching using a photoresist film as a mask.

Thereafter, a third layer wiring is formed via an interlayer insulating film, and a passivation film composed of a silicon oxide film and a silicon nitride film is deposited thereon, but is not shown. Through the above steps, the DR of the present embodiment
AM is almost completed.

The third layer wiring and the plugs connected to it can be formed in the same manner as the second layer wiring.
The interlayer insulating film is, for example, a silicon oxide film having a thickness of about 300 nm, an SOG film having a thickness of about 400 nm, and a film having a thickness of 300 nm.
It can be composed of a silicon oxide film of a degree. The silicon oxide film can be deposited, for example, by a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

According to the present embodiment, since silicon nitride film 56 is formed between lower electrode 55 and tantalum oxide film 57 (polycrystalline tantalum oxide film 58), the oxidation heat treatment of tantalum oxide film 57 is performed. At this time, permeation (diffusion) of oxygen from the tantalum oxide film 57 side can be prevented, and oxidation of the lower electrode 55 (for example, titanium nitride) can be prevented. Thereby, peeling of the polycrystalline tantalum oxide film 58 and formation of a low dielectric constant metal oxide (for example, TiO) on the surface of the lower electrode 55 are suppressed. This constitutes a high-performance capacitor,
M can be highly integrated and performance can be improved.

Further, since the upper end of the lower electrode 55 is formed higher than the elevation of the surface of the silicon oxide film 51, the electrode area of the capacitor can be increased at the upper end of the lower electrode 55, so that the DRAM can be highly integrated (miniaturized). ).

As shown in FIG. 29, a metal silicide film 74 can be formed on plug 49 made of polycrystalline silicon. Such a metal silicide film 7
4. Lower electrode 55 made of metal or metal compound
And the plug 49 made of silicon can be prevented from being thermally reacted. Even with the lower electrode 55 made of titanium nitride as described above, a thermal reaction between titanium nitride and silicon may occur during the oxidation heat treatment of the tantalum oxide film. When such a reaction occurs, the capacitor characteristics may be degraded due to volume expansion in the reaction section, and this can be prevented. In the case where tungsten is used for the lower electrode 55, the reaction between silicon and tungsten easily occurs, so that the effect is particularly large.

When tungsten is used for the lower electrode 55, a thin titanium nitride film can be deposited before forming a tungsten film in the trench 52, and then a tungsten film can be deposited by, for example, a CVD method. Thereafter, the lower electrode 55 can be formed as described above.

The lower electrode 55 is formed of tantalum nitride (Ta).
When N) is used, a tantalum nitride film can be formed by reducing the tantalum oxide film with ammonia as described below. That is, instead of the metal compound film 53, a tantalum oxide film is formed on the entire surface of the semiconductor substrate 1 under conditions for forming a dielectric. This film thickness can be set arbitrarily. After that, heat treatment is performed in an ammonia atmosphere. When the thickness of the tantalum oxide film is, for example, 50 nm, all the tantalum oxide film can be converted to a tantalum nitride film by performing the treatment at 750 ° C. for 5 minutes in an ammonia atmosphere of about 1 atm. The tantalum oxide film is an insulator, but when converted to a tantalum nitride film, it becomes a conductor and can be applied to the lower electrode 55. The heat treatment conditions can be set according to the thickness of the tantalum oxide film. For example, if the tantalum oxide film is about 10 nm, it can be sufficiently converted into a tantalum nitride film by treating at 700 ° C. in an ammonia atmosphere at 1 atm for about 3 minutes. . In general, when the tantalum oxide and the silicon or titanium compound are heat-treated in a contact state, oxygen in the tantalum oxide becomes an oxidizing agent, and silicon oxide or titanium oxide is formed at the interface to deteriorate the capacitor characteristics. However, when heat treatment is performed in an ammonia atmosphere as described above, formation of an undesirable oxide is not performed. Therefore, there is little need to form the metal silicide film 74 on the surface of the plug 49 as described above.

(Embodiment 2) FIGS. 20 to 23 are sectional views showing an example of a manufacturing process of a DRAM of Embodiment 2 in the order of steps. The DRAM of the present embodiment is different from the first embodiment in the structure and manufacturing method of the capacitor insulating film, and the other configuration is the same as that of the first embodiment. Therefore, in the following description, different parts will be described, and description common to the first embodiment will be omitted.

The manufacturing method of this embodiment is the same as that of the first embodiment.
Are similar to the steps up to FIG. A silicon nitride film 56 is formed in the same manner as described in the first embodiment, and then a first tantalum oxide film 68 is deposited on silicon nitride film 56 as shown in FIG. The method of depositing the first tantalum oxide film 68 is the same as that of the tantalum oxide film 57 of the first embodiment, but the thickness is different. The thickness of the first tantalum oxide film 68 is 4 nm. The first tantalum oxide film 68 in the as-deposited state is amorphous similarly to the tantalum oxide film 57 of the first embodiment.

Next, as shown in FIG. 21, the first tantalum oxide film 68 is subjected to a heat treatment in an oxidizing atmosphere in the same manner as in the first embodiment, and the first tantalum oxide film 68 is crystallized. One polycrystalline tantalum oxide film 69 is formed. At this time, the silicon nitride film 56 becomes the silicon oxynitride film 70.

As described above, the same heat treatment as in Embodiment 1 is performed, but the heat treatment conditions are different in this embodiment. That is, since the thickness of the first tantalum oxide film 68, which is the film to be processed, is as thin as 4 nm, the oxidation heat treatment can be performed with a lower thermal load than in the first embodiment. In this embodiment, the heat treatment is performed at 800 ° C. for one minute. Compared with the first embodiment, the time can be reduced by two minutes. Here, an example in which the processing time is shortened to reduce the heat load is shown, but the processing time may be reduced by setting the same time (3 minutes). Since the oxidation heat treatment is performed under the reduced heat load condition, the effect of preventing the oxygen diffusion of the silicon nitride film 56 can be given, or the degree of conversion of the silicon nitride film 56 to the silicon oxynitride film can be reduced. You. Therefore, a decrease in the dielectric constant of the silicon oxynitride film 70 is suppressed,
The capacitance of the capacitor can be increased. Also, since the silicon nitride film 56 has a sufficient oxygen diffusion preventing effect,
The designed thickness of the silicon nitride film 56 can be reduced. If the thickness of the silicon nitride film 56 can be reduced, the effective film thickness of the capacitor insulating film can be effectively reduced, and the capacitance of the capacitor can be increased to achieve higher integration and higher performance of the capacitor.

Next, as shown in FIG. 22, a second tantalum oxide film 71 is deposited on the first polycrystalline tantalum oxide film 69. The method of depositing the second tantalum oxide film 71 is the same as that of the tantalum oxide film 57 of the first embodiment, but the thickness is 6
nm.

Since the second tantalum oxide film 71 is formed on the first polycrystalline tantalum oxide film 69, a kind of epitaxial growth occurs due to the crystallinity of the base.
Therefore, the second tantalum oxide film 71 has already been crystallized in an as-deposited state, and is a polycrystalline tantalum oxide film. Therefore, heat treatment for crystallizing the second tantalum oxide film 71 is not required.

However, although crystallization is performed at the film formation stage as described above, oxygen defects are present, and it is preferable to perform oxidation heat treatment for defect recovery. In this embodiment, as shown in FIG. 23, similar oxidation heat treatment is performed to recover oxygen defects in the second tantalum oxide film 71, which is a polycrystalline tantalum oxide film. However, the heat treatment for this defect recovery does not require a higher heat load than the heat treatment for crystallization, and a short heat treatment is sufficient. The conditions of such heat treatment are 800 ° C. in an oxidizing atmosphere,
A condition of 0.5 minutes can be exemplified.

As described above, in the present embodiment, the lower layer (first
A tantalum oxide film capacitor insulating film composed of two layers, a polycrystalline tantalum oxide film 69) and an upper layer (second tantalum oxide film 71) is provided. As described above, the two-layer structure reduces the heat treatment load for crystallization of each layer or the recovery of oxygen vacancies and produces the above-described effect. However, the total heat for forming the capacitor insulating film is further reduced. The load can be reduced. Accordingly, impurity diffusion in the impurity semiconductor region that has already been formed can be suppressed, and the reliability of a portion where the heat resistance is insufficient, such as a contact portion, can be improved.

Further, since the tantalum oxide film 68 is formed with a small thickness and is crystallized, crystal grains can be formed uniformly, and finally a capacitor insulating film having a uniform crystal can be formed. . In addition, since the crystal grain boundaries are divided in the thickness direction of the polycrystalline tantalum oxide film, leakage current can be reduced. As a result, the reliability of the capacitor insulating film can be improved and the reliability of the DRAM can be improved.

The following steps are the same as those in the first embodiment, and the description is omitted.

[0111] Although a polycrystalline tantalum oxide film having a two-layer structure has been illustrated here, a multi-layer structure of two or more layers may be used.

In the capacitor having a two-layered polycrystalline tantalum oxide film of the present embodiment, the leakage current characteristic can be greatly improved as shown by a curve B in FIG. FIG. 30 is a graph showing data obtained by experimenting the effect of the present invention. The horizontal axis indicates the voltage applied to the upper electrode, and the vertical axis indicates the leak current density. In this case, the lower electrode is at the ground potential, and the voltage applied to the upper electrode is the voltage applied between the capacitor insulating films.

In FIG. 30, a curve A indicates that a 10-nm-thick tantalum oxide film is formed at one time and is subjected to an oxidation reforming treatment (heat treatment).
Is not performed. Very poor insulation
Not practical. Similar results were obtained when an experiment was conducted by selecting a portion that was not peeled off when only the tantalum oxide film was formed without forming the silicon nitride film 56.

On the other hand, the characteristic (curve B) in the case of the present embodiment has a significantly improved leak current and shows extremely excellent characteristics. The curve C will be described later.

(Embodiment 3) FIG. 24 shows Embodiment 3 of the present invention.
FIG. 14 is a cross-sectional view showing one example of a manufacturing process of the DRAM of FIG. The DRAM of the present embodiment is different from the first embodiment in the structure of the capacitor insulating film, and the other configuration is the same as that of the first embodiment. Therefore, in the following description, different parts will be described, and description common to the first embodiment will be omitted.

The manufacturing method of this embodiment is the same as that of the first embodiment.
The same applies to the steps up to FIG. Polycrystalline tantalum oxide film 58 as described in the first embodiment.
Then, as shown in FIG. 24, a silicon nitride film 72 is formed. The silicon nitride film 72 can be formed by LPCVD as in the first embodiment. The thickness of the silicon nitride film 72 is 1.5 nm. Since the silicon nitride film 72 is added as a capacitor insulating film, the thickness of the polycrystalline tantalum oxide film 58 is reduced in the first embodiment in order to suppress a capacitance loss (a decrease in capacitance value due to an effective increase in the insulating film thickness). Is set to 10 nm, but is set to 5 nm here. As the thickness of the polycrystalline tantalum oxide film 58 decreases, the oxidation heat treatment time can be shortened. The heat treatment time is, for example, 1 minute. Other heat treatment conditions are the same as in the first embodiment. Subsequent steps are the same as in the first embodiment.

When the capacitor insulating film has a three-layer structure of a silicon oxynitride film / a polycrystalline tantalum oxide film / a silicon nitride film as in this embodiment, when the upper electrode 61 side is relatively positively biased. Leakage current can be reduced. That is, when the silicon nitride film is not formed on the upper electrode 61 side as in the present embodiment, the upper electrode 61
When the sides are relatively positively biased, there is a problem that the leakage current increases as compared with when the side is negatively biased. However, the above problem can be avoided if the capacitor insulating film is configured as in the present embodiment. The leakage current characteristic of the capacitor of the present embodiment is shown by a curve C in FIG. It can be seen that the leakage current on the positive bias side is reduced as compared with the case of the second embodiment (curve B). It is more effective to convert the silicon nitride film 72 to a silicon oxynitride film.

In this embodiment, the case where the polycrystalline tantalum oxide film has a single layer has been described. However, the polycrystalline tantalum oxide film may have a multilayer structure by applying the method of the second embodiment. is there.

(Fourth Embodiment) FIGS. 25 to 28 are cross-sectional views showing an example of a manufacturing process of a DRAM of a fourth embodiment in the order of processes. The DRAM of the present embodiment is different from the first embodiment in the structure and the manufacturing method of the lower electrode and the insulating film for forming the lower electrode, and the other configuration is the same as the first embodiment. Therefore, in the following description, different parts will be described, and description common to the first embodiment will be omitted.

The manufacturing method of the present embodiment is similar to that of the first embodiment.
The same applies to the steps up to FIG. As described in the first embodiment, a silicon nitride film 50 and a silicon oxide film 51 are formed, and a silicon nitride film 73 is further deposited. The silicon nitride film 73 can be deposited by a CVD method or a sputtering method.

Next, as in the step of FIG. 9 of the first embodiment, the silicon nitride film 73, the silicon oxide film 51, and the silicon nitride film 50 are etched to form the groove 52.
Thereafter, a metal compound film 53 is formed in the same manner as in the step of FIG. 10 of the first embodiment (FIG. 25).

Next, FIGS. 11 and 12 of the first embodiment.
In the same manner as in the step, the insulating film 54 filling the groove 52 and the metal compound film 53 other than the region of the groove 52 are removed to form the lower electrode 55 (FIG. 26).

Next, the insulating film 54 is removed in the same manner as in the step of FIG. 13 of the first embodiment (FIG. 27). At this time, since the silicon nitride film 73 has been formed,
Even if wet etching is performed on the insulating film 54 made of G, the silicon nitride film 73 is hardly etched. Therefore, the upper end of the lower electrode 55 does not protrude.

The protrusion of the upper end of the lower electrode 55 has the effect of increasing the capacitance value since the outer wall portion of the protrusion also contributes to the electrode area forming the capacitor. However, when the cell size is reduced and the thickness of the lower electrode itself has to be reduced, cracks occur at the protruding portions, causing problems such as scattering. Such a problem undesirably causes a decrease in manufacturing yield. However, in the present embodiment, no projection is formed at the upper end of the lower electrode 55, so that the mechanical strength can be maintained at a sufficient level even if the film thickness of the lower electrode 55 is reduced. Therefore, DRA caused by the above problem
The production yield of M does not decrease.

Thereafter, DR is performed in the same process as in the first embodiment.
The AM is completed (FIG. 28).

According to the present embodiment, stable lower electrode 5
5 can be provided, and a decrease in the manufacturing yield of the DRAM can be prevented.

It goes without saying that the structure of the capacitor insulating film of the second and third embodiments can be applied to the lower electrode structure of the present embodiment.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the first to fourth embodiments, the DRA
Although M has been described, the present invention is also applicable to a system LSI or the like in which a DRAM and a logic circuit such as an arithmetic circuit are mounted on one chip.

[0130]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a capacitor using a conventionally used metal or metal compound material such as tungsten for the lower electrode and using a tantalum oxide film for the capacitor insulating film, peeling occurs during the oxidation heat treatment of the tantalum oxide film, or The formation of a metal oxide having a low dielectric constant can be suppressed.

Further, it is possible to provide a stable lower electrode configuration, and to improve the production yield and reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM of the first embodiment.

FIG. 3 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 4 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 5 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 6 is a cross-sectional view showing an example of the manufacturing process of the DRAM according to the first embodiment in the order of steps;

FIG. 7 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 8 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 9 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 10 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 11 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 12 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 13 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 14 is a sectional view illustrating an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 15 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 17 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 18 is a sectional view illustrating an example of a manufacturing process of the DRAM according to the first embodiment in the order of steps;

FIG. 19 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 20 is a cross-sectional view showing an example of a manufacturing step of the DRAM according to another embodiment of the present invention in the order of steps;

FIG. 21 is a cross-sectional view showing an example of the manufacturing process of the DRAM according to the second embodiment in the order of steps;

FIG. 22 is a cross-sectional view showing an example of the manufacturing process of the DRAM according to the second embodiment in the order of steps;

FIG. 23 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the second embodiment in the order of steps;

FIG. 24 shows a DRA according to still another embodiment of the present invention.
It is sectional drawing which showed an example of the manufacturing process of M.

FIG. 25 is a cross-sectional view showing an example of a manufacturing step of the DRAM according to another embodiment of the present invention in the order of steps;

FIG. 26 is a sectional view illustrating an example of a manufacturing process of the DRAM of the fourth embodiment in the order of steps;

FIG. 27 is a cross sectional view showing an example of a manufacturing process of the DRAM of the fourth embodiment in the order of steps.

FIG. 28 is a sectional view illustrating an example of a manufacturing process of the DRAM of the fourth embodiment in the order of steps.

FIG. 29 shows a DRA according to still another embodiment of the present invention.
It is sectional drawing which showed an example of the manufacturing process of M.

FIG. 30 is a graph showing data obtained by experimenting the effect of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 1A semiconductor chip 5 groove (element isolation groove) 6 silicon oxide film 7 silicon oxide film 10 n-type semiconductor region 11 p-type well 12 n-type well 13 gate oxide film 14A gate electrode 14B gate electrode 14C gate electrode 15 silicon nitride Film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20 a sidewall spacer 22 p ⁺ type semiconductor region 23 n ⁺ type semiconductor region 24 SOG film 25, 26 silicon oxide film 28, 29 contact hole 30 plug 31 silicon oxide film 34, 36 contact hole 38 first layer wiring 40 silicon nitride film 42 TiSi ₂ layer 43 sidewall spacers 44 SOG film 45 and silicon oxide film 48 through hole 49 plug 50 silicon nitride film 5 Silicon oxide film 52 groove 53 metal compound film 54 insulating film 55 lower electrode 56 silicon nitride film 57 tantalum oxide film 58 polycrystalline tantalum oxide film 59 silicon oxynitride film 60 titanium nitride film 61 upper electrode 62 silicon oxide film 63 SOG film 64; 65 through hole 66 plug 67 second layer wiring 68 first tantalum oxide film 69 first polycrystalline tantalum oxide film 70 silicon oxynitride film 71 second tantalum oxide film 72, 73 silicon nitride film 74 metal silicide film A, B, C curve BL bit line C information storage capacitance element MARY memory array Qn n-channel MISFET Qp p-channel MISFET Qs MISFET for memory cell selection SA sense amplifier WD word driver WL word line

Claims (12)

[Claims] 1. A lower electrode made of a metal or a metal compound and formed in a hole of an insulating film so as to cover an inner surface thereof, an upper electrode disposed to face the lower electrode, and the upper electrode and the lower electrode. A semiconductor device including an information storage capacitive element including a capacitor insulating film formed therebetween, wherein the capacitor insulating film includes a polycrystalline tantalum oxide film, a metal and an oxygen diffusion preventing film, A semiconductor device, wherein the oxygen diffusion preventing film is formed between the lower electrode made of the metal or the metal compound and the polycrystalline tantalum oxide film. 2. The semiconductor device according to claim 1, wherein said metal and oxygen diffusion preventing films are silicon oxynitride films. 3. The semiconductor device according to claim 1, wherein the capacitor insulating film further includes a silicon nitride film, wherein the silicon nitride film includes the polycrystalline tantalum oxide film and the upper electrode. And a semiconductor device formed between the semiconductor device and the semiconductor device. 4. The semiconductor device according to claim 1, wherein said polycrystalline tantalum oxide film is composed of a plurality of layers. 5. The semiconductor device according to claim 1, wherein said lower electrode is made of any material selected from titanium nitride, tungsten, tungsten nitride or tantalum nitride, or a material selected from the group consisting of titanium nitride, tungsten, tungsten nitride, and tantalum nitride. A semiconductor device comprising a compound, wherein the upper electrode is made of titanium nitride. 6. The semiconductor device according to claim 1, wherein the lower electrode is formed in a hole of a first insulating film formed above a bit line of the DRAM. A height of the tip of the lower electrode is higher than an elevation of a surface of the first insulating film. 7. The semiconductor device according to claim 1, wherein said lower electrode is formed of a first insulating film and a second insulating film formed above a bit line of a DRAM. Formed in the hole,
The semiconductor device according to claim 1, wherein the elevation of the tip of the lower electrode is the same as the elevation of the surface of the second insulating film. 8. A semiconductor device comprising: a MISFET on a main surface of a semiconductor substrate; a bit line on a first insulating film covering the MISFET; and a capacitor for storing information formed on a second insulating film on the bit line. A method for manufacturing a semiconductor device, comprising: (a) forming a third insulating film on the second insulating film and forming a plurality of holes in the third insulating film; (b) forming an inner surface of the hole. Forming a covering metal film or a metal compound film on the entire surface of the semiconductor substrate; forming a fourth insulating film for filling the hole on the metal film or the metal compound film; Removing a film or a metal compound film; (c) removing the fourth insulating film in the hole to expose a lower electrode of the information storage capacitor formed of the metal film or the metal compound film; d) silicon over the entire surface of the semiconductor substrate (E) depositing an amorphous tantalum oxide film on the silicon nitride film; and (f) subjecting the amorphous tantalum oxide film to a heat treatment in an oxidizing atmosphere to form the amorphous tantalum oxide film. Forming a polycrystalline tantalum oxide film by crystallizing the polycrystalline tantalum oxide film; and (g) forming a metal film or a metal compound film on the polycrystalline tantalum oxide film. Production method. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a second polycrystalline tantalum oxide film after the step (f). Production method. 10. The method for manufacturing a semiconductor device according to claim 9, wherein heat treatment in an oxidizing atmosphere applied to said second polycrystalline tantalum oxide film is lower than heat treatment to said amorphous tantalum oxide film. A method for manufacturing a semiconductor device, which is performed at a temperature or in a short time. 11. The method for manufacturing a semiconductor device according to claim 8, wherein the polycrystalline tantalum oxide film or the second polycrystalline oxide is further added before the step (g). A method for manufacturing a semiconductor device, comprising a step of forming a silicon nitride film on a tantalum film. 12. The method of manufacturing a semiconductor device according to claim 8, wherein in the step (a), the third insulating film is etched more than the third insulating film. Slow or CMP
Forming a fifth insulating film having a low polishing rate by a polishing method, and in the step of removing the fourth insulating film and the metal film or the metal compound film in the step (b), etching the fifth insulating film by a CMP method; A method for manufacturing a semiconductor device, wherein the method is used as a polishing stopper film.