KR100418585B1 - Method for fabrication of ferroelectric random access memory - Google Patents
Method for fabrication of ferroelectric random access memory Download PDFInfo
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- KR100418585B1 KR100418585B1 KR10-2001-0038783A KR20010038783A KR100418585B1 KR 100418585 B1 KR100418585 B1 KR 100418585B1 KR 20010038783 A KR20010038783 A KR 20010038783A KR 100418585 B1 KR100418585 B1 KR 100418585B1
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 230000008569 process Effects 0.000 claims abstract description 20
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 115
- 239000010410 layer Substances 0.000 claims description 90
- 229910052697 platinum Inorganic materials 0.000 claims description 56
- 238000000151 deposition Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910019001 CoSi Inorganic materials 0.000 claims description 2
- 229910005881 NiSi 2 Inorganic materials 0.000 claims description 2
- 229910004491 TaAlN Inorganic materials 0.000 claims description 2
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 2
- 229910008482 TiSiN Inorganic materials 0.000 claims description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 150000003057 platinum Chemical class 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000010409 thin film Substances 0.000 abstract description 6
- 238000001039 wet etching Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000004070 electrodeposition Methods 0.000 abstract 2
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- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 230000009257 reactivity Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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Abstract
본 발명은 전기화학적 박막 성장방법(Electro-Chemical Deposition)을 이용하여 3차원 구조의 강유전체 캐패시터의 제조방법에 있어서, 전기화학적 박막 성장방법(Electro-Chemical Deposition)으로 하부전극을 형성하기 위하여 시드층에 전류를 공급하는 WNx층을 형성하고, 상기 WNx층은 후속공정에서 희생막의 습식식각에서 하부절연막과 플러그의 손상을 막는 유리한 효과가 있다.The present invention relates to a method of manufacturing a ferroelectric capacitor having a three-dimensional structure by using an electrochemical thin film growth method (Electro-Chemical Deposition), the electrochemical thin film growth method (Electro-Chemical Deposition) to form a lower electrode in the seed layer Forming a WN x layer for supplying a current, the WN x layer has an advantageous effect of preventing damage to the lower insulating layer and the plug in the wet etching of the sacrificial layer in a subsequent process.
Description
본 발명은 FeRAM(Ferroelectric Random Access Memory)의 캐패시터 제조방법에 관한 것으로 특히 캐패시터의 하부전극의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of a FeRAM (Ferroelectric Random Access Memory), and more particularly, to a method of manufacturing a lower electrode of a capacitor.
FeRAM은 강유전체(Ferroelectric Material)의 분극반전과 히스테리시스 (Hysteresis) 특성을 이용한 비휘발성(Nonvolatile) 기억소자의 일종으로서 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 DRAM과 같은 고속, 대용량, 저전력을 가질 수 있는 이상적인 메모리이다. FeRAM 소자의 강유전체 유전물질로는 SrBi2Ta2O9(이하 SBT라 한다), (SrxBi2-y(TaiNbj)2O9-Z)(이하 SBTN라 한다), Pb(ZrxTi1-X)O3(이하 PZT라 한다), SrTiO3(이하 ST라 한다), Bi4-xLaxTi3O12(이하 BLT라 한다), Bi4Ti3O12(이하 BIT라 한다)박막이 주로 사용된다.강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.FeRAM is a kind of nonvolatile memory device using polarization inversion and hysteresis of ferroelectric material. It is an ideal memory to have low power. Ferroelectric dielectric materials for FeRAM devices include SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT), (Sr x Bi 2-y (Ta i Nb j ) 2 O 9-Z ) (hereinafter referred to as SBTN), and Pb (Zr x Ti 1-X ) O 3 (hereinafter referred to as PZT), SrTiO 3 (hereinafter referred to as ST), Bi 4-x La x Ti 3 O 12 (hereinafter referred to as BLT), Bi 4 Ti 3 O 12 (hereinafter referred to as BIT A thin film is mainly used.A ferroelectric has a dielectric constant ranging from hundreds to thousands at room temperature, and has two stable remnant polarization states, so that the thin film is applied to a nonvolatile memory device. have. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .
FeRAM은 집적도가 향상될수록 잔류분극값의 향상이 요구된다. 잔류분극값의 향상에는 분극값이 높은 물질을 사용하는 방법이 있다. 또한 비록 잔류분극값은 작은 값을 가지지만 현재의 평판의 1차원 캐패시터 공정에서 스택 구조, 실린더 구조, 컨캐이브구조와 같은 3차원 구조를 가지면 전체 분극값의 증가를 가져올 수 있다. 하지만 3차원 구조를 형성하는 경우에는 다양한 기술상의 발전이 뒤따라야 한다. 즉, CVD(Chemical Vapor Deposition)공정과 같이 단차피복성(step coverage)이 우수한 증착방법의 성숙과 안정된 소오스(source)가 개발되어야 한다.As the degree of integration of FeRAM increases, the residual polarization value needs to be improved. In order to improve the residual polarization value, there is a method of using a material having a high polarization value. In addition, although the residual polarization value is small, in the current one-dimensional capacitor process, the three-dimensional structure such as stack structure, cylinder structure, and convex structure can increase the total polarization value. However, when forming a three-dimensional structure, various technological developments must be followed. That is, a mature and stable source of a deposition method with excellent step coverage, such as a chemical vapor deposition (CVD) process, should be developed.
현재 FeRAM의 캐패시터의 전극으로 일반적으로 사용하는 것은 백금(Pt)이다. 백금은 반응성이 낮고 고온 내성이 우수하다. 또한 자기배향성이 강하기 때문에 표면의 결정방위가 일치하여, 백금 상에서 배향성이 좋은 강유전체를 얻기 쉽다.At present, the commonly used electrode of the capacitor of FeRAM is platinum (Pt). Platinum has low reactivity and good high temperature resistance. In addition, since the self-orientation property is strong, the crystal orientations of the surfaces coincide, so that a ferroelectric having a good orientation on platinum is easily obtained.
백금 하부전극의 증착방법은 CVD법 등의 공정이 개발되고 있으나 성숙도는 극히 낮은 문제점이 있다. 따라서 현재 스택구조는 전기화학적 박막성장(Electro-Chemical Deposition; 이하 ECD법이라 한다)으로 스택구조를 형성하는 방법이 다양하게 연구되고 있다. ECD법은 하부전극 도전층이 시드층 도체 상에만 석출되고, 부도체상에서는 석출되지 않는다는 선택적 성장의 특징을 이용하여 백금 하부전극을 스택 구조로 성장시킨다.하부전극에 전류를 공급하는 시드층은 종래에는 백금으로 사용하였다. 이는 후속 공정에서 제거하여 캐패시터 간에 분리시켜야 하는데, 백금 식각시에 발생된 백금 잔유물이 백금 하부전극 스택이나 다른 곳에 부착하여 전기적 특성을 열화시키는 문제점이 있었다.As a method of depositing a platinum lower electrode, a process such as CVD is being developed, but there is a problem in that maturity is extremely low. Therefore, the current stack structure has been studied a variety of ways to form a stack structure by the electro-chemical thin film deposition (ECD method). The ECD method grows a platinum lower electrode in a stack structure by utilizing the characteristic of selective growth that the lower electrode conductive layer is deposited only on the seed layer conductor, and not on the non-conductor. The seed layer for supplying current to the lower electrode is conventionally Used as platinum. This is to be removed in a subsequent process to be separated between the capacitors, there is a problem that the platinum residue generated during platinum etching adheres to the platinum lower electrode stack or elsewhere to deteriorate the electrical characteristics.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 전기화학적 박막 성장방법을 이용하여 3차원 구조의 강유전체 캐패시터를 형성할 때, 시드층의 식각이 어려움이 없는 강유전체 메모리 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, when forming a ferroelectric capacitor having a three-dimensional structure by using an electrochemical thin film growth method, a method of manufacturing a capacitor of a ferroelectric memory device is difficult to etch the seed layer. The purpose is to provide.
도 1은 본 발명에 따른 폴리실리콘 형성 단면도,1 is a cross-sectional view of polysilicon forming according to the present invention,
도 2은 본 발명에 따른 리세스된 폴리실리콘 형성 단면도,2 is a cross-sectional view of forming a recessed polysilicon according to the present invention;
도 3는 본 발명에 따른 실리사이드와 베리어메탈 형성 단면도,3 is a cross-sectional view of the silicide and barrier metal formation according to the present invention;
도 4는 본 발명에 따른 WNx층 형성 단면도,4 is a cross-sectional view of forming a WN x layer according to the present invention;
도 5는 본 발명에 따른 고립된 백금 시드층 형성 단면도,5 is a cross-sectional view of an isolated platinum seed layer forming according to the present invention;
도 6는 본 발명에 따른 희생막 패턴 형성 단면도,6 is a cross-sectional view of forming a sacrificial film pattern according to the present invention,
도 7은 본 발명에 따른 Pt 하부전극 형성 단면도,7 is a cross-sectional view of forming a Pt lower electrode according to the present invention;
도 8은 본 발명에 따른 Pt 하부전극 스택 형성 단면도,8 is a cross-sectional view of forming a Pt lower electrode stack according to the present invention;
도 9는 본 발명에 따른 WNx층 식각 단면도,9 is a sectional view of the WN x layer etching according to the present invention,
도 10은 본 발명에 따른 유전체막 및 상부전극 형성 단면도.10 is a cross-sectional view of the dielectric film and the upper electrode formed according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
100 : 반도체기판 160 : WNx층100: semiconductor substrate 160: WN x layer
165 : 백금시드층 패턴 175 : 백금 하부전극165: platinum seed layer pattern 175: platinum lower electrode
180 : 유전체막 185 : 상부전극 도전층180: dielectric film 185: upper electrode conductive layer
상기 목적을 달성하기 위한 본 발명은, 반도체기판 상에 층간절연막을 형성하고, 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 내부를 폴리실리콘으로 증착한 후 에치백 공정에 의해 상기 콘택홀 내에 리세스된 폴리실리콘 플러그를 형성하는 단계; 상기 리세스된 폴리실리콘 플러그 상부를 금속 실리사이드 및 베리어메탈로 메워서 도전성 플러그를 형성한 후 평탄화하는 단계; 상기 도전성 플러그를 포함하는 상기 층간절연막 상에 WNx층을 증착하는 단계; 상기 도전성 플러그에 대응되는 영역의 상기 WNx층 상에 백금시드층을 증착하는 단계; 상기 백금시드층을 선택적으로 식각하여 백금시드층 패턴을 형성하는 단계; 상기 백금시드층 패턴을 포함한 WNx층 상에 희생막을 형성하는 단계; 상기 희생막을 선택적으로 식각하여 캐패시터의 하부전극이 형성될 백금시드층 패턴을 오픈시키는 단계; 상기 오픈된 백금시드층 패턴 상에 ECD법으로 백금 하부전극을 형성하는 단계; 상기 희생막을 제거하여 하부전극 스택을 형성하는 단계; 에치백 공정을 통해 상기 WNx층을 식각하여 WNx층 패턴을 형성하는 단계; 및 상기 하부전극 상에 캐패시터의 유전체막과 상부전극을 차례로 형성하는 단계를 포함하는 강유전체 메모리 소자의 캐패시터 제조방법을 제공한다.The present invention for achieving the above object, the step of forming an interlayer insulating film on the semiconductor substrate, and selectively etching to form a contact hole; Depositing the inside of the contact hole with polysilicon and forming a recessed polysilicon plug in the contact hole by an etch back process; Filling the recessed polysilicon plug top with metal silicide and barrier metal to form a conductive plug and then flattening it; Depositing a WN x layer on the interlayer insulating film including the conductive plug; Depositing a platinum seed layer on the WN x layer in a region corresponding to the conductive plug; Selectively etching the platinum seed layer to form a platinum seed layer pattern; Forming a sacrificial layer on the WN x layer including the platinum seed layer pattern; Selectively etching the sacrificial layer to open a platinum seed layer pattern on which a lower electrode of the capacitor is to be formed; Forming a platinum lower electrode on the open platinum seed layer pattern by ECD; Removing the sacrificial layer to form a lower electrode stack; Etching the WN x layer through an etch back process to form a WN x layer pattern; And forming a dielectric film of the capacitor and an upper electrode in sequence on the lower electrode.
본 발명의 하부전극은 ECD법으로 형성한 백금(Pt)막이다. ECD법에서는 백금이 시드층 도체상에만 석출되고, 부도체상에서는 석출되지 않는다는 선택적 성장의 특징을 가지므로 스토리지노드 콘택홀 안에서 백금이 성장한다. 따라서 전기적 특성과 단차피복성이 우수한 스택 구조의 하부전극을 형성할 수 있다.The lower electrode of the present invention is a platinum (Pt) film formed by the ECD method. In the ECD method, platinum is grown in the storage node contact hole because the platinum is deposited only on the seed layer conductor and not on the insulator. Therefore, the lower electrode of the stack structure having excellent electrical characteristics and step coverage can be formed.
본 발명은 평탄화된 층간절연막 상에 WNx층을 형성한다. WNx층은 후속 공정에서 희생막를 습식식각에 의하여 제거하는 과정에서 습식 용액이 하부절연막과 플러그로의 확산을 억제한다. 또한 ECD법으로 백금을 형성하기 위한 백금시드층으로 전류를 공급하는 역할을 한다.The present invention forms a WN x layer on the planarized interlayer insulating film. The WN x layer inhibits diffusion of the wet solution into the lower insulating layer and the plug in the process of removing the sacrificial layer by wet etching in a subsequent process. In addition, the ECD method serves to supply current to the platinum seed layer for forming platinum.
본 발명은 백금 하부전극이 성장하는 백금 시드층은 백금 하부전극 스택이 성장하기 전에 분리되므로, 종래 ECD법과 같은 백금 시드층 식각에 의한 백금 잔유물이 하부전극 스택에 부착되어 전기적 특성이 열화되는 현상이 없게된다.According to the present invention, since the platinum seed layer in which the platinum lower electrode is grown is separated before the platinum lower electrode stack is grown, a phenomenon that the platinum residues are attached to the lower electrode stack by the platinum seed layer etching as in the conventional ECD method is deteriorated in electrical characteristics. There will be no.
상술한 목적, 특징들 및 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일실시예를 상세히 설명한다.The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 폴리실리콘 형성한 후의 단면도이다.1 is a cross-sectional view after forming polysilicon according to the present invention.
반도체기판(100)의 소정영역에 활성영역 및 비활성영역을 한정하는 소자분리막(105)을 형성한다. 소자분리막(105)들 사이에 게이트절연막(110), 게이트전극(115), 스페이서(120) 및 소오스/드레인 영역(도시되어 있지 않음)으로 구성되는 모스 트랜지스터를 형성한다. 상기 모스 트랜지스터가 형성된 반도체기판(100) 전면에 제1 층간절연막(125)을 형성하고, 제1 층간절연막(125)을 패터닝하여 모스 트랜지스터의 드레인 영역을 노출시키는 비트라인 콘택홀을 형성한다.이어서, 비트라인 콘택홀을 덮고 드레인 영역과 전기적으로 연결되는 비트라인(130)을 형성한다. 비트라인(130)이 형성된 반도체기판(100) 전면에 제2 층간절연막(135)을 형성한다. 제1 및 제2 층간절연막(125, 135)으로 이루어진 층간절연막(140)을 선택적으로 식각하여 모스 트랜지스터의 소오스 영역을 노출시키는 콘택홀(도시하지 않음)을 형성한다. 콘택홀이 형성된 반도체기판(100) 전면에 콘택홀을 충분히 채우는 폴리실리콘(145)을 증착한다.An isolation layer 105 is formed in a predetermined region of the semiconductor substrate 100 to define an active region and an inactive region. A MOS transistor including a gate insulating film 110, a gate electrode 115, a spacer 120, and a source / drain region (not shown) is formed between the device isolation layers 105. A first interlayer insulating layer 125 is formed on the entire surface of the semiconductor substrate 100 on which the MOS transistor is formed, and the first interlayer insulating layer 125 is patterned to form a bit line contact hole exposing a drain region of the MOS transistor. The bit line 130 may be formed to cover the bit line contact hole and be electrically connected to the drain region. A second interlayer insulating layer 135 is formed on the entire surface of the semiconductor substrate 100 on which the bit lines 130 are formed. The interlayer insulating layer 140 formed of the first and second interlayer insulating layers 125 and 135 is selectively etched to form a contact hole (not shown) that exposes a source region of the MOS transistor. Polysilicon 145 is deposited on the entire surface of the semiconductor substrate 100 on which the contact holes are formed.
도 2은 본 발명에 따른 폴리실리콘(145)을 리세스(Recess) 시켜 리세스된 폴리실리콘 플러그(145a)를 형성한 후의 단면도이다.2 is a cross-sectional view of a recessed polysilicon 145 according to the present invention to form a recessed polysilicon plug 145a.
폴리실리콘(145)을 에치백(Etch back)하여 층간절연막(140)의 표면을 노출시킨다. 이 때 에치백은 폴리실리콘(145)이 과도식각되도록 실시하여 폴리실리콘이 플러그 내부에만 잔류한다. 따라서, 폴리실리콘은 콘택홀을 완전히 충전시키지 못하고 상부에 여유공간을 갖도록 리세스(Recess) 된다.The surface of the interlayer insulating layer 140 is exposed by etching back the polysilicon 145. At this time, the etch back is made so that the polysilicon 145 is excessively etched so that the polysilicon remains only inside the plug. Therefore, the polysilicon is recessed to have a free space thereon without filling the contact hole completely.
도 3은 본 발명에 따른 리세스된 폴리실리콘 플러그(145a) 상부를 금속 실리사이드(150)와 베리어메탈(155)로 채워서 도전성 플러그를 형성한 후의 단면도이다.3 is a cross-sectional view of a recessed polysilicon plug 145a formed with a metal silicide 150 and a barrier metal 155 to form a conductive plug.
폴리실리콘을 리세스 시킨 후 클리닝(Cleaning) 공정을 실시한 후 전면적으로 Ti, Co, 및 Ni로 구성된 금속물질 중에서 하나를 증착하며, 증착방법으로는 CVD법을 이용한다. 증착 후 급속열처리(RTP, Rapid Thermal Processing) 또는 로(Furnace)를 이용한 열처리를 실시한다. 열처리에 의하여 층간절연막(140) 상에 있는 금속물질 중의 하나는 실리사이드 반응을 일으키지 않으나, 폴리실리콘 상에 있는 금속물질 중의 하나는 실리콘과 실리사이드 반응을 하여 TiSi2, CoSi2, NiSi2등의 금속 실리사이드(150)를 형성한다.열처리가 완료된 반도체기판에 황산(H2SO4)과 과수(H2O2)가 혼합된 용액으로 세정 공정을 진행함으로써 층간절연막(140) 상에 실리사이드화 반응을 일으키지 않았던 금속물질을 제거한다. 이 금속 실리사이드(150)은 폴리실리콘과 오믹콘택(Ohmic Contact)을 형성하여 접촉저항을 감소시키는 역할을 한다.After the polysilicon is recessed, a cleaning process is performed, and then one of the metal materials including Ti, Co, and Ni is deposited on the entire surface. The CVD method is used as the deposition method. After deposition, heat treatment is performed using Rapid Thermal Processing (RTP) or Furnace. By heat treatment, one of the metal materials on the interlayer insulating layer 140 does not cause a silicide reaction, but one of the metal materials on the polysilicon reacts with silicon by silicide reaction such as TiSi 2 , CoSi 2 , NiSi 2, or the like. And forming a silicide reaction on the interlayer insulating layer 140 by performing a cleaning process with a solution of sulfuric acid (H 2 SO 4 ) and fruit water (H 2 O 2 ) mixed on the heat-treated semiconductor substrate. Remove any metal that was not used. The metal silicide 150 forms ohmic contact with polysilicon to reduce contact resistance.
그 다음 베리어메탈(155)을 기판전면에 증착한 후 화학 기계적 연마(Chemical Mechanical Polishing,이하 CMP) 공정을 통해 평탄화시킨다. 이 베리어메탈(155)은 유전체 결정화를 위해서 산소 분위기에서 고온의 열처리시, 산소가 스토리지 전극을 통해서 확산해 들어가서, 폴리실리콘 플러그와 스토리지 전극의 계면에서 폴리실리콘의 산화를 방지하는 기능을 한다. 베리어메탈은 TiN, TaN, TiSiN, TaSiN, TaAlN 및 이를 조합한 물질 중에서 선택된 하나로 형성하며, PVD(Physical Vapor Deposition) 또는 CVD법에 의해 증착시킨다.Then, the barrier metal 155 is deposited on the entire surface of the substrate and then planarized through a chemical mechanical polishing (CMP) process. The barrier metal 155 serves to prevent oxidation of the polysilicon at the interface between the polysilicon plug and the storage electrode when oxygen is diffused through the storage electrode during a high temperature heat treatment in an oxygen atmosphere for dielectric crystallization. The barrier metal is formed of one selected from TiN, TaN, TiSiN, TaSiN, TaAlN, and a combination thereof, and deposited by PVD (Physical Vapor Deposition) or CVD.
도 4는 본 발명에 따른 WNx층(160)을 형성한 후의 단면도이다.4 is a cross-sectional view after forming the WN x layer 160 in accordance with the present invention.
상기 도전성 플러그를 형성한 후에는 기판 전면에 WNx층을 형성한다. WNx층(160)은 후속 공정에서 희생막을 습식식각에 의하여 제거하는 과정에서 습식 용액이 하부절연막과 플러그로의 확산을 억제한다. 또한, ECD법으로 백금을 형성하기 위한 백금시드층으로 전류를 공급하는 역할을 한다.After forming the conductive plug, a WN x layer is formed on the entire surface of the substrate. The WN x layer 160 suppresses diffusion of the wet solution into the lower insulating layer and the plug in the process of removing the sacrificial layer by wet etching in a subsequent process. In addition, it serves to supply current to the platinum seed layer for forming platinum by the ECD method.
WNx층의 증착방법은 CVD법, PVD법, ALD(Atomic Layer Deposition)법 중에서 선택된 방법을 사용하며, 두께는 100Å ∼ 5000Å의 범위를 가진다.The deposition method of the WN x layer uses a method selected from the CVD method, PVD method, ALD (Atomic Layer Deposition) method, the thickness is in the range of 100 ~ 5000Å.
도 5는 본 발명에 따른 고립된 백금시드층 패턴(165)이 형성된 단면도이다.5 is a cross-sectional view of an isolated platinum seed layer pattern 165 according to the present invention.
WNx층(160) 상에 순수한 백금시드층을 형성하고, 마스크 작업과 선택적 식각공정을 통해 고립된 백금시드층 패턴(165)을 형성한다. 백금시드층의 증착방법은 스퍼터링(Sputtering) 방식을 사용하며, 백금시드층이 100Å ∼ 5000Å의 두께가 되도록 한다.A pure platinum seed layer is formed on the WN x layer 160, and an isolated platinum seed layer pattern 165 is formed through a mask operation and a selective etching process. The deposition method of the platinum seed layer uses a sputtering method, so that the platinum seed layer has a thickness of 100 kPa to 5000 kPa.
도 6는 본 발명에 따른 희생막 패턴(170)이 형성된 단면도이다.6 is a cross-sectional view of the sacrificial layer pattern 170 according to the present invention.
백금 시드층 패턴(170)을 포함한 WNx층(160) 상에 희생막을 형성한다.A sacrificial layer is formed on the WN x layer 160 including the platinum seed layer pattern 170.
희생막은 PE-TEOS(Plasma Enhanced TEOS), USG(Undoped-Silicate Glass), PSG(Phospho-Silicate Glass), BPSG(Boro-Phospho-Silicate Glass), HDP(High Density Plasma) 산화막 중에서 선택된 어느 하나 또는 이들의 조합으로 형성할 수 있다.The sacrificial film is any one selected from Plasma Enhanced TEOS (PE-TEOS), Undoped-Silicate Glass (USG), Phospho-Silicate Glass (PSG), Boro-Phospho-Silicate Glass (BPSG), or High Density Plasma (HDP) oxide film. It can be formed by a combination of.
다음으로 희생막을 선택적으로 식각하여 스토리지노드 콘택홀과 희생막 패턴(170)을 형성한다.Next, the sacrificial layer is selectively etched to form the storage node contact hole and the sacrificial layer pattern 170.
도 7은 본 발명에 따른 ECD법을 이용하여 백금 하부전극(175)이 형성된 단면도이다.7 is a cross-sectional view of the platinum lower electrode 175 formed using the ECD method according to the present invention.
하부전극(175) 증착시 사용되는 전력은 DC, 펄스(pulse) 또는 펄스리버스(Pulse reverse) 중에서 선택된 하나를 이용하며, 증착시 사용되는 전류밀도(Current density)는 0.1mA/cm2∼ 10mA/cm2의 범위로 한다. 하부전극(175)은 500Å ∼ 5000Å의 높이가 되도록 한다. 증착시 상온 ∼ 100℃의 범위로 증착온도를 조절하며, 증착 도금조의 수소이온농도(pH)는 9 ∼ 14의 범위를 가지도록 한다. 증착시 사용되는 백금염은 K, Pt, OH의 혼합물을 사용한다.The power used to deposit the lower electrode 175 is selected from one of DC, pulse or pulse reverse, and the current density used during deposition is 0.1 mA / cm 2 to 10 mA /. The range is cm 2 . The lower electrode 175 is set to have a height of 500 mV to 5000 mV. During deposition, the deposition temperature is controlled in the range of room temperature to 100 ° C, and the hydrogen ion concentration (pH) of the deposition plating bath is in the range of 9-14. The platinum salt used in the deposition uses a mixture of K, Pt and OH.
하부전극의 높이는 희생막 패턴(170)의 높이보다 낮게 제어된다.The height of the lower electrode is controlled to be lower than the height of the sacrificial layer pattern 170.
도 8은 본 발명에 따른 백금 하부전극 스택(175a)이 형성된 단면도이다.8 is a cross-sectional view of the platinum lower electrode stack 175a according to the present invention.
희생막 패턴(170)을 습식식각하여 백금 하부전극 스택(175a)을 형성한다. 습식식각시에는 BOE(Buffered Oxide Etchant), HF의 복합물을 사용한다.The sacrificial layer pattern 170 is wet-etched to form the platinum lower electrode stack 175a. Wet etching uses a combination of BOE (Buffered Oxide Etchant) and HF.
도 9는 본 발명에 따른 WNx층을 식각하여 WNx층 패턴(160a)이 형성된 단면도이다.Figure 9 is a cross-section formed with a WN x layer pattern (160a) by etching the WN x layer in accordance with the present invention.
WNx층의 식각은 에치백 공정을 이용하며, 이를 통해 각 캐패시터를 서로 고립시킨다.The etching of the WN x layer uses an etch back process, which isolates each capacitor from each other.
도 10은 본 발명에 따른 유전체막(180) 및 상부전극 도전층(185)을 증착하고 패터닝한 단면도이다.10 is a cross-sectional view of depositing and patterning the dielectric film 180 and the upper electrode conductive layer 185 according to the present invention.
유전체막으로는 SBT, SBTN, PZT, ST, BLT, BIT 중에서 선택된 유전물질을 사용하며, 증착방법으로는 CVD법, ALD법 등을 사용한다.As the dielectric film, a dielectric material selected from SBT, SBTN, PZT, ST, BLT, and BIT is used. As the deposition method, a CVD method or an ALD method is used.
상부전극은 Pt, Ir, Ru, IrOx, RuOx, W, WNx, TiN 중에서 선택된 물질을 사용한다.The upper electrode uses a material selected from Pt, Ir, Ru, IrO x , RuO x , W, WN x and TiN.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어진 본 발명은, FeRAM의 캐패시터를 제조하는 과정에서 캐패시터의 하부전극을 전기적 특성이 우수하고, 단차피복성이 우수한 스택 구조로 형성할 수 있는 효과가 있다.The present invention made as described above, the lower electrode of the capacitor in the process of manufacturing the capacitor of the FeRAM has an effect that can be formed into a stack structure excellent in electrical characteristics, excellent step coverage.
또한 ECD법으로 하부전극을 형성하기 위하여 시드층에 전류를 공급하는 WNx층을 형성하고, 상기 WNx층은 후속공정에서 희생막의 습식식각에서 하지층의 손상을 막는 유리한 효과가 있다.In addition, the WN x layer for supplying a current to the seed layer to form a lower electrode by the ECD method is formed, the WN x layer has an advantageous effect of preventing damage to the underlying layer in the wet etching of the sacrificial film in a subsequent process.
또한 백금 하부전극이 성장하는 백금시드층은 백금 하부전극 스택이 성장하기 전에 분리되므로, 종래 ECD법과 같은 백금시드층 식각에 의한 백금 잔유물이 하부전극 스택에 부착되어 전기적 특성이 열화되는 현상이 없게된다.In addition, since the platinum seed layer on which the platinum lower electrode grows is separated before the platinum lower electrode stack grows, platinum residues are deposited on the lower electrode stack due to the platinum seed layer etching as in the conventional ECD method, so that electrical characteristics are not degraded. .
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| KR20000001040A (en) * | 1998-06-08 | 2000-01-15 | 윤종용 | Capacitor with electrode formed by electroplating and its manufacturing method |
| KR20000026003A (en) * | 1998-10-16 | 2000-05-06 | 윤종용 | Capacitor of semiconductor device and method for making the same |
| KR20000066883A (en) * | 1999-04-21 | 2000-11-15 | 윤종용 | Method for manufacturing self-aligned stack capacitor using electroplating method |
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| KR20000001040A (en) * | 1998-06-08 | 2000-01-15 | 윤종용 | Capacitor with electrode formed by electroplating and its manufacturing method |
| KR20000026003A (en) * | 1998-10-16 | 2000-05-06 | 윤종용 | Capacitor of semiconductor device and method for making the same |
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