KR100470159B1 - Ferroelectric Random Access Memory having Iridium plug and method for fabricating the same - Google Patents

Abstract

The present invention provides a ferroelectric memory device and a method for manufacturing the same, which are suitable for preventing the plug from being oxidized even when the thermal process is performed in a high temperature oxygen atmosphere. An iridium plug penetrating the interlayer insulating film and connected to the semiconductor substrate, a lower electrode on the iridium plug, an iridium silicide film inserted between the semiconductor substrate and the iridium plug, and an iridium inserted between the iridium plug and the lower electrode. An oxide film, an insulating insulating film surrounding the lower electrode and exposing the surface of the lower electrode, a ferroelectric film on the lower electrode and the insulating film, and an upper electrode on the ferroelectric film.

Description

Ferroelectric memory device having an iridium plug and a method of manufacturing the same {Ferroelectric Random Access Memory having Iridium plug and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a nonvolatile memory device.

In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. A ferroelectric random access memory (FeRAM) device using such a ferroelectric thin film is a kind of nonvolatile memory device, which not only stores stored information even when power is cut off, but also operates at a speed of DRAM. It is comparable to the next generation memory device.

1 is a device cross-sectional view showing a ferroelectric memory device according to the prior art.

Referring to FIG. 1, an isolation layer 12 for isolation between devices is formed on a semiconductor substrate 11, and a gate oxide layer 13 and a word line 14 are formed on an active region of the semiconductor substrate 11. Source / drain 15a and 15b of the transistor are formed in the active region of the semiconductor substrate 11 on both sides of the word line 14.

A first interlayer insulating film ILD 16a is formed on the semiconductor substrate 11, and the tungsten plug 17 penetrates through the first interlayer insulating film 16a to the bit line contact hole reaching the source / drain 15a on one side. ) Is embedded, and the bit line 18 is connected to the tungsten plug 17.

As such, the storage node contact is formed by covering the second interlayer insulating film 16b over the semiconductor substrate 11 on which the transistor and the bit line are formed, and simultaneously penetrating the second interlayer insulating film 16b and the first interlayer insulating film 16a. TiN / Ti 19 and tungsten plug 20 are partially embedded in the hole, and TiN 21 is embedded in the rest of the contact hole.

A lower electrode 23 made of a platinum film is connected to the TiN 21, and a ferroelectric film 24 and an upper electrode 25 are formed on the lower electrode 23. Meanwhile, in order to increase the adhesion between the lower electrode 23 and the second interlayer insulating film 16b, an alumina 22 as an adhesive layer is inserted.

In the prior art as shown in FIG. 1, the storage node contact plug tungsten plug 20 and the lower electrode 23 are oxidized by a subsequent thermal process such as crystallization annealing of the ferroelectric film 24 to deteriorate thermal stability characteristics. This limits the integration of devices and the improvement of contact resistance.

In particular, the ferroelectric film 24 has a high thermal stability characteristic of the tungsten plug 20 due to the poor thermal stability of the tungsten plug 20 despite the advantage that the crystallization annealing at a high temperature causes the polarization value to increase rapidly due to the enlargement of grain boundaries and the increase of domains. Use of temperature above ℃ is limited.

Such poor thermal stability of the tungsten plug 20 includes titanium (Ti), titanium silicide (Ti-silicide), titanium nitride (TiN), and tungsten, which form ohmic contacts between the metal lower electrode and the semiconductor substrate. (W) and the like are caused by a phenomenon in which the thin film rapidly expands and swells as the volume increases or the element becomes vapor in a high temperature oxygen atmosphere.

This problem also occurs when a polysilicon plug is used as the storage node contact plug.

The present invention has been made to solve the above problems of the prior art, and provides a ferroelectric memory device suitable for preventing the storage node contact plug from being oxidized even if the thermal process is performed in a high temperature oxygen atmosphere and its manufacturing method There is this.

1 is a device cross-sectional view showing a ferroelectric memory device according to the prior art;

2 is a cross-sectional view illustrating a ferroelectric memory device according to an embodiment of the present invention;

3A to 3G are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device shown in FIG.

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: device isolation film

33: gate oxide film 34: word line

35a, 35b: source / drain regions 36: first interlayer insulating film

37: bit line contact 38: bit line

39: second interlayer insulating film 40a: iridium plug

41: iridium silicide film 42a: alumina

43: iridium oxide film 44: lower electrode

45a: third interlayer insulating film 46: ferroelectric film

47: upper electrode

In the ferroelectric memory device of the present invention for achieving the above object, the ferroelectric memory device including a lower electrode connected to the semiconductor substrate via a storage node contact plug, characterized in that the storage node contact plug is an iridium plug, The ferroelectric memory device of the present invention includes a semiconductor substrate, an interlayer insulating film on the semiconductor substrate, an iridium plug connected to the semiconductor substrate through the interlayer insulating film, a lower electrode on the iridium plug, and inserted between the semiconductor substrate and the iridium plug. An iridium silicide film, an iridium oxide film interposed between the iridium plug and the lower electrode, an insulating insulating film surrounding the lower electrode and exposing the surface of the lower electrode, a ferroelectric film on the lower electrode and the insulating film, and on the ferroelectric film Upper war A it characterized in that it comprises.

The method of manufacturing a ferroelectric memory device of the present invention may include forming an interlayer insulating film on a semiconductor substrate, forming a contact hole for exposing the semiconductor substrate by etching the interlayer insulating film, until the contact hole is filled. Forming an iridium film on the interlayer insulating film, forming an iridium silicide film at an interface between the semiconductor substrate and the iridium film exposed inside the contact hole, and removing an iridium film on the interlayer insulating film to form an iridium plug in the contact hole. Forming an adhesive layer on the iridium plug and the interlayer insulating film, etching the adhesive layer to expose the surface of the iridium plug, forming an iridium oxide film on the exposed iridium plug, and the iridium oxide film and A lower electrode, a ferroelectric film, and a phase on the adhesive layer And forming a capacitor comprising an electrode, wherein the forming of the capacitor comprises: forming a lower electrode conductive film on the iridium oxide film and the adhesive layer, and forming the lower electrode conductive film and the adhesive layer. Simultaneously patterning to form a lower electrode, forming an insulating insulating film surrounding the lower electrode and exposing the surface of the lower electrode, forming a ferroelectric film on the lower electrode and the insulating insulating film, on the ferroelectric film Forming an upper electrode conductive film on the upper electrode, and etching the upper electrode conductive film to form an upper electrode.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a cross-sectional view illustrating a ferroelectric memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a first interlayer insulating film 36 and a second interlayer insulating film 39 are formed on the semiconductor substrate 31 on which the device isolation film 32 is formed, and the second interlayer insulating film 39 is formed as an interlayer insulating material. An iridium silicide film 41 and an iridium plug 40a are buried in the storage node contact hole that simultaneously passes through the first interlayer insulating film 36, and the lower electrode 44, the ferroelectric film 46, and the iridium plug 40a are buried. The ferroelectric capacitor consisting of the upper electrode 47 is connected.

An alumina 42a having an opening for opening the iridium plug 40a is inserted to increase adhesion between the lower electrode 44 and the second interlayer insulating film 39, and the iridium plug opened in the opening of the alumina 42a. An iridium oxide film 43 is provided on the 40a. The lower electrode 44 and the alumina 42a are insulated from the neighboring structure by the third interlayer insulating film 45a.

Meanwhile, a gate oxide film 33 and a word line 34 are formed on the semiconductor substrate 31, and source / drain regions 35a and 35b are formed in the semiconductor substrate 31, and the first interlayer insulating layer 36 is formed. The bit line contact 37 and the bit line 38 are connected to one source / drain region 35a through the through hole.

In FIG. 2, in order to improve the stability of the plug, the plug is formed using iridium having excellent thermal stability without forming the plug with general Ti, TiN, Ti-silicide, W, and the like, and the semiconductor substrate 31 and the iridium plug ( An iridium silicide film 41 is formed at the interface of 40a to form an ohmic contact. The iridium film has excellent oxygen barrier properties at high temperatures and does not oxidize even when annealing is performed in an oxygen atmosphere of ˜750 ° C.

3A to 3G are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device shown in FIG. 2.

As shown in FIG. 3A, an isolation region 32 is formed on the semiconductor substrate 31 to define an active region, thereby defining an active region, and forming a gate oxide layer 33 and a word on the active region of the semiconductor substrate 31. Lines 34 are formed in sequence.

Next, impurities are implanted into the semiconductor substrate 31 on both sides of the word line 34 to form source / drain regions 35a and 35b of the transistor.

Although not shown in the drawing, as is well known, spacers may be formed on both sidewalls of the word line 34, thereby forming a source / drain region having a lightly doped drain (LDD) structure. That is, the LDD region is formed by ion implanting low concentration impurities using the word line 34 as a mask, and then spacers are formed on both side walls of the word line 34, and the high concentration impurities are formed using the word line 34 and the spacer as a mask. Ion implantation forms a source / drain region in contact with the LDD region.

Next, after depositing and planarizing the first interlayer insulating layer 36 on the semiconductor substrate 31 on which the transistor is formed, the first interlayer insulating layer 36 is etched with a contact mask (not shown) to etch one side source / drain region ( A bit line contact hole exposing 35a) is formed, and a bit line contact 37 embedded in the bit line contact hole is formed. Here, the bit line contact 37 may be a tungsten plug (W-plug) formed by depositing tungsten (W) and then etch back or chemical mechanical polishing (CMP).

Next, a bit line conductive film is deposited on the entire surface, and then patterned to form a bit line 38 connected to the bit line contact 37, and a second interlayer insulating layer 39 is formed on the entire surface including the bit line 38. After deposition it is planarized.

Next, the second interlayer insulating layer 39 and the first interlayer insulating layer 36 are simultaneously etched with a storage node contact mask (not shown) to form a storage node contact hole exposing the other source / drain region 35b.

Next, an iridium film 40 is deposited on the second interlayer insulating film 39 including the storage node contact hole. In this case, the iridium film 40 is deposited by using a deposition method such as metal organic deposition (MOD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) or plasma enhanced ALD (PEALD), and the thickness thereof is 100 kV. It is-10000 microseconds.

As shown in FIG. 3B, heat treatment is performed to induce a reaction between the iridium film and the silicon in the source / drain regions to form the iridium silicide film 41 to a thickness of 10 kV to 1000 kPa. At this time, the heat treatment for forming the iridium silicide film 41 uses rapid thermal annealing or furnace annealing. For example, rapid heat treatment (RTA) or royal heat treatment (FA) is performed at a temperature of 500 ° C. to 1000 ° C. in a reducing gas atmosphere selected from a mixture of Ar, N ₂ , He, Ne, Xe, and N ₂ / Ar.

As illustrated in FIG. 3C, chemical mechanical polishing or etch back of the iridium film 40 is performed to form an iridium plug 40a having a flat surface while being embedded in the storage node contact hole. At this time, the iridium film 40 on the second interlayer insulating film 39 is removed.

As shown in FIG. 3D, an alumina (Al ₂ O ₃ , 42), which is an adhesion layer, is deposited on the second interlayer insulating film 39 including the iridium plug 40a to a thickness of 5 μs to 500 μs. A portion of the alumina 42 is etched using an open mask (not shown) as an etch mask to expose the surface of the iridium plug 40a.

At this time, the etching of the alumina 42 uses a dry etching or a wet etching using a wet chemical, as a wet chemical is used HF, BOE, NH ₃ F, NH ₄ OH.

Next, the exposed surface of the iridium plug 40a is oxidized through rapid thermal treatment (RTA) to form an iridium oxide film 43 on the iridium plug 40a. At this time, the iridium oxide film 43 is formed to a thickness not to deviate from the alumina 42, in order to provide a flat lower structure before forming the lower electrode. For example, the iridium oxide film 43 is formed to have a thickness of 10 kV to 1000 kV.

As shown in FIG. 3E, after the lower electrode conductive film is deposited on the alumina 42 including the iridium oxide film 43, the lower electrode 44 is formed by simultaneously patterning the conductive film and the alumina 42. At this time, the alumina 42 is patterned in the same shape as the lower electrode 44 and remains as the alumina 42a between the lower electrode 44 and the second interlayer insulating film 39.

Next, the third interlayer insulating film 45 is formed on the second interlayer insulating film 39 including the lower electrode 44 until the space between the adjacent lower electrodes 44 is filled. At this time, the third interlayer insulating film 45 is one selected from HDP (High Density Plasma) oxide film, BPSG, BSG or PSG, and is formed to have a thickness of 1000 kPa to 10,000 kPa.

As shown in FIG. 3F, the third interlayer insulating layer 45 is planarized through chemical mechanical polishing (CMP) until the surface of the lower electrode 44 is exposed. At this time, the third interlayer insulating film 45a remaining after chemical mechanical polishing is called an isolation dielectric because it has a form surrounding the lower electrodes 44 while insulating the adjacent lower electrodes 44 from each other.

As described above, the lower electrode 44 is formed in the form of being surrounded by the third interlayer insulating film 45a, so that the burden of the mask work due to the step difference of the capacitor, difficulty in planarization, and short-circuit between the upper and lower electrodes can be prevented. Have

As shown in FIG. 3G, the ferroelectric film 46 is grown to a thickness of 100 kPa to 3000 kPa on the flattened resultant after chemical mechanical polishing, and the upper electrode 47 is formed on the ferroelectric film 46. As shown in FIG. Here, the ferroelectric film 46 has a sequence of nucleation, growth, and grain growth, and nuclear growth uses a rapid thermal annealing (RTA) method, and the temperature during rapid heat treatment is 400 ° C to 900 ° C. The ramp up rate is 80 ° C to 250 ° C. The grain growth is carried out by a furnace anneal, the temperature during the heat treatment is 500 ℃ to 800 ℃, the atmosphere gas is O ₂ , N ₂ O, N ₂ , Ar, Ne, Kr, Xe or He Is selected.

On the other hand, as the ferroelectric film 46, SBT [SrBi ₂ Ta ₂ O ₉ ], SBTN [SrBi ₂ (Ta _1-x , Nb _x ) ₂ O ₉ ], BTO (Bi ₄ Ti ₃ O ₁₂ ), BLT [Bi _1-x , La _x ) Ti ₃ O ₁₂ ] or PZT [(Pb, Zr) TiO ₃ ] or a combination thereof, and the ferroelectric film 46 is spin coated or LSMCD (Liquid). It is formed to a thickness of 50 ~ 3000 ~ by using a Source Mixed Chemical Deposition) method.

In addition, the upper electrode 47 may be formed by depositing one selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma enhanced layer deposition (PEALD). It is deposited by using one of platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), iridium oxide film, ruthenium oxide film, tungsten nitride film or titanium nitride film or a composite structure thereof. .

The ferroelectric memory device as described above is referred to as a merged top plate (MTP) structure.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention uses an iridium film having excellent thermal stability as a storage node contact plug to prevent oxidation of the storage node contact plug during a subsequent thermal process, thereby improving the electrical characteristics of the device.

Claims (13)

delete delete Semiconductor substrates; An interlayer insulating film formed on the semiconductor substrate; A storage node contact hole formed through the interlayer insulating layer to expose a portion of the semiconductor substrate; An iridium plug embedded in the storage node contact hole; A lower electrode formed on the iridium plug; An iridium silicide film formed between the semiconductor substrate and the iridium plug; An iridium oxide film formed between the iridium plug and the lower electrode; An isolation insulating film surrounding the lower electrode to expose a surface of the lower electrode; A ferroelectric film formed on the lower electrode and the insulating film; And An upper electrode formed on the ferroelectric film Ferroelectric memory device comprising a. The method of claim 3, wherein And an adhesive layer formed between the lower electrode and the interlayer insulating layer while being in contact with the iridium oxide film and the interlayer insulating layer. The method of claim 4, wherein And the adhesive layer is alumina. The method of claim 3, wherein A ferroelectric memory device, wherein the iridium oxide film has a thickness of 10 GPa to 1000 GPa. The method of claim 3, wherein The iridium silicide film has a thickness of 10 kV to 500 kV. The method of claim 3, wherein The isolation insulating film, A ferroelectric memory device, characterized in that one selected from the HDP oxide film, BPSG, BSG or PSG. Forming an interlayer insulating film on the semiconductor substrate; Selectively etching the interlayer insulating layer to form a storage node contact hole exposing a portion of the semiconductor substrate; Forming an iridium film on the interlayer insulating film until the contact hole is filled; Forming an iridium silicide film at an interface between the semiconductor substrate exposed in the contact hole and the iridium film; Removing an iridium film on the interlayer insulating film to form an iridium plug in the contact hole; Forming an adhesive layer on the iridium plug and the interlayer insulating film; Selectively etching the adhesive layer to expose the iridium plug surface; Forming an iridium oxide film on the exposed iridium plug; And Forming a capacitor including a lower electrode, a ferroelectric layer, and an upper electrode on the iridium oxide film and the adhesive layer Method of manufacturing a ferroelectric memory device comprising a. The method of claim 9, Forming the iridium silicide film, A method of manufacturing a ferroelectric memory device, characterized in that it is made through rapid heat treatment or royal heat treatment. The method of claim 9, Forming the iridium plug, A method of manufacturing a ferroelectric memory device, wherein the iridium film is chemically polished or etched back. The method of claim 9, Forming the iridium oxide film, A method of manufacturing a ferroelectric memory device, characterized in that the rapid heat treatment of the surface of the iridium plug. The method of claim 9, Forming the capacitor, Forming a conductive film for a lower electrode on the iridium oxide film and the adhesive layer; Simultaneously forming the lower electrode conductive layer and the adhesive layer to form a lower electrode; Forming an insulating insulating film surrounding the lower electrode to expose a surface of the lower electrode; Forming a ferroelectric film on the lower electrode and the isolation insulating film; Forming an upper electrode conductive film on the ferroelectric film; And Etching the upper electrode conductive layer to form an upper electrode Method of manufacturing a ferroelectric memory device, characterized in that it comprises a.