KR20040008638A - Method for fabricating Ferroelectric Random Access Memory with bottom electrode isolated by dielectric - Google Patents
Method for fabricating Ferroelectric Random Access Memory with bottom electrode isolated by dielectric Download PDFInfo
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- KR20040008638A KR20040008638A KR1020020042306A KR20020042306A KR20040008638A KR 20040008638 A KR20040008638 A KR 20040008638A KR 1020020042306 A KR1020020042306 A KR 1020020042306A KR 20020042306 A KR20020042306 A KR 20020042306A KR 20040008638 A KR20040008638 A KR 20040008638A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 강유전체 메모리소자 및 그 제조 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a ferroelectric memory device and a method for manufacturing the same.
일반적으로, 반도체 메모리 소자에서 강유전체(Ferroelectric) 박막을 강유전체 캐패시터에 사용함으로써 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(Refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. 이러한 강유전체 박막을 이용하는 강유전체 메모리 소자(Ferroelectric Random Access Memory; 이하 'FeRAM'이라 약칭함) 소자는 비휘발성 메모리 소자(Nonvolatile Memory device)의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. A ferroelectric random access memory device (hereinafter referred to as 'FeRAM') device using the ferroelectric thin film is a nonvolatile memory device, which has an advantage of storing stored information even when power is cut off. In addition, the operating speed is comparable to DRAM, and is becoming the next generation memory device.
도 1은 종래기술에 따른 강유전체 메모리 소자를 도시한 소자 단면도이다.1 is a device cross-sectional view showing a ferroelectric memory device according to the prior art.
도 1을 참조하면, 반도체기판(11)에 활성영역을 정의하는 소자분리막(12)이 형성되고, 반도체기판(11)상에 게이트산화막(13)과 워드라인(14)의 적층구조물이 형성되며, 워드라인(14) 양측의 반도체기판(11)에 소스/드레인영역(15a, 15b)이 형성된다.Referring to FIG. 1, an isolation layer 12 defining an active region is formed on a semiconductor substrate 11, and a stacked structure of a gate oxide layer 13 and a word line 14 is formed on the semiconductor substrate 11. Source / drain regions 15a and 15b are formed in the semiconductor substrate 11 on both sides of the word line 14.
그리고, 워드라인(14)과 소스/드레인영역(15a, 15b)을 포함하는 트랜지스터상에 제1 층간절연막(16)이 형성되고, 제1 층간절연막(16)을 관통하여 일측 소스/드레인영역(15a)에 콘택되는 비트라인콘택(17)을 통해 비트라인(18)이 연결된다.A first interlayer insulating film 16 is formed on the transistor including the word line 14 and the source / drain regions 15a and 15b, and penetrates through the first interlayer insulating film 16 to form one source / drain region ( The bit line 18 is connected through a bit line contact 17 which contacts 15a.
그리고, 비트라인(18)을 포함한 전면에 제2 층간절연막(19)이 형성되고, 제 2층간절연막(19)과 제1 층간절연막(16)을 동시에 관통하여 타측 소스/드레인영역(15b)에 이르는 스토리지노드콘택(20)이 형성된다.A second interlayer insulating film 19 is formed on the entire surface including the bit line 18, and simultaneously passes through the second interlayer insulating film 19 and the first interlayer insulating film 16 to the other source / drain region 15b. Leading storage node contacts 20 are formed.
그리고, 스토리지노드콘택(20)에 연결되는 하부전극(21)이 형성되고, 이웃한 하부전극(21)간 격리를 위해 평탄화된 고립절연막(22)이 하부전극(21)을 에워싸고 있으며, 고립절연막(22)과 하부전극(21)을 강유전체막(23)이 덮는다. 여기서, 강유전체막(23)은 셀영역에만 형성된다. 이때, 하부전극(21)은 이리듐막(Ir, 21a), 이리듐산화막(IrO2, 21b), 백금막(Pt, 21c)의 순서로 적층된 적층막(Pt/IrO2/Ir)이다.In addition, a lower electrode 21 connected to the storage node contact 20 is formed, and a planarized insulating insulating layer 22 surrounds the lower electrode 21 for isolation between adjacent lower electrodes 21. The ferroelectric film 23 covers the insulating film 22 and the lower electrode 21. Here, the ferroelectric film 23 is formed only in the cell region. In this case, the lower electrode 21 is a laminated film (Pt / IrO 2 / Ir) stacked in the order of the iridium films Ir and 21a, the iridium oxide films IrO 2 and 21b, and the platinum films Pt and 21c.
마지막으로, 강유전체막(23) 상에 상부전극(24)이 형성된다.Finally, the upper electrode 24 is formed on the ferroelectric film 23.
상술한 종래기술에 따른 강유전체 메모리소자는 MTP(Merged Top Plate) 구조를 구현한 것이다.The ferroelectric memory device according to the related art described above implements a merged top plate (MTP) structure.
도 1에서, 하부전극이 이리듐막(Ir, 21a), 이리듐산화막(IrO2, 21b), 백금막(Pt, 21c)의 순서로 적층된 적층막이므로 하부전극 패터닝이 용이하도록 하드마스크로서 티타늄나이트라이드막(TiN)을 이용한다.In FIG. 1, since the lower electrode is a laminated film laminated in the order of the iridium film (Ir, 21a), the iridium oxide film (IrO 2 , 21b), and the platinum film (Pt, 21c), titanium nitride as a hard mask to facilitate patterning of the lower electrode. Ride film TiN is used.
그리고, 고립절연막(22)이 하부전극(21)을 에워싸는 형태로 형성시키기 위해, 하부전극(21)을 먼저 형성한 후 고립절연막(22)을 증착하고 하부전극(21) 표면이 드러날때까지 화학적기계적연마(Chemical Mechanical Polishing; CMP)를 통해 고립절연막(22)을 평탄화시킨다.Then, in order to form the insulating insulating film 22 to surround the lower electrode 21, the lower electrode 21 is formed first, and then the insulating insulating film 22 is deposited and chemically until the surface of the lower electrode 21 is exposed. The insulating insulating film 22 is planarized through chemical mechanical polishing (CMP).
그러나, 상술한 종래기술은 하드마스크 제거 과정에서 티타늄나이트라이막이 충분히 제거되지 않고 잔류하는 경우, 후속 강유전체막 증착과 열처리 과정에서 티타늄산화막(TiO2)으로 산화되어 리프팅(Lifting) 및 분극값의 급격한 열화를 초래하여 신뢰성을 저하시키는 문제가 있다.However, in the above-described conventional technique, when the titanium nitride layer is not sufficiently removed during the hard mask removal process, the titanium oxide film (TiO 2 ) is oxidized during the subsequent ferroelectric film deposition and heat treatment process, so that the lifting and polarization values are abrupt. There is a problem of deterioration resulting in deterioration of reliability.
또한, 고립절연막(22)을 평탄화시키기 위한 화학적기계적연마(CMP) 과정에서 하부전극(21)을 이루는 백금막(Pt)(21c)이 손실되며, 이와 같이 백금막이 손실되면 막의 두께가 얇아져 캐패시터의 분극값이 감소되며, 후속 열처리 과정에서 뭉침(agglomeration) 현상이 발생되어 불균일한 캐패시터 특성과 막의 박리현상도 유발할 수 있다.In addition, during the chemical mechanical polishing (CMP) process to planarize the insulating insulating film 22, the platinum film Pt 21c constituting the lower electrode 21 is lost. If the platinum film is lost, the thickness of the capacitor becomes thinner. The polarization value is reduced, and agglomeration may occur during the subsequent heat treatment, which may cause uneven capacitor characteristics and film peeling.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로, 하부전극을 패터닝하기 위한 하드마스크가 잔류함에 따른 리프팅 및 분극값 열화를 억제하고, 고립절연막의 평탄화시 하부전극 표면이 손실되는 것을 방지하는데 적합한 강유전체 메모리 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned problems of the prior art, it is to suppress the deterioration of the lifting and polarization value due to the remaining hard mask for patterning the lower electrode, the loss of the lower electrode surface during planarization of the insulating insulating film It is an object of the present invention to provide a method for manufacturing a ferroelectric memory device suitable for preventing.
도 1은 종래기술에 따른 강유전체 메모리 소자를 도시한 도면,1 illustrates a ferroelectric memory device according to the prior art;
도 2a 내지 도 2e는 본 발명의 실시예에 따른 강유전체 메모리 소자의 제조 방법을 도시한 공정 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 소자분리막31: semiconductor substrate 32: device isolation film
33 : 게이트산화막 34 : 워드라인33: gate oxide film 34: word line
35a,35b : 소스/드레인영역 36 : 제1 층간절연막35a, 35b: source / drain region 36: first interlayer insulating film
37 : 비트라인콘택 38 : 비트라인37: bit line contact 38: bit line
39 : 제2 층간절연막 40 : 스토리지노드콘택39: second interlayer insulating film 40: storage node contact
41a : 이리듐막 42a : 이리듐산화막41a: iridium film 42a: iridium oxide film
43a : 백금막 44a : 티타늄나이트라이드막43a: platinum film 44a: titanium nitride film
46b : 고립절연막 47 : 강유전체막46b: insulating film 47: ferroelectric film
48 : 상부전극48: upper electrode
상기 목적을 달성하기 위한 본 발명의 강유전체 메모리 소자의 제조 방법은 반도체기판 상부에 층간절연막을 형성하는 단계, 상기 층간절연막상에 하부전극과 하드마스크의 순서로 적층된 적층막을 형성하는 단계, 상기 적층막을 포함한 전면에 고립절연막을 형성하는 단계, 상기 하드마스크의 표면이 드러날때까지 상기 고립절연막을 평탄화시키는 단계, 상기 하드마스크를 액체케미컬을 이용하여 제거하는 단계, 상기 하드마스크 제거후 드러난 상기 하부전극을 포함한 전면에 강유전체막을 형성하는 단계, 및 상기 강유전체막상에 상부전극을 형성하는 단계를 포함함을 특징으로 하고, 상기 하드마스크는 티타늄나이트라이드막인 것을 특징으로 하며, 상기 액체 케미컬은 HCl/H2O2/H2O의 혼합액인 SC-1 액체케미컬인 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory device, including forming an interlayer insulating film on an upper surface of a semiconductor substrate, and forming a laminated film laminated on the interlayer insulating film in the order of a lower electrode and a hard mask. Forming an insulating insulating film on the entire surface including a film; planarizing the insulating insulating film until the surface of the hard mask is exposed; removing the hard mask using a liquid chemical; and removing the lower electrode after removing the hard mask. And forming an upper electrode on the ferroelectric film, wherein the hard mask is a titanium nitride film, and the liquid chemical is HCl / H. It is characterized in that the SC-1 liquid chemical which is a mixture of 2 O 2 / H 2 O.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2e은 본 발명의 실시예에 따른 강유전체 메모리 소자의 제조 방법을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(31)에 소자간 분리를 위한 소자분리막(32)을 형성하여 활성영역을 정의하고, 반도체기판(31)의 활성영역상에 게이트산화막(33)과 워드라인(34)을 차례로 형성한다.As shown in FIG. 2A, an isolation region 32 for device isolation is formed on the semiconductor substrate 31 to define an active region, and a gate oxide layer 33 and a word are formed on the active region of the semiconductor substrate 31. Lines 34 are formed in sequence.
다음으로, 워드라인(34) 양측의 반도체기판(31)에 불순물을 이온주입하여 트랜지스터의 소스/드레인영역(35a, 35b)을 형성한다.Next, impurities are implanted into the semiconductor substrate 31 on both sides of the word line 34 to form source / drain regions 35a and 35b of the transistor.
한편, 도면에 도시되지 않았지만, 워드라인의 양측벽에 스페이서를 형성할 수 있고, 이에 따라 LDD(Lightly Doped Drain) 구조의 소스/드레인영역을 형성할 수 있다. 즉, 워드라인을 마스크로 저농도 불순물을 이온주입하여 LDD 영역을 형성한 후, 워드라인의 양측벽에 스페이서를 형성하고, 워드라인과 스페이서를 마스크로 고농도 불순물을 이온주입하여 LDD 영역에 접하는 소스/드레인영역을 형성한다.Although not shown in the drawings, spacers may be formed on both sidewalls of the word line, thereby forming a source / drain region having a lightly doped drain (LDD) structure. In other words, the LDD region is formed by ion implanting low concentration impurities using a word line as a mask, and then spacers are formed on both sidewalls of the word line, and the ion / implant implanted with high concentration impurities using the word line and spacer as a mask to contact the LDD region. A drain region is formed.
다음으로, 트랜지스터가 형성된 반도체기판(31)상에 제1 층간절연막(36)을 증착 및 평탄화한 후, 콘택마스크(도시 생략)로 제1 층간절연막(36)을 식각하여 일측 소스/드레인영역(35a)을 노출시키는 비트라인콘택홀을 형성하고, 비트라인콘택홀에 매립되는 비트라인콘택(37)을 형성한다. 여기서, 비트라인콘택(37)은 텅스텐(W)을 증착한 후 에치백(Etch back)이나 화학적기계적연마(Chemical Mechanical Polishing; CMP)를 통해 형성한 텅스텐플러그(W-plug)일 수 있다.Next, after depositing and planarizing the first interlayer insulating layer 36 on the semiconductor substrate 31 on which the transistor is formed, the first interlayer insulating layer 36 is etched with a contact mask (not shown) to etch one side source / drain region ( A bit line contact hole exposing 35a) is formed, and a bit line contact 37 embedded in the bit line contact hole is formed. Here, the bit line contact 37 may be a tungsten plug (W-plug) formed by depositing tungsten (W) and then etch back or chemical mechanical polishing (CMP).
다음으로, 전면에 비트라인용 도전막을 증착한 후 패터닝하여 비트라인콘택에 연결되는 비트라인(38)을 형성하고, 비트라인(38)을 포함한 전면에 제2 층간절연막(39)을 증착한 후 평탄화한다.Next, after the bit line conductive film is deposited on the entire surface, patterning is performed to form a bit line 38 connected to the bit line contact, and a second interlayer insulating layer 39 is deposited on the entire surface including the bit line 38. Flatten.
다음으로, 스토리지노드콘택마스크(도시 생략)로 제2 층간절연막(39)과 제1 층간절연막(36)을 동시에 식각하여 타측 소스/드레인영역(35b)을 노출시키는 스토리지노드콘택홀을 형성한 후, 스토리지노드콘택홀에 스토리지노드콘택(40)을 매립시킨다.Next, the second interlayer insulating layer 39 and the first interlayer insulating layer 36 are simultaneously etched with a storage node contact mask (not shown) to form a storage node contact hole exposing the other source / drain region 35b. The storage node contact 40 is buried in the storage node contact hole.
한편, 스토리지노드콘택(40)은 폴리실리콘플러그(polysilicon-plug), 티타늄실리사이드(Ti-silicide) 및 티타늄나이트라이드(TiN)의 순서로 적층된 구조물로서, 이들의 형성 방법은 생략하기로 한다. 여기서, 티타늄실리사이드는 폴리실리콘플러그와 하부전극간 오믹콘택을 형성해주며, 티타늄나이트라이드는 폴리실리콘플러그와 하부전극간 상호확산을 방지하는 확산배리어막이고, 티타늄나이트라이드막은 화학적기계적연마(CMP)를 통해 평탄화된다.On the other hand, the storage node contact 40 is a structure stacked in the order of polysilicon plug (polysilicon-plug), titanium silicide (Ti-silicide) and titanium nitride (TiN), the formation method thereof will be omitted. Here, titanium silicide forms an ohmic contact between the polysilicon plug and the lower electrode, and titanium nitride is a diffusion barrier film that prevents mutual diffusion between the polysilicon plug and the lower electrode, and the titanium nitride film is chemical mechanical polishing (CMP). Planarized through.
다른 스토리지노드콘택(40)의 형성 방법으로는 티타늄막을 증착한 후 열처리하여 티타늄실리사이드막을 형성한 후, 텅스텐막을 플러깅시키고, 배리어메탈로서 티타늄나이트라이드막을 형성한 후 화학적기계적연마(CMP)를 통해 평탄화시킬 수 있다.Another method of forming the storage node contact 40 is to deposit a titanium film and then heat-treat it to form a titanium silicide film, then plug the tungsten film, form a titanium nitride film as a barrier metal, and then planarize it through chemical mechanical polishing (CMP). You can.
다음으로, 스토리지노드콘택(40)을 포함한 제2 층간절연막(39)상에 하부전극을 이룰 도전막으로서 이리듐막(Ir, 41), 이리듐산화막(IrO2, 42), 백금막(Pt, 43)을 차례로 증착한다. 이때, 이리듐막(41), 이리듐산화막(42), 백금막(43)은 각각 200Å∼2000Å의 두께로 증착된다.Next, an iridium film Ir, 41, an iridium oxide film IrO 2 , 42, and a platinum film Pt, 43 as a conductive film for forming a lower electrode on the second interlayer insulating film 39 including the storage node contact 40. ) In order. At this time, the iridium film 41, the iridium oxide film 42, and the platinum film 43 are deposited with a thickness of 200 kPa to 2000 kPa, respectively.
다음에, 백금막(43)상에 하부전극 패터닝시 하드마스크로 이용되는 티타늄나이트라이드막(44)을 증착한 후, 티타늄나이트라이드막(44)상에 하부전극을 정의하는 감광막패턴(45)을 형성한다. 이때, 티타늄나이트라이드막(44)은 50Å∼1000Å의 두께로 증착되며, 티타늄나이트라이드막(44)은 하부전극의 패터닝시 기울기 특성이 우수한 하드마스크이다.Next, after depositing a titanium nitride film 44 used as a hard mask when patterning the lower electrode on the platinum film 43, a photosensitive film pattern 45 defining a lower electrode on the titanium nitride film 44 To form. At this time, the titanium nitride film 44 is deposited to a thickness of 50 kPa to 1000 kPa, and the titanium nitride film 44 is a hard mask having excellent inclination characteristics when patterning the lower electrode.
그리고, 감광막패턴(45)을 마스크로 티타늄나이트라이드막(44)을 식각한다.The titanium nitride film 44 is etched using the photosensitive film pattern 45 as a mask.
도 2b에 도시된 바와 같이, 감광막패턴(45)을 제거한 후, 식각처리된 티타늄나이트라이드막(44)을 식각마스크로 백금막(43), 이리듐산화막(42), 이리듐막(41)을 차례로 패터닝하여 이리듐막(41a), 이리듐산화막(42a) 및 백금막(43a)의 순서로 적층된 하부전극을 완성한다. 이로써, 하부전극은 산소배리어막(oxygen barrier) 역할을 수행하는 이리듐막(41a), 접착층(glue layer) 역할을 수행하는 이리듐산화막(42a)과 금속막인 백금막(43)의 순서로 적층된 3중 구조이다.As shown in FIG. 2B, after the photoresist layer pattern 45 is removed, the platinum layer 43, the iridium oxide layer 42, and the iridium layer 41 are sequentially formed using the etched titanium nitride layer 44 as an etch mask. By patterning, the lower electrodes stacked in the order of the iridium film 41a, the iridium oxide film 42a, and the platinum film 43a are completed. Accordingly, the lower electrode is laminated in the order of the iridium film 41a serving as an oxygen barrier film, the iridium oxide film 42a serving as a glue layer, and the platinum film 43 serving as a metal film. It is a triple structure.
하부전극을 이루는 금속막으로는 백금막외에 루테늄막, 이리듐막, 텅스텐막 또는 텅스텐나이트라이드막중에서 선택되고, 접착층으로는 이리듐산화막외에 루테늄산화막 또는 텅스텐산화막중에서 선택되며, 산소배리어막으로는 이리듐막외에 루테늄막을 선택할 수 있다.The metal layer constituting the lower electrode is selected from a ruthenium film, an iridium film, a tungsten film, or a tungsten nitride film in addition to the platinum film. In addition, a ruthenium film can be selected.
상기한 바와 같이 하부전극 패터닝시 하드마스크인 티타늄나이트라이드막 (44)은 일부분 소모되어 백금막(43)상에 두께가 감소하여 잔류한다. 이하, 잔류하는 티타늄나이트라이드막을 도면부호 '44a'라 한다.As described above, the titanium nitride film 44, which is a hard mask, is partially consumed when the lower electrode is patterned, and the thickness remains on the platinum film 43. Hereinafter, the remaining titanium nitride film is referred to as '44a'.
다음에, 이웃한 하부전극간 공간을 채울때까지 하부전극을 포함한 전면에 고립절연막(46)을 형성한다. 이때, 고립절연막(46)은 HDP(High Density Plasma) 산화막, BPSG, BSG 또는 PSG 중에서 선택된 하나이며, 1000Å∼10000Å의 두께로 형성된다.Next, an insulating insulating film 46 is formed on the entire surface including the lower electrode until the space between adjacent lower electrodes is filled. At this time, the isolation insulating film 46 is one selected from a high density plasma (HDP) oxide film, a BPSG, a BSG, or a PSG, and has a thickness of 1000 kPa to 10,000 kPa.
도 2c에 도시된 바와 같이, 티타늄나이트라이드막(44a)의 표면이 드러날때까지 화학적기계적연마(CMP)를 통해 고립절연막(46)을 평탄화시킨다. 이때, 화학적기계적연마과정시 티타늄나이트라이드막(44a)이 백금막(43a)을 캡핑(capping)하고 있으므로, 과도 화학적기계적연마(over CMP)되더라도 백금막(43a)이 손실되는 것을 억제한다.As shown in FIG. 2C, the insulating insulating film 46 is planarized through chemical mechanical polishing (CMP) until the surface of the titanium nitride film 44a is exposed. At this time, since the titanium nitride film 44a caps the platinum film 43a during the chemical mechanical polishing process, the platinum film 43a is suppressed from being lost even when over-chemical mechanical polishing (over CMP) occurs.
도 2d에 도시된 바와 같이, 백금막(43a)상에 잔류하는 티타늄나이트라이드막(44a)을 제거하되, SC-1 액체 케미컬에 담그어 제거한다. 이때, 티타늄나이트라이드막(44a) 제거시 고립절연막(46a)이 산화막이므로 액체 케미컬에 쉽게 제거되고, 결국 백금막(43a) 표면이 드러나는 시점까지 고립절연막(46a)이 제거된다.As shown in FIG. 2D, the titanium nitride film 44a remaining on the platinum film 43a is removed, but immersed in SC-1 liquid chemical to remove it. At this time, since the insulating insulating film 46a is an oxide film when the titanium nitride film 44a is removed, the insulating insulating film 46a is easily removed by the liquid chemical, and thus the insulating insulating film 46a is removed until the surface of the platinum film 43a is exposed.
여기서, SC-1 액체 케미컬은 HCl/H2O2/H2O의 혼합액으로서 금속막과의 반응성이 우수하기 때문에 티타늄나이트라이드막(44a)을 쉽게 제거할 수 있고, 이로써 고립절연막(46a) 또한 쉽게 제거되어 우수한 백금막(43a) 표면을 이룰 수 있다.Here, the SC-1 liquid chemical is a mixed solution of HCl / H 2 O 2 / H 2 O, which is excellent in reactivity with the metal film, so that the titanium nitride film 44a can be easily removed, whereby the insulating insulating film 46a is provided. In addition, it can be easily removed to form an excellent platinum film 43a surface.
결국, 잔류하는 고립절연막(46b)은 이웃한 하부전극들을 서로 절연시키면서 적층구조의 하부전극을 에워싸는 형태를 갖는다.As a result, the remaining insulating insulating film 46b surrounds the lower electrodes of the stacked structure while insulating neighboring lower electrodes from each other.
이와 같이, 하부전극을 고립절연막(46b)에 에워싸이는 형태로 형성하므로써 캐패시터의 단차에 따른 마스크작업의 부담 및 평탄화의 어려움, 그리고 상하부전극간 단락을 방지할 수 있는 장점을 갖는다.As described above, the lower electrode is formed in the form of being surrounded by the insulating insulating film 46b, so that the burden of the mask work due to the step difference of the capacitor, difficulty in planarization, and short circuit between the upper and lower electrodes can be prevented.
도 2e에 도시된 바와 같이, 화학적기계적연마후 평탄화된 결과물상에 강유전체막(47)을 50Å∼3000Å의 두께로 성장시키고, 강유전체막(47)상에 상부전극(48)을 형성한다. 여기서, 강유전체막(47)은 핵생성 및 성장과 결정립성장의시퀀스(sequence)를 갖고, 핵성장은 급속열처리(Rapid Thermal Anneal; RTA) 방법을 이용하며, 급속열처리시 온도는 400℃∼900℃이고, 램프업(ramp up) 속도는 80℃∼250℃이다. 그리고, 결정립성장은 로열처리(furnace anneal)를 수행하며, 로열처리시 온도는 500℃∼800℃이고, 분위기 가스는 O2, N2O, N2, Ar, Ne, Kr, Xe 또는 He 중에서 선택된다.As shown in FIG. 2E, the ferroelectric film 47 is grown to a thickness of 50 kPa to 3000 kPa on the flattened resultant after chemical mechanical polishing, and the upper electrode 48 is formed on the ferroelectric film 47. Here, the ferroelectric film 47 has a sequence of nucleation, growth and grain growth, and nuclear growth uses a rapid thermal annealing (RTA) method, and the temperature during rapid heat treatment is 400 ° C to 900 ° C. The ramp up rate is 80 ° C to 250 ° C. The grain growth is carried out by a furnace anneal, the temperature during the heat treatment is 500 ℃ to 800 ℃, the atmosphere gas is O 2 , N 2 O, N 2 , Ar, Ne, Kr, Xe or He Is selected.
한편, 강유전체막(47)으로는 SBT[SrBi2Ta2O9], SBTN[SrBi2(Ta1-x, Nbx)2O9], BTO(Bi4Ti3O12), BLT[Bi1-x, Lax)Ti3O12] 또는 PZT[(Pb, Zr)TiO3]중에서 선택된 하나이거나 이들의 조합막이며, 강유전체막(47)은 스핀코팅(Spin coating)법 또는 LSMCD(Liquid Source Mixed Chemical Deposition)법을 이용하여 50Å∼3000Å의 두께로 형성된다.On the other hand, as the ferroelectric film 47, SBT [SrBi 2 Ta 2 O 9 ], SBTN [SrBi 2 (Ta 1-x , Nb x ) 2 O 9 ], BTO (Bi 4 Ti 3 O 12 ), BLT [Bi 1-x , La x ) Ti 3 O 12 ] or PZT [(Pb, Zr) TiO 3 ] or a combination thereof, and the ferroelectric film 47 is spin coated or LSMCD (Liquid). It is formed to a thickness of 50 ~ 3000 ~ by using a Source Mixed Chemical Deposition) method.
그리고, 상부전극(48)은 화학기상증착법(CVD), 물리기상증착법(PVD), 원자층증착법(Atomic Layer Deposition; ALD) 및 플라즈마원자층증착법(Plasma Enhanced ALD; PEALD) 중에서 선택된 하나의 증착법을 이용하여 증착되며, 백금(Pt), 이리듐(Ir), 루테늄(Ru), 텅스텐(W), 이리듐산화막, 루테늄산화막, 텅스텐나이트라이드막 또는 티타늄나이트라이드막 중에서 선택된 하나이거나 이들의 복합구조물을 이용한다.In addition, the upper electrode 48 may be formed by depositing one selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma enhanced layer deposition (PEALD). It is deposited by using one of platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), iridium oxide film, ruthenium oxide film, tungsten nitride film or titanium nitride film or a composite structure thereof. .
전술한 실시예에서는 산소배리어막, 접착층과 금속막의 순서로 적층된 3중 구조의 하부전극을 예로 들었으나, 하부전극이 금속막 단일층인 경우에도 적용가능하다. 이때, 금속막은 실시예와 동일하게 Pt, Ru, Ir, W 또는 WN 중에서 선택된다.In the above embodiment, the lower electrode having a triple structure stacked in the order of the oxygen barrier film, the adhesive layer, and the metal film is taken as an example, but it is also applicable to the case where the lower electrode is a metal film single layer. At this time, the metal film is selected from Pt, Ru, Ir, W or WN as in the embodiment.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 화학적기계적연마시 하부전극 표면이 손실되는 것을 방지하므로써 캐패시터의 분극값 열화를 방지하여 캐패시터의 전기적 특성을 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of preventing the lower electrode surface from being lost during chemical mechanical polishing, thereby preventing the polarization of the capacitor from deteriorating, thereby improving the electrical characteristics of the capacitor.
또한, 하부전극의 패터닝을 용이하기 하기 위해 도입한 하드마스크를 제거하므로써 캐패시터의 신뢰성을 확보할 수 있는 효과가 있다.In addition, it is possible to secure the reliability of the capacitor by removing the hard mask introduced to facilitate the patterning of the lower electrode.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020042306A KR20040008638A (en) | 2002-07-19 | 2002-07-19 | Method for fabricating Ferroelectric Random Access Memory with bottom electrode isolated by dielectric |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020020042306A KR20040008638A (en) | 2002-07-19 | 2002-07-19 | Method for fabricating Ferroelectric Random Access Memory with bottom electrode isolated by dielectric |
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| Publication Number | Publication Date |
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| KR20040008638A true KR20040008638A (en) | 2004-01-31 |
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| KR1020020042306A KR20040008638A (en) | 2002-07-19 | 2002-07-19 | Method for fabricating Ferroelectric Random Access Memory with bottom electrode isolated by dielectric |
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| KR (1) | KR20040008638A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100697272B1 (en) * | 2004-08-06 | 2007-03-21 | 삼성전자주식회사 | A ferroelectric memory device and a method of forming the same |
-
2002
- 2002-07-19 KR KR1020020042306A patent/KR20040008638A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100697272B1 (en) * | 2004-08-06 | 2007-03-21 | 삼성전자주식회사 | A ferroelectric memory device and a method of forming the same |
| US7517703B2 (en) | 2004-08-06 | 2009-04-14 | Samsung Electronics Co., Ltd. | Method for forming ferroelectric memory device |
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