KR20030057704A - Ferroelectric Capacitor and the method for fabricating the same - Google Patents

Abstract

PURPOSE: A ferroelectric capacitor and a method for manufacturing the same are provided to be capable of preventing the degradation of a ferroelectric film by forming a lower and upper electrode before forming the ferroelectric film. CONSTITUTION: A lower electrode(43) is formed on a semiconductor substrate(31). A pair of upper electrodes(44a,44b) are formed at both sides of the lower electrode(43) and spaced apart from each other. A ferroelectric film(45) is covered on and between the lower electrode(43) and the upper electrodes(44a,44b). At this time, the pair of upper electrodes(44a,44b) are also used as a plate line. The lower electrode(43) has an island shape, and the upper electrodes(44a,44b) have a line shape. Also, the lower electrode(43) and the upper electrodes(44a,44b) have the same thickness.

Description

Ferroelectric capacitors and method of manufacturing the same {Ferroelectric Capacitor and the method for fabricating the same}

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a ferroelectric memory device and a method for manufacturing the same.

In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. A ferroelectric random access memory device (hereinafter referred to as 'FeRAM') device using the ferroelectric thin film is a nonvolatile memory device, which has an advantage of storing stored information even when power is cut off. In addition, the operating speed is comparable to DRAM, and is becoming the next generation memory device.

Ferroelectric thin films such as SrBi ₂ Ta ₂ O ₉ (hereinafter abbreviated as 'SBT') and Pb (Zr, Ti) O ₃ (hereinafter abbreviated as 'PZT') are mainly used as storage materials for such FeRAM devices. Ferroelectric thin films have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable Remnant polarization (Pr) states.

Non-volatile memory devices using ferroelectric thin films store the digital signals '1' and '0' by controlling the direction of polarization in the direction of the applied electric field and inputting the signal, and the residual polarization remaining when the electric field is removed. The hysteresis characteristic is used.

When using a ferroelectric thin film such as Sr _x Bi _y (Ta _i Nb _j ) ₂ O ₉ (hereinafter referred to as SBTN) having a perovskite structure in addition to the above-described PZT and SBT as a ferroelectric thin film of a ferroelectric capacitor in a FeRAM device In general, upper and lower electrodes are formed by using metals such as platinum (Pt), iridium (Ir), ruthenium (Ru), iridium oxide (IrO), ruthenium oxide (RuO), and platinum alloy (Pt-alloy). .

1 is a layout diagram of a ferroelectric memory cell according to the prior art.

Referring to FIG. 1, word lines WL ₁ and WL ₂ are arranged in a direction crossing the active region ACT and the active region ACT of the semiconductor substrate, and are arranged on the word lines WL ₁ and WL ₂ . The bit lines BL ₁ and BL ₂ are arranged in the vertical crossing direction (for example, the word lines are arranged in the Y-axis direction and the bit lines are arranged in the X-axis direction).

Then, the bit line contacts BLC ₁ and BLC _{2 for} contacting the active region ACT and the bit lines BL ₁ and BL ₂ between the word lines WL ₁ and WL ₂ are disposed, and one word line is disposed. (WL ₁₎ parallel to the first capacitor module according to (capacitor module; CM ₁₎ is arranged, it is arranged in parallel with the second capacitor module (CM ₂₎ along the other of the word line (WL _2).

On the other hand, the first capacitor module CM ₁ is a storage node contact (SNC ₁ ) and a storage node contact (SNC ₁ ) contacted with the other side of the active area ACT to which the bit line contact BLC ₁ is connected. the island (island) while overlapping with the shape of the bottom electrode (BE _1), the lower electrode (BE ₁₎ the area overlapping the upper electrode of the small island shape than the bottom electrode (TE _1), the upper electrode (TE ₁₎ coupled to The plate line PL ₁ is arranged in the same direction as the word line WL ₁ .

In addition, the second capacitor module CM ₂ has an island-type lower portion in which the bit line contact BLC _{2 is} connected to the storage node contact SNC ₂ and the storage node contact SNC ₂ , which contact the other side of the active area. electrode (BE _2), the lower electrode (BE ₂₎ and while overlapping the upper electrode of the small island-type than the area of the bottom electrode _{(BE 2) (TE 2)} , as overlapping the top electrode (TE ₂₎ a word line (WL ₂ It is composed of a plate line (PL ₂ ) arranged in the same direction as).

In the above-described first capacitor module and the second capacitor module, a plurality of lower electrodes and a plurality of upper electrodes constitute one capacitor, and the plate lines and the upper electrodes are connected through capacitor contacts CPAC ₁ and CAPC ₂ , respectively. do.

2A to 2B are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device taken along the line y-y 'of FIG. 1.

As shown in FIG. 2A, after the gate oxide film 12 and the word line 13 are formed on the semiconductor substrate 11, impurities are implanted into the semiconductor substrate 11 on both sides of the word line 13 to form a source. / Drain 14 is formed.

Next, after the first interlayer insulating film 15 is formed on the semiconductor substrate 11 including the word line 13, the first interlayer insulating film 15 is etched using the contact mask as an etch mask to etch the source / drain 14. A bit line contact hole (not shown) is formed to expose one side of Subsequently, the bit line 16 connected to one side of the source / drain 14 through the bit line contact hole is formed.

Next, after forming the second interlayer insulating film 17 on the semiconductor substrate 11 including the bit line 16, a storage node contact mask (not shown) is formed on the second interlayer insulating film 17. The second interlayer insulating layer 17 exposed by the storage node contact mask is etched to form a storage node contact hole (not shown) that exposes the other side of the source / drain 14.

Next, the storage node contact 18 is embedded in the storage node contact hole.

In this case, the storage node contacts 18 are typically stacked in the order of polysilicon plugs, titanium silicides, and titanium nitrides, and their formation methods will be omitted.

Here, titanium silicide forms an ohmic contact between the polysilicon plug and the lower electrode, and titanium nitride is a barrier layer that prevents mutual diffusion between the lower electrode and the polysilicon plug.

Subsequently, after forming the adhesive layer 19 on the second interlayer insulating layer 17 having the storage node contact 18 embedded therein, the contact hole for selectively opening the storage node contact 18 by selectively etching the adhesive layer 19. (Not shown) is formed. In this case, the contact hole formed after etching the adhesive layer 19 not only opens the storage node contact 18 but also exposes a part of the second interlayer insulating layer 17 around the storage node contact 18.

This adhesive layer 19 is used to increase the adhesion between the lower electrode and the interlayer insulating film when metal is used as the subsequent lower electrode.

Next, the lower electrode 20, the ferroelectric film 21, and the upper electrode 22 are sequentially formed on the adhesive layer 19, and then the upper electrode 22 is etched first to a line width larger than that of the upper electrode 22. The ferroelectric film 21, the lower electrode 20, and the adhesive layer 19 are simultaneously etched to form a ferroelectric capacitor.

As shown in FIG. 2B, after forming the third interlayer insulating film 23 on the ferroelectric capacitor, the capacitor contact hole exposing the surface of the upper electrode 22 by selectively etching the second interlayer insulating film 23. (Not shown) is formed. Here, the capacitor contact hole typically provides a contact hole for contacting the metal wiring and the upper electrode.

Next, the metal wiring 25 connected to the upper electrode 22 through the capacitor contact hole is formed. In this case, a diffusion barrier 24 may be inserted between the metal wire 25 and the upper electrode 22 to prevent impurities in the metal wire 25 from diffusing into the upper electrode 22.

However, the above-described prior art has a problem in that the ferroelectric film is deteriorated by being exposed to plasma generated during etching of the upper electrode and the lower electrode and during a capacitor contact etching process that exposes a part of the surface of the upper electrode.

In order to solve this problem, a thermal recovery process is performed after the upper and lower electrode etching and after the capacitor contact etching to restore the characteristics of the ferroelectric film.

However, since the capacitor size gradually decreases as the ferroelectric memory device is highly integrated, there is a limit in recovering the loss of the etching process in a subsequent process, and thus, an integrated process is required to prevent this.

The present invention has been made to solve the problems of the prior art, to prevent the ferroelectric film is degraded by exposure to the plasma generated in the etching process for forming the capacitor and the capacitor contact etching process for connecting the upper electrode to the metal wiring. It is an object to provide a method for producing a suitable ferroelectric capacitor.

1 is a layout diagram of a ferroelectric memory cell according to the prior art;

2A to 2B are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to the prior art;

3 is a layout diagram of a ferroelectric memory cell according to an embodiment of the present invention;

4A to 4C are cross-sectional views illustrating a method of manufacturing a ferroelectric capacitor according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

39: adhesive layer 40: electrode film

41: hard mask 43: lower electrode

44a, 44b: pair of upper electrodes 45: ferroelectric film

The ferroelectric capacitor of the present invention for achieving the above object is a lower electrode, a pair of upper electrodes arranged horizontally at predetermined intervals on both sides of the lower electrode; And a ferroelectric layer covering the gap between the lower electrode and the pair of upper electrodes and the upper portion of the lower electrode and the pair of upper electrodes, wherein the pair of upper electrodes double as a plate line.

The method of manufacturing the ferroelectric capacitor of the present invention includes forming an electrode film on a planarized insulating film, selectively etching the electrode film, and forming a pair of upper electrodes spaced apart from one lower electrode and the lower electrode at predetermined intervals. And forming a ferroelectric film on the lower electrode and the pair of upper electrodes until the gap between the lower electrode and the pair of upper electrodes is completely filled.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a layout diagram of a ferroelectric memory cell according to an embodiment of the present invention.

Referring to FIG. 3, word lines WL ₁ and WL ₂ are disposed in a direction crossing the active region ACT and the active region ACT of the semiconductor substrate, and perpendicularly intersect the word lines WL ₁ and WL ₂ . The bit lines BL ₁ and BL ₂ are arranged in the direction of the direction (for example, the word lines are arranged in the Y-axis direction and the bit lines are arranged in the X-axis direction).

Then, the bit line contacts BLC ₁ and BLC _{2 for} contacting the active region ACT and the bit lines BL ₁ and BL ₂ between the word lines WL ₁ and WL ₂ are disposed, and one word line is disposed. are arranged in parallel to the first capacitor module (CM ₁₎ in accordance with the (WL _1), it is arranged in parallel to the second capacitor module (CM ₂₎ along the other of the word line (WL _2).

On the other hand, the first capacitor module (CM ₁₎ is of an island-type connection to the other and which contact the storage node contacts the bit line contact is connected to the active region () (SNC _1), a storage node contact (SNC ₁₎ lower electrode ( BE ₁ ) and a pair of upper electrodes TE _11- TE _{12 in the} form of a line disposed in the same direction as the word line WL ₁ on both sides of the lower electrode BE ₁ .

Then, the second capacitor module (CM ₂₎ are bit line contacts the other and which contact the storage node contacts in the active region (ACT) (SNC _2), a storage node contact (SNC ₂₎ The island-type of bottom electrode (BE connected to ₂ ), the lower electrode BE ₂ includes a pair of upper electrodes TE _21- TE ₂₂ having a line shape disposed in the same direction as the word line WL ₂ .

Above the first capacitor module (CM ₁₎ and the second capacitor module (CM ₂₎ is shared by one (TE _12, TE ₂₂₎ of the pair of top electrode _{(TE 11 -TE 12, TE 21} -TE 22) The pair of upper electrodes serve as plate lines PL.

Referring to FIG. 3, a pair of upper electrodes common to a plurality of lower electrodes form a capacitor, and a pair of upper electrodes TE _11- TE ₁₂ and TE _21- TE ₂₂ are used as plate lines. There is no need, and a capacitor contact (CAPC) for connecting the upper electrode and the plate line is also unnecessary.

As will be described later, when the lower electrode and the pair of upper electrodes are disposed in parallel at a predetermined distance, the ferroelectric film covers the upper part while filling the lower electrode and the upper electrode, thereby preventing deterioration of the ferroelectric film according to the conventional etching process.

4A to 4C are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device taken along the line y-y 'of FIG. 3.

As shown in FIG. 4A, after the gate oxide layer 32 and the word line 33 are formed on the semiconductor substrate 31, impurities are implanted into the semiconductor substrate 31 on both sides of the word line 33 to form a source. / Drain 34 is formed.

Next, after the first interlayer insulating film 35 is formed on the semiconductor substrate 31 including the word line 33, the first interlayer insulating film 35 is etched using a contact mask (not shown) as an etch mask. Bit line contact holes (not shown) that expose one side of the drain 34 are formed. Subsequently, a bit line 36 connected to one side of the source / drain 34 through the bit line contact hole is formed.

Next, after forming the second interlayer insulating film 37 on the semiconductor substrate 31 including the bit line 36, a storage node contact mask (not shown) is formed on the second interlayer insulating film 37. The second interlayer insulating layer 37 exposed by the storage node contact mask is etched to form a storage node contact hole (not shown) that exposes the other side of the source / drain 34.

Next, the storage node contact 38 is buried in the storage node contact hole.

In this case, the storage node contacts 38 are typically stacked in the order of polysilicon plug, titanium silicide (Ti-silicide) and titanium nitride (TiN), and their formation methods will be omitted.

Subsequently, after the adhesive layer 39 is formed on the second interlayer insulating layer 37 having the storage node contact 38 embedded therein, the adhesive hole 39 is selectively etched to open the storage node contact 38. (Not shown) is formed. In this case, the contact hole formed after etching the adhesive layer 39 not only opens the storage node contact 38 but also exposes a part of the second interlayer insulating layer 37 around the storage node contact 38.

The adhesive layer 39 is used to increase the adhesion between the lower electrode and the second interlayer insulating film 37 when a metal is used as a subsequent lower electrode, and typically uses TiO ₂ , Al ₂ O ₃ , Ta, or Ti.

Next, an electrode film 40 to be used as an upper electrode and a lower electrode is deposited on the adhesive layer 39.

In this case, the electrode film 40 is a single layer or a multilayer film in which at least two layers are selected from Pt, Ir, IrO ₂ , Ru, and RuO ₂ , and the electrode films 40 are chemical vapor deposition (CVD) and plasma chemical vapor deposition. (PECVD), Atomic Layer Deposition (ALD), Plasma Atomic Layer Deposition (PEALD), and a deposition method selected from one of sputtering to deposit a thickness of 100 kPa to 20000 kPa.

Next, a hard mask 41 is deposited on the electrode film 40 to facilitate masking. In this case, the hard mask 41 is one selected from TiN, an oxide film, and an organic anti-reflective coating.

Subsequently, a photoresist film is applied on the hard mask 41 and patterned by exposure and development to form a storage node mask 42. In this case, the storage node mask 42 is a mask for simultaneously forming one lower electrode and a pair of upper electrodes in parallel, and is a mask for etching the upper electrode and a mask process for simultaneously etching the ferroelectric layer and the lower electrode. In comparison, there is an advantage that one mask process can be omitted.

As shown in FIG. 4B, the hard mask 41 exposed by the storage node mask 42 is etched, and the electrode layer 40 and the adhesive layer 39 exposed after the hard mask 41 are etched are etched. A pair of upper electrodes 44a in a line form arranged parallel to the lower electrodes 43 in the same direction as the word line 33 while forming a lower electrode 43 having an island shape connected to the contact 38. , 44b).

Here, the line width w of the lower electrode 43 and the pair of upper electrodes 44a and 44b are the same, and one of the pair of upper electrodes 44a and 44b is 43b adjacent to the pair of upper electrodes. It is also used as one. That is, one of the pair of upper electrodes is shared by neighboring capacitors.

On the other hand, since the thickness of the electrode film 40 is 100 kPa to 20000 kPa, the height h of the lower electrode 43 and the pair of upper electrodes 44a and 44b is 100 kPa to 20000 kPa and the pair of lower electrodes 43 The interval g between the upper electrodes 44a and 44b of the is adjusted according to the line width of the storage node mask, and is preferably 100 ns to 10000 ns.

As described above, when the lower electrode 43 and the pair of upper electrodes 44a and 44b are formed horizontally, the height of each electrode can be increased to the limit of the etching process, thereby increasing the capacitor capacity.

As shown in FIG. 4C, the ferroelectric film is formed on the lower electrode 43 and the pair of upper electrodes 44a and 44b to a thickness sufficiently filling the lower electrode 43 and the pair of upper electrodes 44a and 44b. After the deposition of 45, annealing for crystallization is performed.

At this time, the ferroelectric layer 45 is deposited using a metal organic deposition (MOD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or plasma atomic layer deposition (PEALD), commonly known ferroelectric Film (SBT, BLT, PZT, etc.).

On the other hand, when the ferroelectric film 45 is deposited, the lower electrode 43 and the pair of upper electrodes 44a and 44b should be deposited at a thickness of 1.5 times or more than the interval (100 to 10000 ms). These electrodes can be covered while sufficiently filling between the electrodes 44a and 44b.

Although not shown in the cross-section along the y-y 'line of FIG. 3, the ferroelectric film 45 is removed only at one end of the pair of upper electrodes 44a and 44b in a subsequent process, and a third interlayer insulating film is formed on the entire surface. Thereafter, the third interlayer insulating film is etched to form a metal wiring contact hole exposing one end of the pair of upper electrodes 44b and 44b, and the pair of upper electrodes 44b and 44b are formed through the metal wiring contact hole. The metal wiring M1 connected to is formed.

In this case, when the upper electrode is formed to have the same line width as the lower electrode, one end of the upper electrode may be widened to prevent the process wiring from becoming difficult due to the small contact hole for metal wiring.

The capacitor formed by the above-described method is always driven in pairs during operation of the device because a pair of upper electrodes disposed independently of the lower electrode is used as a plate line, and moreover, one of the pair of upper electrodes is one of the adjacent capacitors. Since it is shared by one of the pair of upper electrodes, this means that the platelines can be driven in pairs through the circuit.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the lower electrode and the upper electrode are formed in advance before the ferroelectric film is formed, thereby preventing deterioration of the ferroelectric film generated during electrode etching, thereby improving the electrical characteristics of the capacitor.

In addition, the subsequent thermal process for recovering the loss generated during excessive electrode etching may be omitted, thereby reducing the heat burden applied to the storage node contact, thereby improving the contact resistance of the storage node contact.

In addition, since the lower electrode and the upper electrode are formed at the same time, and the upper electrode is used as a plate line, the process can be simplified.

In addition, since the electric field is applied in the horizontal direction, the ferroelectric film can be aligned in the a-axis or the b-axis with a large polarization value, and the area and the spacing of the electrodes can be freely adjusted, thereby sufficiently securing the capacitance.

In addition, since the upper electrode and the lower electrode are self-aligned, the alignment margin is improved to improve the yield, various types of cell arrays can be designed, and the subsequent metallization process is easy.

Claims (12)

Lower electrode; A pair of upper electrodes arranged horizontally at predetermined intervals on both sides of the lower electrode; And A ferroelectric layer covering a gap between the lower electrode and the pair of upper electrodes and an upper portion of the lower electrode and the pair of upper electrodes, The pair of upper electrodes is ferroelectric capacitor, characterized in that also serves as a plate line. The method of claim 1, The lower electrode has an island shape, and the pair of upper electrodes have a line shape ferroelectric capacitor. The method of claim 1, And the lower electrode and the pair of upper electrodes have the same thickness. The method of claim 3, The thickness of the ferroelectric capacitor, characterized in that 100 ~ 20000 kHz. The method of claim 1, One of the pair of upper electrodes is ferroelectric capacitor, characterized in that shared with one of the adjacent pair of upper electrodes. The method of claim 1, A ferroelectric capacitor, wherein the gap between the lower electrode and the pair of upper electrodes is 100 mW to 10000 mW. The method of claim 1, A ferroelectric capacitor, characterized in that a metal wiring is connected to one end of the pair of upper electrodes. Forming an electrode film on the planarized insulating film; Selectively etching the electrode film to simultaneously form one lower electrode and a pair of upper electrodes spaced apart from the lower electrode by a predetermined distance; And Forming a ferroelectric film on the lower electrode and the pair of upper electrodes until the gap between the lower electrode and the pair of upper electrodes is completely filled. Method for producing a ferroelectric capacitor, characterized in that consisting of. The method of claim 8, The lower electrode and the pair of upper electrodes are formed in the same line width method of manufacturing a ferroelectric capacitor. The method of claim 8, And the one lower electrode is formed in an island shape, and the pair of upper electrodes are formed in a line shape. The method of claim 8, And said one lower electrode and said pair of upper electrodes are arranged horizontally at intervals of 100 mW to 10000 mW. The method of claim 8, And said one lower electrode and said pair of upper electrodes are formed to a thickness of 100 k? To 20000 k ?.