JPH0254960A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve interlayer breakdown strength by removing angular parts of a conductive layer when an insulating layer mask is provided selectively on the conductive layer and the contact region of a base layer is exposed with a self-alignment system after patterning the above conductive layer and the like and then, covering these layers with an insulating film. CONSTITUTION:A gate oxide film 22 is deposited on an Si substrate 21 to allow impurities to be contained on the above film and then, conductive polycrystal Si and W silicide layers 23 and 24 are obtained. Being composed of the above layers, conductive layers are laminated and are covered with an SiO2 layer 25 and further, a resist layer 26 having its prescribed form is provided at the surface of a center part of the layer 25. The layer 25 is etched by using the layer 26 as a mask to make the layer 25 have a prescribed size. Isotropic etching is performed to make recessed parts 27 where their angular parts are removed in a W silicide layer 24 below the layer 25 and then, a conductive polycrystal layer 23 which has the same size that the layer 24 has is left as it is below the layer 24. After that a structure laminated by a series of layers commencing from the layer 25 is covered with an SiO2 film 28. Its film is left only at both sides as SiO2 films 30 to expose the layer 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device including a step of exposing a contact region of an underlayer in a self-aligned manner.

[1 Summary of the Invention] The present invention involves selectively forming an 8i layer mask on a conductive layer, patterning the 4 conductive layer and the insulating layer mask, and covering the contact area with an insulating film. In a method of manufacturing a semiconductor device that is exposed in a self-aligned manner, this method aims to improve interlayer breakdown voltage by removing corners of a conductive layer during patterning.

[Conventional technology]

As semiconductor devices, especially DRAMs that require high integration,
A stacked capacitor type cell structure as shown in Figure 5 is known, for example, "Nikkei Electronics"
, June 3 issue, 1985.

Pages 209 to 231 (see especially FIG. 15) also describe techniques related to the structure of the DRAM.

As shown in FIG. 5, in the stacked capacitor type cell structure, a gate electrode 101 of an access transistor is formed on a silicon substrate 100 with a gate insulating film 102 interposed therebetween, and this gate electrode 101 is covered with an interlayer insulating film 103. be done. Gate electrode 101 has a polycide structure. The capacitor consists of a second layer polysilicon layer 104 and a third layer polysilicon layer 105, and the capacitor is formed from the contact region 107 of the source/drain region 106 along the stepped glabella insulating film 103. It extends to the top of the gate electrode 101.

Here, the manufacturing process will be explained with reference to FIGS. 6a and 6s. First, as shown in FIG. Gate insulation on the substrate 100! 10
2 and coated with CVD5
After the insulating film 111 made of iO□ is formed, etching is performed to open the contact regions of the source/drain regions.
This is done in a self-aligned manner using the step 01.

That is, the insulating film 111 and the insulating layer mask 110 are both etched back by RIE, and the silicon substrate 100 is etched back.
The source/drain regions 112 of are exposed.

[Problem to be solved by the invention]

However, in the method of exposing the source/drain regions 112 in a self-aligned manner, the interlayer breakdown voltage between the gate electrode 101 and the second layer of polysilicon N104 tends to deteriorate.

That is, at the upper end of the gate electrode IO1, a corner 113 is formed by patterning using anisotropic etching, as shown in FIG. The insulating film 111 covering the gate electrode 101 is
It is the thinnest at the portion 3, and as a result, the glabellar withstand voltage between it and the second polysilicon layer 104 deteriorates.

Therefore, in view of the five problems of breakdown voltage deterioration, it is an object of the present invention to provide a method for manufacturing a semiconductor device 1 that improves the breakdown voltage.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of selectively forming an insulating layer mask on a conductive layer, and selectively etching the conductive layer using the insulating layer mask. and a step of removing corners of the conductive layer;
forming an insulating film covering the sidewalls of the conductive layer and the insulating layer mask; etching the entire surface of the insulating film to form a contact formed on the base layer of the conductive layer) exposing the SM region in a self-aligned manner; and a step of forming second conductors ar, m over the insulating film to be connected to the contact region.

Here, the corner portions of the conductive layer can be removed by a combination of anisotropic etching and isotropic etching. For example, when the conductive layer has a polycide structure, the silicide layer is etched isotropically. However, the polysilicon layer can be etched anisotropically. Removal of the corner portions of the conductive layer of the polycide structure is not limited to only the silicide layer, but may involve removing part of the underlying polysilicon layer.

[Effect]

By selectively etching the conductive layer using an insulating layer mask and removing the corners of the conductive layer, the cross-sectional shape of the conductive layer becomes such that the upper corner has fallen off. Then, when the contact area is exposed in a self-aligned manner by etching the entire surface after coating with the insulating film, the distance from the surface of the insulating film is When the second conductive layer connected to the contact region is formed over the insulating film, the second The conductive layer is formed on the surface of the insulating film, and therefore the withstand voltage can be improved.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The method of manufacturing a semiconductor device of this embodiment is a method of manufacturing a DRAM having a stacked capacitor type cell structure as shown in FIG. This is a manufacturing method in which formation is performed on a selfa line.

Before explaining the manufacturing method, the structure at the time of bit line formation will be described with reference to FIG. 1 in order to clarify the manufacturing method.

As shown in FIG. 1, a field oxide film 2 and a gate oxide film 3 are formed on a silicon substrate 1, and on the gate oxide 11U3, a gate of an access transistor is formed in a pattern whose extension direction is perpendicular to the figure. Electrocution (word line)
is formed. This gate electrode has a polycide structure, with the lower layer being a polysilicon layer 4 and the upper layer being a tungsten silicide layer 5. Note that the field oxide film 2
The upper gate electrode becomes the word line for the adjacent cell.

These tungsten silicides N5 have their upper corners removed to form depressions 14 by a process to be described later. These tungsten silicide layers 5 are covered with interlayer insulation [Q6].

A contact region 8 is formed on one side of the source/drain region 7 of the access transistor formed on the surface of the silicon substrate 10, and is exposed by etching the interlayer insulating film 6 in a self-aligned manner. This contact to be a cell structure? +'J4 area 8
tungsten silicide layer 5 along the interlayer insulating film 6 from
A second polysilicon layer 9 is formed in a pattern extending to the top of the polysilicon layer 9 . This second layer of polysilicon
1J9 is the lower electrode of the capacitor, and the upper electrode of the capacitor is the third polysilicon layer 10 provided through the insulating film 11. A glabellar insulating film 12 is also formed on the third polysilicon layer 10, and a bit line 13 connected to the other source/drain region 7 of the access transistor is formed on the glabellar insulating film 12. .

Next, a manufacturing method for obtaining such a structure will be explained with reference to FIGS. 2a to 2d. In addition, the second
Figures a to 2d each show a portion of an access transistor.

First, as shown in FIG. 2a, a gate oxide film 22 is formed on a silicon substrate 21, and a polysilicon layer (DOPO3) 23.
A tungsten silicide layer 24 is laminated. These polysilicon layer 23 and tungsten silicide layer 24 function as a conductive layer of a polycide structure. A silicon oxide layer 25 serving as an insulating film mask is formed on the polysilicon layer 23 and tungsten silicide layer 24. On this silicon oxide layer 25, a silicon oxide layer 2
A resist film 26 for patterning 5 is formed and selectively exposed.

Next, silicon oxide N25 is patterned using the resist film 26 as a mask. The resist film 26 is removed, and selective etching is performed using the patterned silicon oxide layer 25 as a mask. At this time, isotropic etching is first performed to remove the tungsten silicide layer 24.
Remove the corners. When the isotropic etching using the silicon oxide 125 as a mask progresses and the polysilicon layer 23 is exposed, anisotropic etching is performed this time. CCe4 +SFh is used as a gas for etching the tungsten silicide 7124 in the same direction. Further, as the gas for anisotropically etching the polysilicon layer 23, CCl
There is 4+Ot +Hz. Then, as shown in FIG. 2, a tungsten silicide layer 24 is obtained in which the corners of the lower part of the silicon oxide layer 25 are removed and depressions 27 are formed in an isotropic shape at the edges. A polysilicon layer 23 having a shape reflecting the pattern is obtained.

As a means to obtain such a shape in which the corners of the conductive layer are removed, anisotropic etching is first performed using the silicon oxide layer 25 as a mask, buttering is performed up to the polysilicon layer 23, and then the upper tungsten layer is patterned. Silicide layer 24
It is also possible to remove the ends isotropically. Further, isotropic etching in which the etching rate of the tungsten silicide layer 24 is higher than the etching rate of the polysilicon layer 23 may be combined with anisotropic etching. Furthermore, as shown in FIG. 3, the depression 31 may have an isotropic shape extending not only to the tungsten silicide layer 24 but also to the polysilicon layer 23.

After selective etching of such a conductive layer, e.g.
As shown by the dotted line in FIG. 2, the source/drain region 32 can be formed by the patterned conductive layer and the self-line.

Next, as shown in FIG. 2C, a solicon oxide film 28 as an insulating film is formed on the entire surface using the tungsten silicide I! 2
4 and the side walls of polysilicon I'1i23 and the silicon oxide layer 25 serving as an insulating film mask. This silicon oxide film 28 also fills the depression 27 and is formed by, for example, the CVD method.

Then, as shown in FIG. 2d, the silicon oxide film 2
8 and the silicon oxide layer 25 are etched over the entire surface by RIE method. Then, the contact regions 29 formed in the source/drain regions, which are the underlying layers of the conductive layer, are exposed in a self-aligned manner. Side mail portions 30 are formed on the side walls of the tungsten silicide layer 24 and the polysilicon layer 23.

Next, a second polysilicon layer (corresponding to reference numeral 9 in FIG. 1) serving as a second conductive layer is connected to the exposed contact region 29. This second polysilicon layer functions as the lower electrode of the capacitor. This second polysilicon layer is the etched silicon oxide layer 25. It is formed over the sidewall portion 30.

In the semiconductor device manufacturing method of this embodiment, since the corners of the conductive layer are removed, the removed depressions 2
At a portion 7.31, the thickness Po of the insulating film shown in FIG. 2d becomes thicker. Therefore, its withstand voltage is improved. Furthermore, since the corners of the conductive layer are removed and the isogonal depressions 27 are formed, there are no protruding parts, and the electric field that is concentrated at the corners due to the shape is relieved. Therefore, sufficient breakdown voltage can be easily obtained.

In addition, in the method for manufacturing a semiconductor device of this embodiment, the ring 7
One layer was a polycide structure consisting of a tungsten silicide layer and a polysilicon layer, but other materials were used.

It is also possible to implement the conductive layer of the structure.

Second Embodiment This embodiment is a modification of the first embodiment, and similarly to the first embodiment, the DR has a stacked capacitor type cell structure.
This is a manufacturing method for an AM in which contact regions for source/drain regions of access transistors are formed using self-fins. Further, the structure of the DRAM manufactured according to this embodiment is similar to the structure shown in FIG. 1 when the bit lines are formed, and the explanation of the structure will be omitted because it is an hour wheel.

The steps corresponding to FIGS. 2a to 2d of the first embodiment will be explained with reference to FIGS. 4a to 4e.

First, as shown in FIG. 4A, a gate oxide film 42 is formed on a silicon substrate 41, and a polysilicon layer (DOPO3) 43.
A tungsten silicide layer 44 is laminated. These polysilicon layer 43 and tungsten silicide layer 44 function as a conductive layer of a polycide structure. A silicon oxide layer 45 serving as an insulating layer mask is formed on the polysilicon layer 43 and the tungsten silicide layer 44 .

A resist film for patterning the silicon oxide layer 45 is formed on the silicon oxide layer 45 and selectively exposed. Then, as shown in FIG. 4, the silicon oxide layer 45 is patterned using the pattern of the resist film.
The resist film is stripped off, and then its silicon oxide layer 4 is removed.
The tungsten silicide layer 44 and the polysilicon N43 are patterned in the pattern No.5. These selective etchings are performed, for example, by RIE.

Further, at this point, as shown by dotted lines in the figure, ion implantation may be performed to form source/drain regions.

Next, as shown in FIG. 4C, isotropic etching is performed using the oxide film as a mask to form the tungsten silicide layer 4.
The sidewalls of the conductive layer including the corners of No. 4 are set back. This etching causes the silicon oxide layer 45. The tungsten silicide layer 44 and the polysilicon layer 43 are formed into an overhang shape from which the silicon oxide layer 45 protrudes.

Next, as shown in FIG. 4d, a silicon oxide film 46 as an insulating film is deposited on the entire surface. This silicon oxide film 4
6 can be formed with sufficient coverage even in the above-mentioned overhang shape by LP-CVD at a high temperature of approximately 700° C. using, for example, TE01.

Next, as shown in FIG. 4e, the silicon oxide film 46 is
The entire surface of the silicon oxide layer 45 is etched using the RIE method. Then, the contact regions 47 formed in the source/drain regions, which are the underlying layers of the conductive layer, are exposed in a self-aligned manner. Sidewall portions 48 are formed on the sidewalls of the tungsten silicide layer 44 and polysilicon layer 43.

Next, as in the first embodiment, a second polysilicon layer functioning as the lower electrode of the capacitor is made of silicon oxide N45. It is formed over the sidewall portion 48. The shape of the capacitor is similar to that shown in FIG.

As described above, also in the method of manufacturing the semiconductor device of this embodiment, the distance between the eyebrows of the second polysilicon layer and the conductive layer such as the tungsten silicide layer 44 can be increased. Therefore, deterioration of the interlayer breakdown voltage is prevented.

Each of the above-mentioned embodiments is a DRAM with a stacked capacitor type cell structure, and the manufacturing method is described in which the contact regions of the source and drain regions of the access transistor are formed in the self-alignment line, but the manufacturing method is not limited to this. The present invention can be applied to all semiconductor device manufacturing methods including a process in which an insulating film on a conductive layer is etched in a self-aligned manner, and the second conductive layer is not limited to a capacitor, but can also be used for wiring. It may also be a layer or other material layer.

[Effects of the Invention] The method for manufacturing a semiconductor device of the present invention selectively etches the conductive layer using an insulating layer mask, and in order to remove the corners of the conductive layer, the entire covered insulating film is etched. Even if the contact area is exposed in a self-aligned manner, the glabellar withstand pressure will not deteriorate. Therefore, the yield can be improved, and the number of additional processes can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part showing the structure of a DRAM manufactured by an example of the semiconductor device manufacturing method of the present invention, and FIGS. 2a to 2d are examples of the semiconductor device manufacturing method of the present invention. FIG. 3 is a cross-sectional view of a main part of the process for explaining the process according to the process, and FIG. 3 is a cross-sectional view of a main part showing an example in which the shape of corner removal is changed in an example of the method of manufacturing a semiconductor device of the present invention. Further, FIGS. 4a to 4e are cross-sectional views of main steps for explaining another example of the method of manufacturing a semiconductor device according to the present invention according to the steps, and FIG. 5 is a cross-sectional view of a typical stacked capacitor type. FIGS. 6A and 6B are cross-sectional views of main parts of the structure of a DRAM having the above cell structure, respectively, for explaining an example of a conventional method for manufacturing a DRAM having the above cell structure. 23.43...Polysilicon layer 44...Tungsten silicide layer 45...Silicon oxide layer 28°46...Silicon oxide film

Claims (1)

[Claims] A step of selectively forming an insulating layer mask on the conductive layer; and a step of selectively etching the conductive layer using the insulating layer mask and removing corners of the conductive layer. forming an insulating film covering the sidewalls of the conductive layer and the insulating layer mask; and etching the entire surface of the insulating film to expose a contact region formed in the base layer of the conductive layer in a self-aligned manner. A method for manufacturing a semiconductor device, comprising the steps of: forming a second conductive layer over the insulating film to be connected to the contact region.