JPH0379072A - Semiconductor memory device and manufacturing method - Google Patents

Abstract

PURPOSE:To enable the formation of a large capacitor in a small formation area on a substrate by forming an etching stopper film which has a first etching rate and a second etching rate on the surfaces of a third insulation film which includes the side of an opening and a first semiconductor region, and carrying out anisotropic etching suitable to each etching rate. CONSTITUTION:A silicon nitriding film 9 is formed on the surfaces of a silicon oxidizing film 7 which includes the side of an opening section 8 and the source diffusion layer 5 on the bottom of the opening section 8. After a polycrystal silicon layer 10 is deposited on the silicon nitriding film 9, a second layer silicon nitriding film 11 is formed on this polycrystal silicon layer 10. Then, anisotropic etching is carried out so as to eliminate the silicon nitriding film 11 but the film on the side of the opening section 8 is excluded and different anisotropic etching is further carried out so as to eliminate the polysilicon layer 10 but the layer on the bottom of the opening section 8 is excluded. Then, similar anisotropic etching is further carried out so as to eliminate the silicon nitriding film 9 but the film on the side of the opening section 8 is excluded. It is, therefore, possible to increase the surface area of the electrode and form a large capacitor by turning the region of the capacitor into pleated waves in this manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a capacitor in a semiconductor memory device, particularly a memory cell of a dynamic RAM, and a method for manufacturing the same.

(Prior Art) As dynamic RAMs (hereinafter referred to as DRAMs) become highly integrated, the area occupied by capacitors in memory cells is restricted and becomes smaller and smaller. However, in order to prevent soft errors caused by α rays, it is necessary to ensure sufficient capacitance within this limited area.

FIG. 3 is a sectional view showing the structure of a conventional DRAM. P
Type silicon substrate 2! A gate oxidation WA 23 and a gate electrode 24 are formed on a substrate separated by an element isolation region 22 formed on the substrate, and a memory structure is formed with an N1 type source diffusion layer 25 and a drain diffusion layer 2G on the substrate surface on both sides. A cell MOS transistor 27 is formed.

An opening 29 through which the surface of the source diffusion layer 25 is exposed is formed in the interlayer insulating film 28 covering the MOS transistor 27, and a capacitor is formed using this portion. The second capacitor has an opening z9 to increase its surface area.
A protruding side wall @30 is formed to extend from the side wall surface. As a result, one capacitor electrode 31 is formed to cover the surface of the sidewall film 30 and the source diffusion layer 25 from above the interlayer insulating film 28 around the opening 29, and the other capacitor electrode 33 is formed with the oxide film 32 for the capacitor in between. It is formed. Furthermore, a metal wiring 35 is formed in the upper layer via an interlayer insulating film 34, and is connected to the drain diffusion layer 2B of the MOS transistor 17 through a contact hole 3B in an interlayer insulating film 1184.

In this way, the capacitor electrode is formed in a relatively small area on the substrate surface so as to have as large a capacitance as possible. A part of the process for manufacturing this capacitor is shown in Figure 4 (
This will be explained with reference to the cross-sectional views in a) and (b). First, M.O.
A silicon nitride film 41 is formed by low pressure CVD or the like on the entire surface of the interlayer insulating film 28 having a thickness of about 7,000 0, in which the opening 29 through which the surface of the source diffusion layer 25 of the S transistor 27 is exposed is formed.

After that, RI E (reacNve Jon etc.
Anisotropic etching is performed using the hing method to remove the silicon nitride film 41, leaving it only on the side surfaces of the opening 29.
Figure 4(a)). Next, the interlayer insulating film 28 is etched with ammonium fluoride to reduce the film thickness of the interlayer insulating film 11A2g, and silicon nitride H41
so that it protrudes outside the opening (Fig. 4(b)). Thereafter, as shown in FIG. 3, the capacitor electrode 31. An oxide film 32 for a capacitor and a capacitor electrode 33 are formed.

However, when a capacitor is manufactured using this manufacturing method, a problem arises. As shown in FIG. 4(b), the interlayer insulating film 2B
In the process of etching back the interlayer insulating film 28, the etching time is set and the etching of the interlayer insulating film 28 is stopped midway through, so it is difficult to control the thickness of the interlayer insulating film 28, and it is difficult to control the thickness of the interlayer insulating film 28. There is a high possibility that the interlayer breakdown voltage between the gate electrode 27 and the gate electrode 24 will be weakened, and in the worst case, there is a risk of a short circuit.

(Problem to be Solved by the Invention) In this way, in the conventional method, etching of the interlayer insulating film is stopped midway through, so it is difficult to control the thickness of the interlayer insulating film to determine how much of the interlayer insulating film is left. The disadvantage is that the interlayer breakdown voltage with the gate electrode becomes weaker.

This invention was made in consideration of the above circumstances, and its purpose is to provide a highly reliable semiconductor memory device having a capacitor electrode with a large capacitance in a small area on a substrate. and its manufacturing method.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device of the present invention includes a semiconductor substrate of a first conductivity type, and a first insulating film for element isolation selectively formed on the substrate. a second insulating film formed on the substrate surrounded by the first insulating film; a first conductor layer selectively formed on the second insulating film; first and second semiconductor regions of a second conductivity type selectively formed on the surface of a semiconductor substrate of one conductivity type; and the first and second semiconductor regions laminated on the first conductor layer; a third insulating film provided with an opening such that the surface of the region is exposed; a convex wall protruding annularly from the inner bottom surface of the opening in the third insulating film; and a surface on the side of the convex wall. a first electrode made of a first polycrystalline semiconductor layer selectively formed on the entire inner wall surface of the opening and on the third insulating film; and an oxide film for a capacitor formed on the first electrode. , a second electrode made of a second polycrystalline semiconductor layer formed on the oxide film for the capacitor, and a fourth insulating film formed on the entire surface of the second semiconductor region except for exposed portions; and a second conductor layer formed over the entire surface including the exposed portion of the second semiconductor region.

The method for manufacturing a semiconductor memory device of the present invention includes the steps of selectively forming a first insulating film for element isolation on a semiconductor substrate of a first conductivity type, and the substrate surrounded by the first insulating film. forming a second insulating film on the second insulating film; selectively forming a first conductive layer on the second insulating film; and introducing impurities into the surface of the first conductive type semiconductor substrate. and second
selectively forming first and second semiconductor regions of conductive type; forming a third insulating film over the entire surface of the substrate including the first conductor layer; and forming a third insulating film on the third insulating film. On the other hand, a step of forming an opening such that the surfaces of the first and second semiconductor regions are exposed, and a step of forming an opening on a third insulating film including a side surface of the opening and on a surface of the first semiconductor region. forming an etching stopper film having a second etching rate on the first etching stopper film; forming a second etching stopper film having a second etching rate on the first etching stopper film; forming a convex wall forming film having a first etching rate on the second etching stopper film;
etching using an anisotropic etching technique adapted to the etching rate of the etching process, and leaving the second etching stopper film on the side surface of the opening as a sidewall; etching using a conventional etching technique, leaving this second etching stopper film at the bottom of the opening;
etching the etching stopper film using an anisotropic etching technique adapted to the first etching rate, leaving the first etching stopper film on the side surface of the opening, and etching the entire inner wall surface of the opening and selectively forming a first electrode made of a first polycrystalline semiconductor layer on a third insulating film; forming an oxide film for a capacitor on the first electrode by an oxidation method; forming a second electrode made of a second polycrystalline semiconductor layer on the oxide film for the capacitor; and forming a fourth insulating film on the entire surface of the second semiconductor region except for exposed portions. , forming a second conductor layer on the entire surface including the exposed portion of the second semiconductor region.

(Function) In the present invention, the convex wall provided in an annular manner protrudes within the opening for manufacturing the capacitor part, so that the first polycrystalline semiconductor layer is coated over the entire inner wall surface of the opening, including the surface on the convex wall side, and the third polycrystalline semiconductor layer.
By forming the first electrode of the capacitor selectively on the insulating film and making the first electrode of the capacitor a corrugated electrode, the surface area of the electrode surface is increased, thereby forming a capacitor with a large capacitance. In this capacitor manufacturing method, the first etching stopper film prevents the interlayer insulating film on the first conductor layer from being etched, so that the interlayer breakdown voltage does not decrease. Further, the first etching stopper film has a different etching rate from the second etching stopper film, and a corrugated electrode with a fine corrugated structure is manufactured using the Selfa line.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIGS. 1A to 1B are cross-sectional views showing the main steps of a method for manufacturing a memory cell in a dynamic RAM (hereinafter referred to as DRAM) according to the present invention. That is, first, a field oxide film 2 is formed on a P-type silicon substrate 1 as an element isolation region. Thereafter, a gate oxide film 3 and a gate electrode 4 are selectively formed on the surface of the substrate 1 surrounded by the field oxide film 2. Next, using the gate electrode 4 and field oxide film 2 as a mask, for example, P(
By ion-implanting phosphorus), an N+ type source diffusion layer 5 and drain diffusion layer 6 are formed.

After that, about 4000 silicon oxide films 7 are deposited on the entire surface by, for example, CVD (chemical vapor deposition), and then,
A portion of the silicon oxide film 7 on the source diffusion layer 5 is selectively etched to form an opening 8 (FIG. 1(a)).

Next, a silicon nitride film 9 with a thickness of approximately 1000 mm is deposited as an etching Q stopper film for the silicon oxide film 7 on the silicon oxide film 7 including the side surfaces of the opening 8 and on the surface of the source diffusion layer 5 at the bottom of the opening 8. It is formed by a low pressure CVD method.

After that, a polycrystalline silicon layer 10 is deposited on the silicon nitride film 9, and then a second silicon nitride film 11 is formed on this polycrystalline silicon layer 10 by about 1000 people (see FIG. 1).
b)).

Next, anisotropic etching is performed using the RIE method to remove the silicon nitride film 11, leaving it only on the side surfaces of the opening 8.

The RIE method at this time is anisotropic etching that increases the etching rate of silicon nitride gt1,
Since the etching rate of the polycrystalline silicon layer 10 is extremely low, the underlying polycrystalline silicon layer 10 is etched. The stopper acts as a polycrystalline silicon layer 10.
The end point of etching of the upper silicon nitride film 11 can be detected (FIG. 1(C)).

Next, anisotropic etching is performed using the RIE method to remove the polycrystalline silicon layer 10, leaving it only at the bottom of the opening 8. The RIE method at this time is an anisotropic etching that increases the etching rate of the polycrystalline silicon layer 10, and the etching rate of the silicon nitride films 9 and 11 is extremely low. 9 acts as an etching stopper, and the point in time when etching of the polycrystalline silicon layer lO on the silicon oxide film 9 is completed can be detected.

In this way, inside the opening 8, a silicon nitride film 111 protrudes annularly so as to surround the silicon nitride film 9 exposed on the bottom surface.
1 is formed, and a groove 12 for a capacitor is formed in a donut shape (FIG. 1(d)).

Next, anisotropic etching is performed using the RIE method similar to that shown in FIG. As a result, the source diffusion region 5 is exposed at a portion of the bottom surface of the opening 8. Thereafter, a polycrystalline silicon layer is formed over the entire inner wall surface of the opening 8 including the exposed source diffusion region 5 and on the third insulating film, and is patterned to form one capacitor electrode 13. Next, a capacitor oxide film is formed on the surface of the capacitor electrode 13! 4, the other capacitor electrode 15 is formed on the oxide film 14 for the capacitor, thereby forming the capacitor 16 (FIG. 1(e)).

Next, after depositing an interlayer insulating film over the entire surface, patterning is performed so that a part of the drain region 6 of the transistor is exposed, and a drain electrode 18 made of aluminum is formed.
Figure 1(f)).

According to such a manufacturing method, the convex wall of the silicon nitride film 11 formed in an annular manner in the opening 8 for manufacturing the capacitor part makes the region of the capacitor part have a corrugated shape, thereby forming the electrode. A capacitor with a large capacitance is formed by increasing the surface area of the surface. In addition, in manufacturing this capacitor, the capacitor region is formed by combining film materials with different etching rates, making it easy to control etching, and manufacturing microscopic corrugated corrugated electrodes on the Selfa line. be done.

Note that the combination of film materials with different etching rates is silicon nitride film (9)-polycrystalline silicon layer (10) instead of silicon nitride film 9-polycrystalline silicon layer lO-silicon nitride film 11 in this embodiment. - silicon oxide film (11) or polycrystalline silicon layer (9) - silicon nitride film (10) - polycrystalline silicon layer (11) or
It can also be realized using a combination such as a polycrystalline silicon layer (9), a silicon oxide film (lO), and a polycrystalline silicon layer (11).

In addition, the surface area of the electrode surface of the capacitor is further increased,
If it is desired to form a capacitor with a large capacity, this can be achieved by making the outer circumference of the donut-shaped groove 12 larger than that of the embodiment shown in FIG. 1, as shown in FIG. In this case, the opening 8 may be formed in the interlayer insulating film 7 in a part of the upper layer of the gate electrode 3. Therefore, for example, an etching stopper layer (Fig. It is necessary to complete the formation of the opening 8 at the position A by, for example, inserting a hole (not shown). Furthermore, when exposing the source diffusion region 5 by etching the inside surrounded by the convex wall of the silicon nitride film, an etching stopper layer (not shown) is added on the surface of the interlayer insulating film 7 other than the opening.
It is a good idea to provide

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a highly reliable semiconductor memory device having a capacitor electrode with a large capacity, and a method for manufacturing the same.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are cross-sectional views showing the main steps of a method for manufacturing a dynamic RAM memory cell according to an embodiment of the present invention, and FIG. A cross-sectional view showing the configuration of a memory cell of a dynamic RAM, FIG. 3 is a diagram of a conventional dynamic RAM.
FIGS. 4(a) and 4(b) are cross-sectional views showing a part of the manufacturing process of the memory cell having the structure shown in FIG. 3. FIGS. 1... P-type semiconductor substrate, 2... Field oxide film,
3... Gate electrode, 4... Gate oxide film, 5...
Source diffusion layer, 6... Drain diffusion layer, 7, 17...
- Interlayer insulating film, 8... Opening, 9.11... Silicon nitride film, lO... Polycrystalline silicon layer, 12... Groove, 13.15... Capacitor electrode, 14... Capacitor oxide film, 16... Capacitor, 18... Drain electrode.

Claims (2)

[Claims] (1) a semiconductor substrate of a first conductivity type; a first insulating film for element isolation selectively formed on the substrate; and a semiconductor substrate formed on the substrate surrounded by the first insulating film. a second insulating film; a first conductive layer selectively formed on the second insulating film; and a second conductive type selectively formed on the surface of the first conductive type semiconductor substrate. and a third insulating film laminated on the first conductor layer and provided with an opening through which surfaces of the first and second semiconductor regions are exposed. a convex wall provided to protrude annularly from the inner bottom surface of the opening in the third insulating film; and the entire inner wall surface of the opening including the convex wall side surface and the third insulating film.
a first electrode made of a first polycrystalline semiconductor layer selectively formed on an insulating film; an oxide film for a capacitor formed on the first electrode; and an oxide film for a capacitor formed on the oxide film for the capacitor. a second electrode made of a second polycrystalline semiconductor layer formed on the second semiconductor region; a fourth insulating film formed on the entire surface of the second semiconductor region except for exposed portions; and an exposed portion of the second semiconductor region. 1. A semiconductor memory device comprising: a second conductor layer formed over the entire surface including a portion of the semiconductor memory device. (2) selectively forming a first insulating film for element isolation on a semiconductor substrate of a first conductivity type; and forming a second insulating film on the substrate surrounded by the first insulating film. selectively forming a first conductive layer on the second insulating film; and introducing an impurity into the surface of the first conductive type semiconductor substrate to form a second conductive type. selectively forming first and second semiconductor regions; forming a third insulating film over the entire surface of the substrate including the first conductor layer; forming an opening such that the surfaces of the first and second semiconductor regions are exposed; and performing first etching on the third insulating film including the side surfaces of the opening and on the surface of the first semiconductor region. - forming an etching stopper film having a second etching rate; forming a second etching stopper film having a second etching rate on the first etching stopper film; and the second etching - forming a film for forming a convex wall having a first etching rate on the stopper film; and forming the film for forming a convex wall by an anisotropic etching technique adapted to the first etching rate. etched,
etching the second etching stopper film using an anisotropic etching technique adapted to the second etching rate; etching the first etching stopper film by an anisotropic etching technique adapted to the first etching rate; leaving the first etching stopper film at the bottom of the opening; a step of selectively forming a first electrode made of a first polycrystalline semiconductor layer over the entire inner wall surface of the opening and on the third insulating film; and a step of forming an oxidation method on the first electrode. forming a second electrode made of a second polycrystalline semiconductor layer on the oxide film for the capacitor, excluding exposed portions of the second semiconductor region; Manufacturing a semiconductor memory device comprising: forming a fourth insulating film over the entire surface; and forming a second conductor layer over the entire surface including the exposed portion of the second semiconductor region. Method.