FR2752481A1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE HAVING A SHAFT TYPE CAPACITOR - Google Patents

Abstract

The tree type capacitor which is produced by the method of the invention comprises a storage electrode having a trunk-shaped conductive layer (34a) connected to at least one branch-shaped conductive layer (28a), which may have various shapes to increase the surface area of the branch-shaped layer. The latter is formed by successively depositing on a substrate (10) at least one insulating layer and at least one conductive layer, so that the conductive layer has a series of changes in direction defining the shape of the branch-shaped layer (28 ). The trunk-like layer (34a) is formed so as to be in contact with a source / drain region (16a) of a transfer transistor of the device. A dielectric layer (36a) and a conductive covering layer (38) complete the capacitor.

Description

METHOD FOR MANUFACTURING A DEVICE

SEMICONDUCTOR MEMORY

  HAVING A TREE TYPE CAPACITOR

  The invention relates generally to metering devices.

  semiconductor memory, and more particularly relates to a structure of a dynamic random access memory (or DRAM) cell essentially constituted by a transfer transistor and a storage transistor

dump.

  Figure 1 is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a cell

  DRAM is essentially constituted by a transistor T and a conden-

  charge storage sector C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain of this transistor is connected to a storage electrode 6 of the capacitor

  charge storage C. A gate of the transfer transistor T is con-

  nected to a corresponding WL word line. An opposite electrode 8

  of capacitor C is connected to a constant voltage source.

  A dielectric film 7 is formed between the storage electrode 6 and

the opposite electrode 8.

  In the manufacturing process of a DRAM device, a two-dimensional capacitor, called a planar type capacitor, is essentially used for a conventional DRAM device having a capacity of

  storage less than 1 M (mega = million) bits. In the case of a dis-

  positive DRAM having a memory cell which uses a planar type capacitor, electrical charges are stored on the main surface of a semiconductor substrate, so that the main surface must have a relatively high area. This type of memory cell is therefore not suitable for a DRAM device having a high level of integration. For a DRAM device with a high level of integration, such as a

  DRAM device with more than 4M bits of memory, we have introduced a

  three-dimensional densifier, called a stacked type capacitor or

trench type.

  With stacked or trench type capacitors, it has

  been able to get a larger memory in a similar volume.

  However, to make a semiconductor device having an even higher level of integration, such as a very high level of integration circuit (or VLSI) having a capacity of 64M bits, a capacitor with a simple three-dimensional structure, such as the type stacked or the

  classic trench type, turns out to be insufficient.

  A solution to improve the capacity of a capacitor

  is to use what is called the stacked capacitor type ai-

  lettes, which is proposed by Ema et al. in "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electron Devices Meeting, pages 592-595, December 1988. The stacked fin type capacitor includes electrodes and dielectric films which extend in a fin in a set of stacked layers. DRAM devices having the finned type stacked capacitor are also described in U.S. patents. No. 5,071,783 (Taguchi et al); 5,126,810 (Gotou); 5,196,365 (Gotou); and 5,206,787 (Fujioka). Another solution to improve the capacitance of a capacitor

  is to use what is called the stacked capacitor of cy- type

  lindrique, which is proposed by Wakamiya et al. in "Novel Stacked Ca-

  pacitor Cell for 64-Mb DRAM ", 1989, Symposium on VLSI Technology, Digest of Technical Papers, pages 69-70. The stacked cylindrical type capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. A DRAM device having the stacked capacitor of the cylindrical type is also described in US Pat. No. 5

077 688 (Kumanoya et al.).

  With the trend towards increased integration density, it is born

  stop further reducing the size of a DRAM cell in a plane (that is, the area it occupies in a plane). Generally speaking, a reduction in cell size leads to a reduction

  load storage capacity (electrical capacity). In addition, when

  that the electrical capacity is reduced, the probability of transient errors

  resulting from the incidence of c-rays is increased. There are therefore all

  days a need in this technique relating to the design of a new storage capacitor structure, which makes it possible to obtain the same electrical capacity, while occupying a smaller area in a

  plan, as well as on a suitable process for manufacturing the structure.

  An object of the invention is therefore to provide a method for fa-

  brick a semiconductor memory device that includes a

  tree type densifier providing increased area for

charge storage.

  In accordance with the foregoing object, as well as others, the invention provides a new and improved method for manufacturing a device

semiconductor memory.

  The invention provides a method for manufacturing a device for

  semiconductor memory. The semiconductor memory device

  The sensors include a substrate, a transfer transistor having source / drain regions, formed on the substrate, and a charge storage capacitor which is electrically connected to one of the regions of

  source / drain. In accordance with the process, a pre-

  first insulating layer on the substrate, so that it covers the tran

  transfer sistor. An insulating pillar is then formed on the first layer.

  insulating che, the insulating pillar defining regions of cavities on both sides and

  else of himself. A first film is then formed alternately.

  insulating material and a second film of insulating material on the first insulating layer, in a cavity region and on the pillar

  insulating. Then remove a selected part of the second film

  cule which extends above the insulating pillar, and a first conductive layer is formed which penetrates at least through the second film,

  the first film and the first insulating layer, so as to be

  electrically connected to one of the source / drain regions. The first conductive layer and the second film thus form in combination a storage electrode of the charge storage capacitor. Then remove the insulating pillar and the first film. We form a

  dielectric layer on bare surfaces of the first layer

  conductive and the second film, and a second layer is formed

  conductive on the dielectric layer. The second conductive layer thus fulfills the function of an opposite electrode of the charge storage capacitor.

  A semiconductor memory device in accordance with the

  vention is therefore formed so as to include a tree type capacitor having an increased area in order to be able to store reliably on this capacitor electrical charges representative of data. In

  varying the number of conductive layers during manufacture

  those that are formed, by being intertwined with insulating layers,

  the total surface area of the capacitor electrodes can be defined.

  You can also vary the size, shape and placement of the insulating pillar as well as the size, shape and structure of the second conductive layer, to change the shape of the type capacitor into a tree.

  to meet specific design needs.

  Other characteristics and advantages of the invention will be

  better understood on reading the detailed description which follows

  embodiments, given by way of nonlimiting examples. Following

  the description refers to the accompanying drawings, in which:

  Figure 1 is a circuit diagram of a memory cell of a DRAM device;

  FIGS. 2A to 2G are sections which are intended for ex-

  plicate a first embodiment of a semi-memory cell

  conductors having a tree type capacitor according to the invention

  tion, and a method for its manufacture according to the invention;

  FIGS. 3A to 3D are sections which are intended for ex-

  plique a second embodiment of a semi-memory cell

  conductors having a tree type capacitor according to the invention

  tion, and a method for its manufacture according to the invention; FIGS. 4A and 4B are sections intended to explain a

  third embodiment of a semiconductor memory cell

  teurs having a tree type capacitor according to the invention, and a method for its manufacture according to the invention; FIGS. 5A to 5D are sections intended to explain a

  fourth embodiment of a semiconductor memory cell

  teurs having a tree type capacitor according to the invention, and a method for its manufacture according to the invention; FIGS. 6A and 6B are sections intended to explain a fifth embodiment of a semiconductor memory cell having a tree type capacitor according to the invention, and a method for its production according to the invention ; FIGS. 7A and 7B are sections intended to explain a sixth embodiment of a semiconductor memory cell having a tree type capacitor according to the invention, and a method for its production according to the invention; FIGS. 8A to 8F are sections intended to explain a

  seventh embodiment of a semiconductor memory cell

  teurs having a tree type capacitor according to the invention, and a method for its manufacture according to the invention; FIGS. 9A to 9D are sections intended to explain an eighth embodiment of a semiconductor memory cell having a tree type capacitor according to the invention, and a method for its production according to the invention; and Figures 10A to 10D are sections intended to explain

  a ninth embodiment of a semicon memory cell

  ductors having a tree type capacitor according to the invention,

  and a process for its production according to the invention.

  First preferred embodiment

  We will present a description of a first embodiment

  tion of a semiconductor memory device having a tree type charge storage capacitor according to the invention, with reference to FIGS. 2A to 2G. This embodiment of the semiconductor memory device can be produced by a first preferred method for manufacturing a semiconductor memory device in accordance with

to the invention.

  Referring to Figure 2A, we note that we apply a

  thermal oxidation by the LOCOS technique (local oxidation of sili-

  cium) on a surface of a silicon substrate 10, which has the effect of forming a field oxide film 12 having a thickness which is for example about 300 nm. Then a film of oxide of

  grid 14 having a thickness of about 15 nm, for example, subjecting it to

  both the silicon substrate 10 to the thermal oxidation treatment. We

  then deposits on the entire upper surface of the silicon substrate

  cium 10 a polycrystalline silicon film having a thickness of

  about 200 nm, using the chemical phase deposition process

  fear, or CVD, or low pressure chemical vapor deposition (or LPCVD). To obtain a low polycrystalline silicon film

  resistance, impurities are diffused into the polycrystalline silicon film

  suitable reagents, such as for example phosphorus ions. Wave-

  preferably places a layer of refractory metal on the polycrystalline silicon film, and then preferably an annealing treatment is carried out to form a material of the polycrystalline silicon / silicide type, so as to further reduce the resistance of the film. The refractory metal can be tungsten (W), and its thickness is

  example of about 200 nm. The polycrystalline silicon is then subjected

  linen / silicide to a pattern formation process to form electrons

  grid trodes (or word lines) WL1 to WL4, as shown in FIG. 2A. Then, for example, arsenic ions are diffused into the

  silicon substrate 10, at an energy of 70 keV, to obtain a con-

  centering in impurities which is for example about 1 x 1015 atoms / cm2. In this step, the word lines WL1 to WL4 are used as mask films. Drain regions 16a and 16b and regions of

  source 18a and 18b are thus formed in the silicon substrate 10.

  Referring next to FIG. 2B, it is noted that in the next step

  We use the CVD process to deposit an insulating leveling layer 20, consisting for example of borophosphosilicate glass.

  (or BPSG), up to a thickness which is for example around 700 nm.

  The same process is then used to form a layer of protection against attack 22, which can for example be a layer of silicon nitride, having for example a thickness of approximately 100 nm. After this, a thick insulating layer is deposited on the wafer, consisting for example of silicon dioxide, having a thickness which is for example

  about 700 nm. Then we use conventional photo-

  lithography and etching to define an insulating pillar 24 bounded by cavities 23. Although FIG. 2B shows the insulating pillar 24 in a number of separate locations, the insulating pillar 24 is actually a

  integrated element which is visible when viewed from above.

  Referring next to FIG. 2C, it is noted that in the next step

  We use the CVD process to successively form a first insulating layer 26, a polycrystalline silicon layer 28 and a second insulating layer 30. The first and second insulating layers

  26, 30 preferably consist of silicon oxide. Each of the cou-

  ches comprising the first insulating layer 26 and the polycrystalline silicon layer 28 is deposited with a thickness which is for example about 100 nm, and the second insulating layer 30 is deposited with

  a thickness which is for example around 700 nm. We can diffuse

  ser arsenic (As) ions in the polycrystalline silicon layer 28,

  so as to increase its conductivity.

  Referring next to Figure 2D, we note that in the next step

  In this case, a chemo-mechanical polishing (or CMP) is performed on the surface of the wafer of FIG. 2C, until an upper part of the

  polycrystalline silicon layer 28 is removed by polishing. The par-

  remaining part of the polycrystalline silicon layer 28 comprises a certain number of separate sections which are designated by the references 28a,

28b shown in Figure 2D.

  Referring next to FIG. 2E, it is noted that conventional photolithography and etching treatments are then carried out for

  selectively attacking, in succession, the insulating layer 30, the dry

  polycrystalline silicon layer 28a and 28b, and the insulating layer 26, the protective layer against attack 22, the insulating layer 20 and the grid oxide film 14. As a result, contact holes of storage electrode 32a and 32b are formed. The storage electrode contact holes 32a and 32b extend respectively from an upper surface of the insulating layer 30 to a surface

  upper drain regions 16a and 16b. Then a film is deposited.

  polycrystalline silicon cule and its thickness is reduced by etching to fill the contact holes of storage electrode 32a and 32b with

  polycrystalline silicon layers 34a and 34b.

  Referring next to FIG. 2F, it is noted that in the next step

  In order to carry out a wet attack operation on the wafer, with the protective layer against attack 22 as the end point of the attack, so as to remove the insulating layers 26, 30 and the insulating pillar 24. The remaining polycrystalline silicon layers, 34a, 34b, in the form of a tree trunk, and the branched polycrystalline silicon layers 28a, 28b, in combination form a tree-type storage electrode for the device capacitor. DRAM. The trunk-shaped polycrystalline silicon layers 34a, 34b are respectively

  electrically connected to the drain regions 16a and 16b of the transistors

  transfer tors in the DRAM device. Each of the silicon layers

  polycrystalline branch-shaped cium 28a, 28b has substantially an L-shaped cross-section, and these layers have substantially cross-section

  horizontal in electrical contact with the polycrystalline silicon layers

  tallin in the shape of a trunk 34a, 34b. With this particular shape, the elect

  storage trodes are called in the rest of this description of

  "tree-shaped storage electrodes", and the capacitors as well

  manufactured are called "tree type capacitors".

  Referring next to FIG. 2G, it is noted that in the next step

  In particular, dielectric films 36a, 36b are formed on the tree-shaped storage electrode (34a, 28a) and on the tree-shaped storage electrode (34b, 28b), respectively. Dielectric films 36a,

  36b can consist for example of silicon dioxide, silicon nitride

  cium, NO (silicon nitride / silicon dioxide), ONO (silicon dioxide)

  cium / silicon nitride / silicon dioxide), or others. Then we train

  on the dielectric films 36a, 36b an opposite electrode 38 if

  polycrystalline silicon, which faces the storage electrodes (34a, 28a) and (34b, 28b). The process for the formation of the opposite electrode 38

  includes a first step consisting in depositing a layer of silicon

  polycrystalline cium, by the CVD process, to a thickness which is

  example of around 100 nm, a second step which consists in diffusing

  ser N-type impurities in the polycrystalline silicon layer,

  so as to increase its conductivity, and a final step which consists in using

  read conventional photolithography and etching treatments to remove by attack selected parts of the polycrystalline silicon layer. The manufacture of tree type capacitors in the

  DRAM device is thus finished.

  To complete the manufacturing of the DRAM chip, the steps

  following include the manufacturing of bit lines, measurement ranges

  nxion, interconnections and passivations, as well as the condition-

  is lying. These steps only involve conventional techniques and they do not enter into the spirit and the scope of the invention, which means that

  a detailed description will not be presented here.

  Second preferred embodiment In the first preceding embodiment, the tree-type capacitor which is described has only one electrode in the form of a branch. The number of branches is not limited to

  one, and it can be two or more. In what follows, it is described with reference to

  in FIGS. 3A to 3D a second embodiment of the capacitor

  tree type, which includes two branches of electrodes. The conden-

  The tree type sator of the second embodiment is based on the slice structure of FIG. 2B. The elements in FIGS. 3A to

  3D which are identical to those of FIG. 2B are designated by the same-

my digital references.

  Referring to FIG. 3A in conjunction with FIG. 2B, it is noted that the CVD method is used to successively form alternating layers of insulator and polycrystalline silicon, comprising a

  first insulating layer 40, a first layer of polycrystalline silicon

  linen 42, a second insulating layer 44, a second layer of silicon

  polycrystalline 46 and a third insulating layer 48. The iso-

  lantes 40, 44, 48 are preferably formed for example of silicon oxide. Each of the layers comprising the insulating layers 40, 44 and the polycrystalline silicon layers 42, 46 is deposited with a thickness which is for example around 100 nm, and the insulating layer 48

  is deposited with a thickness which is for example around 700 nm.

  Arsenic (As) ions can be diffused into the silicon layers.

  polycrystalline cium 42, 46, so as to increase their conductivity.

  Referring next to FIG. 3B, it is noted that in the next step

  We apply the chemo-mechanical polishing technique to the over-

  face of the wafer which is represented in FIG. 3A, so as to remove

  worm by polishing an upper part of the poly-

  crystalline 42, 46. The remaining part of the polycrystalline silicon layers

  42, 46 includes a number of separate sections which are desi-

  indicated by the references 42a, 46a and 42b, 46b.

  Referring next to FIG. 3C, it is noted that in the next step

  In particular, conventional photolithography and etching treatments are used to form storage electrode contact holes which extend from the upper surface of the insulating layer 48 (see

  Figure 3B) to the surface of the drain regions 16a and 16b. We rem-

  then fold the storage electrode contact holes with

  polycrystalline silicon plates 50a, 50b, first using the process

  CVD die to deposit a polycrystalline silicon layer, and then by etching away part of the thickness of the silicon layer

  polycrystalline. We then apply an edge attack to the wafer.

  mide, with the protective layer against attack 22 to define the end point of the attack, so as to remove the insulating layers 40, 44, 48 and the insulating pillar 24. The layers of trunk-shaped polycrystalline silicon 50a , 50b remaining and the branch-shaped polycrystalline silicon layers 42a, 46a and 42b, 46b form in combination two

  tree-shaped storage electrodes. Poly- silicon layers

  trunk-shaped lens 50a, 50b are respectively connected

  electrically to the drain regions 16a and 16b of the transistors

  fert in the DRAM device. Each of the polycrystallized silicon layers

  tallin branch-shaped 42a, 46a and 42b and 46b has practically an L-shaped cross section, and these layers have sections practically

  which are in contact with the layers of polycrystalline silicon

trunk-shaped linen 50a, 50b.

  Referring next to FIG. 3D, it is noted that in the next step

  dielectric films 52a, 52b are formed respectively on the tree-shaped storage electrodes (50a, 46a, 42a) and (50b, 46b

  and 42b). Next, an opposite electrode 54 is formed, made of poly-

  crystalline, on the dielectric films 52a, 52b. The process for the formation of the opposite electrode 54 comprises a first step which consists in depositing a layer of polycrystalline silicon by the CVD process, a second step which consists in diffusing N-type impurities in the layer of polycrystalline silicon, so as to increase its conductivity, and a final step which consists in using conventional photolithography and etching treatments to remove by etching

  a selected part of the polycrystalline silicon layer. After this-

  Ci, the fabrication of the tree type capacitors in the DRAM device is completed. Third Preferred Embodiment In the first and second embodiments above, the lowest layer of the branched portion of the tree-shaped storage electrode is separated from the attack protective layer 22 The invention is however not limited to such a structure. In the following, with reference to FIGS. 4A and 4B, a third embodiment of the invention is described, in which the lowest layer of the branch-shaped part of each tree-shaped storage electrode is in contact with the protective layer

against attack 22.

  The tree type capacitors of the third embodiment

  They are also based on the structure of Figure 2B. The ele-

  ment in FIGS. 4A and 4B which are identical to those in FIG. 2B

  are designated by the same reference numerals.

  Referring first to Figure 4A, together with the

  FIG. 2B, it is noted that the CVD process is used to form successively

  of alternating layers of insulation and polycrystalline silicon, including

  taking a first layer of polycrystalline silicon 60, a first insulating layer 62, a second layer of polycrystalline silicon 64 and

a second insulating layer 66.

  Referring next to FIG. 4B, it is noted that in the next step

  We apply the chemo-mechanical polishing technique to the over-

  face of the wafer which is represented in FIG. 4A, so as to remove

  worm by polishing an upper part of the poly-

  crystalline 60, 64. The remaining parts of the polycrystalline silicon layers

  tallin 60, 64 include a number of separate sections which

  are designated by the references 60a, 64a and 60b, 64b. We use in-

  continuation of conventional photolithography and etching treatments to form storage electrode contact holes. We then fill

  the storage electrode contact holes with silicon layers

  polycrystalline cium 68a, 68b. After this, an attack operation is carried out.

  wet only on the wafer, with the protective layer against

  attack 22 for the end point of the attack, so as to remove the

insulating shields 62, 66.

  The remaining polycrystalline silicon layers 68a, 68b, in

  trunk-shaped, and the polycrystalline silicon layers in the shape of a branch

  che 60a, 64a and 60b, 64b form in combination two tree-shaped storage electrodes. The trunk-shaped polycrystalline silicon layers 68a, 68b are respectively electrically connected

  to the drain regions 16a and 16b of the transfer transistor in the device

  DRAM. Each of the branch-shaped polycrystalline silicon layers 60a, 64a and 60b, 64b has a substantially L-shaped cross section, and these layers have substantially horizontal sections which are in contact with the trunk-shaped polycrystalline silicon layers 68a, 68b . In this embodiment, the polycrystalline silicon layers

  in the form of a branch 60a, 60b of the storage electrodes in the form of a

  bre are in contact with the protective layer against attack 22. On

  can now form a dielectric film and an oppo-

  polycrystalline silicon, as described above for the pre-

  mier and second embodiments. After this, the manufacture of the con-

  tree type densifiers in the DRAM device is completed.

  Fourth Preferred Embodiment In the previous three embodiments, the trunk-shaped portion of the tree-shaped storage electrode of each tree-type capacitor is a semiconductor element formed of a

  in one piece. The invention is however not limited to such a structure.

  In what follows, with reference to FIGS. 5A to 5D, a description is given of

  third embodiment in which the trunk-like part of

* each tree-shaped storage electrode is made up of a

  seems of semiconductor elements.

  The tree type capacitor of the fourth embodiment

  sation is also based on the structure of Figure 2A. The elements in FIGS. 5A to 5D which are identical to those in FIG. 2A are

  designated by the same reference numerals.

  Referring first to FIG. 5A, together with FIG. 2A, it is noted that the CVD process is used to deposit on the wafer an insulating leveling layer 70, consisting for example of borophosphosilicate glass. The same method is then used to deposit a layer of protection against attack 72, consisting for example of silicon nitride. After this, conventional photolithography and etching treatments are used to attack selected parts of the attack protection layer 72 and the insulating leveling layer 70, so as to form electrode contact holes. storage 76a, 76b, which extend from the upper surface of the attack protection layer 72 to the upper surface of the drain regions 16a and 16b. We then use

  the CVD process for depositing on the wafer a layer of poly-

  lens which fills the contact holes of storage electrode 76a,

  76b. Impurities can be diffused into the silicon layer for

  lycrystalline, so as to increase its conductivity. We then use conventional photolithography and etching treatments to define

  T-shaped elements, 74a, 74b, so as to form lower parts

  respective res of the charge storage electrodes of capacitors

  for memory cells in the DRAM device.

  Referring next to FIG. 5B, it is noted that in the next step

  Vante a thick insulating layer is deposited on the wafer, consisting for example of silicon dioxide. Conventional photolithography and etching treatments are then used to remove by attack selected parts of the insulating layer, so as to form pillars

  insulators 78. The CVD process is then used to form successively-

  a first insulating layer 80, a layer of polycrystalline silicon

  tallin 82 and a second insulating layer 84.

  Referring next to FIG. 5C, it is noted that in the next step

  We apply the chemo-mechanical polishing technique to the over-

  face of the wafer which is represented in FIG. 5B, so as to remove

  worm by polishing an upper part of the poly-

  lens 82. The remaining part of the polycrystalline silicon layer 82 comprises a number of separate sections which are designated by

references 82a, 82b.

  Referring next to FIG. 5D, it is noted that in the next step

  We use classic photolithography and atmospheric treatments.

  plate to successively remove by attack selected parts of the second insulating layer 84, polycrystalline silicon layers 82a, 82b and the first insulating layer 80, so as to form contact holes which extend from the upper surface from the insulating layer 84 to the upper surface of the T-shaped elements 74a, 74b of the tree-shaped storage electrodes. The contact holes are then filled with polycrystalline silicon, so as to form upper parts 86a, 86b of the storage electrodes.

  tree shape. The process for filling the contact holes with the sili-

  polycrystalline cium comprises a first step which consists in depositing a layer of polycrystalline silicon by the CVD process, and a second

  step which consists in reducing the thickness of this layer, by attack.

  After this, a wet attack operation is carried out on the edge, with the attack protection layer 72 to define the end point of the attack, so as to remove the insulating layers 84, 80

  and the insulating pillar 78. This completes the manufacture of the stock electrodes.

  age of the tree type capacitors in the DRAM device. The

  embodiment differs from that of FIG. 2F by the fact that each

  each of the storage electrodes additionally comprises a practical section

  which is horizontal and extends from the T-shaped elements 74a,

  74b, at the bottom. We can now form a thin film

  electric and an opposite polycrystalline silicon electrode, as

  previously written for the first, second and third embodiments

  station. After this, the manufacture of the tree type capacitors

  in the DRAM device is completed.

  Fifth preferred embodiment In the previous four embodiments, the portion in

  trunk shape of the tree-shaped storage electrode is an ele

  full semiconductor. The invention is however not limited to a

  such structure. The following description presents, with reference to the fig-

  res 6A and 6B, a fifth embodiment in which the trunk-shaped portion of each tree-shaped storage electrode is

dig.

  The tree type capacitor of the fifth embodiment

  sation is based on the structure of Figure 2D. The elements of FIGS. 6A and 6B which are identical to those of FIG. 2D are designated by the

same reference numbers.

  Referring first to Figure 6A, together with the

  Figure 2D, we note that after the manufacturing has reached the represented stage

  felt in Figure 2D, we use conventional photoli-

  thography and attack to remove by attack selected parts-

  born from the insulating layer 30, the branch-shaped polycrystalline silicon layer 28a, 28b, the insulating layer 26, the attack protection layer 22, the insulating leveling layer 20 and the film of gate oxide 14, so as to form storage electrode contact holes 87a, 87b which extend from the

  upper surface of the insulating layer 30 up to the upper surfaces

  res of the drain regions 16a and 16b. Then, we use the CVD process to deposit a layer of polycrystalline silicon, so that the

  polycrystalline silicon layer is formed only on the inner walls

  of the storage electrode contact holes 87a, 87b, and does not fill the holes. After this, conventional photolithography and etching treatments are used to define polycrystalline silicon layers in the form of a trunk 88a, 88b for the storage electrodes.

  memory cells in the DRAM device. As re-

  shown in Figure 6A, each of the trunk-shaped polycrystalline silicon layers 88a, 88b has a substantially U-shaped cross section, which provides increased area over which the storage electrodes

  can store large amounts of electrical charge.

  Referring next to FIG. 6B, it is noted that in the next step

  In a wet attack operation, the protective layer against attack 22 is applied to the wafer as the end point of the attack, so as to remove the insulating layers 30, 26 and the insulating pillar 24. This completes the fabrication of the storage electrodes of the tree type capacitors in the DRAM device. The embodiment differs from that of FIG. 2F in that the trunk-shaped parts of the storage electrodes, that is to say the trunk-shaped polycrystalline silicon layers 88a, 88b, are hollow and have U-shaped cross sections, which give the storage electrodes a

  increased surface area. We can now form a dielectric film.

  that and an opposite polycrystalline silicon electrode, as described

  previously for the first, second and third embodiments

  tion. After this, the fabrication of the tree type capacitors in

the DRAM device is completed.

  Sixth preferred embodiment A sixth embodiment of the invention is illustrated in Figures 7A and 7B. Also in this embodiment, the trunk-shaped portion of each tree-shaped storage electrode is

  dig. The tree type capacitors of the sixth embodiment

  tion are based on the structure of Figure 5C. The elements of FIGS. 7A and 7B which are identical to those of FIG. 5C are designated by the

same reference numbers.

  Referring first to FIG. 7A, together with FIG. 5C, it is noted that after the manufacture has reached the stage which is represented in FIG. 5C, conventional treatments are used.

  photolithography and attack to remove by attack parts

  lectionées of the insulating layer 84, layers of polycrystalline silicon-

  flax 82a, 82b and insulating layer 80, so as to form holes

  contact 90a, 90b which extend downward from the upper surface

  from the insulating layer 84 to the upper surfaces of the elements

  T-shaped elements 74a, 74b of the storage electrodes. Next, the CVD method is used to deposit a layer of polycrystalline silicon, the thickness of which is reduced by etching, so as to form lateral wall spacing elements 92a, 92b on the interior walls of the contact holes 90a, 90b. Side wall spacers

  92a, 92b constitute upper trunk-shaped parts of the elect

  tree-shaped storage trodes, and they are hollow, with U-shaped cross sections, which gives the storage electrode a

increased surface area.

  Referring next to FIG. 7B, it is noted that in the next step

  In this case, a wet attack operation is applied to the wafer, with the attack protection layer 72 as the end point of the attack, so as to remove the insulating layers 84, 80 and the insulating pillar 78. This completes the fabrication of the storage electrodes of the tree type capacitors in the DRAM device. The mode of

  realization differs from that of FIG. 5D by the fact that the upper part

  The bottom of each electrode in the form of a trunk is hollow, and also has a U-shaped cross section. It is now possible to form a dielectric film and an opposite electrode in polycrystalline silicon, as described above for the first, second and third embodiments. After this, the manufacture of the tree type capacitors

  in the DRAM device is completed.

  Seventh preferred embodiment In the previous six embodiments, the portion in

  branch shape of the tree-shaped storage electrode has a sec-

  transverse L-shaped, so that it is bent, with two segments

  straight. The invention is however not limited to such a structure.

  The number of straight segments can be increased to three or

  more. The following description, referring to FIGS. 8A and 8F, relates to

  a seventh embodiment in which the branch-shaped part

  che of each tree-shaped storage electrode is angled, with

four straight segments.

  The tree type capacitors of the seventh mode of reaction

  These are based on the structure of Figure 2A. The elements of the fi-

  gures 8A to 8F which are identical to those of FIG. 2A are designated

  by the same reference numbers.

  Referring first to FIG. 8A in conjunction with FIG. 2A, it is noted that after the manufacture has reached the stage which is represented in FIG. 2A, the CVD process is used to deposit an insulating leveling layer. 100, consisting for example of borophosphosilicate glass. The same process is then used to deposit a layer of protection against attack, which can for example be a layer of silicon nitride 102. A layer is then deposited on the wafer.

  thick insulating layer, for example consisting of silicon dioxide.

  After this, we use a conventional photolithographic processing to

  form a layer of photosensitive resist material 106, and ef-

  then performs an anisotropic attack on the silicon dioxide layer

  bare cium, so as to form projecting insulating layers 104 and a

underlying insulating layer 103.

  Referring next to FIG. 8B, it is noted that in the next step

  boasts a photosensitive resin erosion technique

  to erode part of the photosensitive resin layer 106, thereby

  Lesson to form a layer of photosensitive resin 106a which is reduced both in width and in thickness (height). Part of the surface of

  protruding insulating layers 104, previously located under the

  che photosensitive resin 106 not eroded, is thus exposed.

  Referring next to FIG. 8C, it is noted that in the next step

  In order to carry out an anisotropic attack on the exposed surface of the

  projecting insulating pads 104 and the underlying insulating layer 103,

  until the layer of silicon nitride 102, which fulfills the function

  tion of a layer of protection against attack, or exposed. Cou-

  104a projecting insulating panels with stepped side walls are

  thus formed. After this, the photosensitive resin layer is removed.

  Referring next to FIG. 8D, it is noted that the steps

  are the same as those shown in the figures

  res 2C and 2D, in which the CVD process is used successively to form a first insulating layer 108, a polycrystalline silicon layer and a second insulating layer 112, and then the chemo-mechanical polishing technique is applied to the surface of the wafer so as to remove by polishing an upper part of the layer of

  polycrystalline silicon. The remaining part of the poly- silicon layer

  lens thus includes a number of separate sections which are

  designated by the references 110a, 110Ob.

  Referring next to FIG. 8E, it is noted that in the next step

  We use classic photolithography and atmospheric treatments.

  tack to successively remove, by attack, selected parts

  born from insulating layer 112, polycrystalline silicon layers

  110a, 110Ob, of the insulating layer 108, of the silicon nitride layer

  cium 102, the insulating planarizing layer 100 and the gate oxide film 14, so as to form storage electrode contact holes 114a, 114b which extend from the upper surface of the insulating layer 112 to the upper surface of the drain regions 16a and 16b. After this, the storage electrode contact holes 114a, 114b are filled with polycrystalline silicon layers 116a, 116b, first using the CVD process to deposit a polycrystalline silicon layer, and then by etching a part of

  the thickness of the polycrystalline silicon layer.

  Referring next to FIG. 8F, it is noted that in the following stage, a wet attack operation is carried out on the wafer,

  with the silicon nitride layer 102 as the end point of the attack

  that in order to remove the insulating layers 112, 108 of silicon dioxide and the insulating pillar 104a. This completes the manufacturing of the storage electrodes of the tree type capacitors in the device.

  DRAM. We can now form a dielectric film and an electric

  opposite polycrystalline silicon trode, as described above for the first, second and third embodiments. After this, the fabrication of the tree type capacitors in the DRAM device

is completed.

  As illustrated in FIG. 8F, the storage electrodes of the tree-type capacitors comprise layers of trunk-shaped polycrystalline silicon 116a, 116b and layers of branch-shaped polycrystalline silicon 110a, 110Ob, each of these being

  angled, with four straight segments. Poly- silicon layers

  trunk-shaped lens 116a, 116b are electrically connected

  to the drain regions 16a and 16b of the transfer transistor in the device

  DRAM. The lowest horizontal segments of the silicon layers

  polycrystalline cium in the form of a branch 110a, 110b are in contact with

  the trunk-shaped polycrystalline silicon layers 116a, 116b.

  Insulating pillars or projecting insulating layers of this

  embodiment have a modified form so as to give the

  polycrystalline silicon in the form of a branch an increased area for charge storage. However, the particular shapes of the insulating pillars and the projecting insulating layers are not limited to those described. Thus, by referring for example to FIG. 2B, it is noted that one can use an isotropic attack or a wet attack instead of an anisotropic attack to remove by attack part of

  the thick insulating layer. This allows the formation of insulating layers

  almost triangular in shape, instead of the rectangular layers that are shown. In addition, also referring to FIG. 2B, it is noted that after the formation of the insulating pillar 24, it is possible to form insulating layers of side walls on the side walls of the insulating pillar 24, so as to form insulating pillars of different shape. The branch-shaped polycrystalline silicon layers can therefore be

  modified to take various forms.

  If it is desired to fabricate the branch-shaped polycrystalline silicon layers with an increased number of straight segments, the wafer structure of Figures 8B and 8C can be used as a basis, and the technique can then be used repeatedly of photosensitive resin erosion and anisotropic attack, to form the insulating layers

  protruding with an increased number of rung segments.

  Eighth preferred embodiment In the preceding seven embodiments, the chemo-mechanical polishing technique is used to divide a single layer of polycrystalline silicon into separate sections which are respectively

  used to form individual storage electrodes. The invent-

  However, this is not limited to the use for this purpose of the chemical mechanical polishing technique. Instead, in accordance with an eighth embodiment of the invention which is illustrated in FIGS. 9A to 9D, the chemomechanical polishing process can be replaced by conventional photolithography and etching treatments, to divide the

  single layer of polycrystalline silicon in separate sections.

  The tree type capacitor of the eighth embodiment

  tion is based on the structure of Figure 3A. The elements in FIGS. 9A to 9D which are identical to those in FIG. 3A are designated by the

same reference numbers.

  Referring first to FIG. 9A in conjunction with FIG. 3A, it is noted that after the manufacture has reached the stage which is represented in FIG. 3A, it is removed by attack or it is polished by the chemo polishing technique. -mechanical the upper layer of silicon dioxide 48, until the upper layer of silicon

  polycrystalline 46 is exposed. The resulting slice structure is re-

shown in Figure 9A.

  Referring next to FIG. 9B, it is noted that a

  conventional photolithographic treatment to form a protective layer

  sine photosensitive 120. After this, a successive

  anisotropic coating on the exposed parts of the polycrystalline silicon layer

  flax 46, the silicon dioxide layer 44 and the polycrystalline silicon layer 42. Such an etching operation has the effect of dividing the polycrystalline silicon layers 42, 46 into a number of sections

  separated which are designated by the references 42c, 42d and 46c, 46d.

  Referring next to FIG. 9C, it is noted that conventional photolithography and etching treatments are then applied to form contact holes for storage electrode 122a, 122b which

  extend from the upper surface of the insulating layer 48 to

  than at the upper surface of the drain regions 16a and 16b. The storage electrode contact holes 122a, 122b are then filled with layers of polycrystalline silicon 124a, 124b, first using the CVD process to deposit a layer of polycrystalline silicon, and then by etching away a portion of the thickness of the layer of

polycrystalline silicon.

  Referring next to FIG. 9D, it is noted that in the next step

  A wet attack is applied to the wafer, with the attack protective layer 22 as the end point of the attack, so as to remove the insulating layers 40, 44, 48 of dioxide.

  of silicon and the insulating pillar 24. This completes the manufacture of the electro-

  storage of tree type capacitors. We can now

  thus forming a dielectric film and an opposite electrode in silicon.

  polycrystalline cium, as described above for the first, second

  and third embodiments. After this, the manufacture of conden-

  sater type tree in the DRAM device is completed.

  These electrodes consist of layers of polycrystalline silicon in the form of a trunk 124a, 124b and layers of polycrystalline silicon in the form of a branch 42c, 46c and 42d, 46d, each of them being constituted by three rectilinear segments. The layers of silicon

  polycrystalline in the form of a trunk 124a, 124b are respectively connected

  electrically connected to the drain regions 16a and 16b of the transfer transistors in the DRAM device. Polycrystalline silicon layers

  in the form of a branch 42c, 46c and 42d, 46d have their horizontal segments-

  respective lower rates in contact with the layers of poly-

  trunk-shaped lens 50a, 50b.

  Ninth Preferred Embodiment In the first to seventh previous embodiments, the upper segments of the branch-shaped polycrystalline silicon layers are substantially aligned in the same horizontal plane, and

  in the eighth embodiment the upper segments of the

  Branch-shaped polycrystalline silicon plates are practically ali-

  in the same vertical plane. The invention is however not limited to such structures. According to a variant, in accordance with a ninth embodiment of the invention which is illustrated in FIGS. 10A to 1 OD, the upper segments of the polycrystalline silicon layers in

  branch shape are not aligned.

  The tree type capacitor of the ninth embodiment

  sation is based on the structure of Figure 9A. The elements on the fig-

  res 10A to 10D which are identical to those of FIG. 9A are designated

  by the same reference numbers.

  Referring first to FIG. 10A together with FIG. 9A, it is noted that after the manufacture has reached the stage which is represented in FIG. 9A, photolithographic processing is used

  conventional to form a layer of photosensitive resin 130, and ef-

  performs an anisotropic attack on the exposed parts of the silica layer

  polycrystalline cium 46 and the layer of silicon dioxide 44. This pro-

  cessus has the effect of dividing the layer of polycrystalline silicon 46 into

  a number of separate sections which are designated by the references

rences 46e, 46f.

  Referring next to FIG. 10B, it is noted that in the next step

  We use the photosensitive resin erosion technique to remove

  erosion worm part of the photosensitive resin layer 130, so as to form a photosensitive resin layer 130a of reduced width and thickness. A part of the upper surface of the polycrystalline silicon layers 46e, 46f is thus exposed. Then we do

  an anisotropic attack on the exposed parts of the poly- silicon layers

  crystalline 46e, 46f and 42. By this process, parts of the polycrystalline silicon layers 46e, 46f are removed more by etching, which has the effect of forming polycrystalline silicon layers 46g, 46h

  reduced in size. After this, an aniso-

  trope on the bare parts of the layers of silicon dioxide 44, 40, until

  that the upper surfaces of the polycrystalline silicon layers

  linen 42g, 42h are exposed. The layer of photosensitive resin is then removed.

  Referring next to FIG. 10C, it is noted that in the next step

  We use classic photolithography and atmospheric treatments.

  plate to form contact holes for storage electrode 132a,

  132b which extend from the upper surface of the iso- layer

  lante 48 to the upper surfaces of the drain regions 16a and 16b.

  The storage electrode contact holes 132a, 132b are then filled with polycrystalline silicon layers 134a, 134b, using

  first of all the CVD process for depositing a layer of polycrystalline silicon, and then by removing part of the thickness by attack

  of the polycrystalline silicon layer.

  Referring finally to FIG. 10D, it is noted that in step

  next, an attack operation is applied to the wafer

  mide, with the protective layer against attack 22 as the end point of the attack, so as to remove the insulating layers 40, 44, 48 of silicon dioxide and the insulating pillar 24. This completes the manufacture of the

  storage electrodes of the tree type capacitors in the

  positive DRAM. We can now form a dielectric film and an opposite polycrystalline silicon electrode, as described above for the first, second and third embodiments. After this, the fabrication of the tree type capacitors in the DRAM device

is completed.

  The storage electrodes include the silicon layers.

  trunk-shaped polycrystalline cium 134a, 134b and the silicon layers

  polycrystalline cium in the form of a branch 42g, 46g and 42h, 46h having cross sections in L. The layers of polycrystalline silicon in

  trunk shape 134a, 134b are respectively connected electric-

  to the drain region 16a and to the drain region 16b of the transistors

  transfer to the DRAM device. Polycrystalline silicon layers

  linen in the shape of a branch 42g, 46g and 42h, 46h have horizontal segments-

  lower rates which are respectively in contact with the layers of

  polycrystalline silicon in the form of a trunk 134a, 134b, and the pra-

  vertically vertical layers of polycrystalline silicon in the form of

  branch 46g, 46h are higher than those of the silicon layers po-

  lycristalline in the shape of a branch 42g, 42h. It will appear to specialists in the field of semiconductor manufacturing that the embodiments described above can be applied alone or in combination, so as to provide storage electrodes of various sizes and shapes, on a single chip.

  of DRAM. All these variants fall within the scope of the invention.

  Although in the accompanying drawings, the embodiments of the drains of the transfer transistors are based on diffusion zones in a silicon substrate, other variants, for example

  trench-type drain regions are possible.

  The elements in the accompanying drawings are representations

  schematic statements for illustrative purposes and are not shown in

  the actual scale. The dimensions of the elements of the invention which are re-

  presented should not be considered in any way as

  limitations of the scope of the invention.

  It goes without saying that many other modifications can be made to the process described and shown, without going beyond the ambit of the invention.

Claims (32)

  1. Method for manufacturing a semicon memory device   conductors, comprising a substrate (10), a transfer transistor having source / drain regions (16a, 16b) formed in the substrate, and a charge storage capacitor electrically connected to one of   source / drain regions, characterized in that it comprises the following steps   vantes: (1) a first insulating layer (20) is formed on the substrate, the first insulating layer covering the transfer transistor; (2) we   forms an insulating pillar (24) on the first insulating layer, the iso-   lant defining regions of cavities on either side of itself; (3) forming a first conductive layer (28) on the insulating pillar and on the first insulating layer (20) in the cavity regions; (4) removing portions of the first conductive layer (28) so as to leave a set of first conductive layer sections (28a, 28b); (5) forming a second conductive layer (34a, 34b) in a cavity region, this layer penetrating at least through the first layer   conductive (28) and the first insulating layer (20), so as to be con-   electrically connected to one of the source / drain regions (16a, 16b), the second conductive layer forming a trunk-shaped conductive layer (34a, 34b) and the first conductive layer forming a layer   branch-shaped conductor (28a, 28b) having substantially a sec-   L-shaped cross-section, the L-shaped cross-section having one end connected to the trunk-shaped conductive layer, the first layer   conductive (28a, 28b) and the second conductive layer (34a, 34b) form   mant in combination a storage electrode for the charge storage capacitor; (6) the insulating pillar (24) is removed; (7) we form a   dielectric layer (36a, 36b) on the first and second layers   ducting; and (8) a third conductive layer (38) is formed on the   dielectric layer (36a, 36b), the third conductive layer filled   sant the function of an opposite electrode of the storage capacitor dump.   2. Method according to claim 1, characterized in that the   conductive trunk-shaped layer includes a practical segment-   vertical (34a, 34b) having an electrically connected lower end   only at one of the source / drain regions (16a, 16b).   3. Method according to claim 1, characterized in that it further comprises, between step (1) and step (2), the step of forming a layer of protection against attack (22 ) on the first layer insulating (20).   4. Method according to claim 3, characterized in that step (2) comprises the following steps: a thick insulating layer is formed on the protective layer against attack (102); a photosensitive resin layer (106) is formed on the thick insulating layer, so that a first part of the thick insulating layer is exposed; a region of the first bare part of the thick insulating layer is removed by attack, to form the cavity in the first bare part; we   erodes a selected part of the photo- resin layer   sensitive (106), so as to further expose a second part of the thick insulating layer; and we remove by attack the second naked part and we also remove by attack the first naked part, until   the attack protection layer (102) is exposed in the case   vity, and so as to form the insulating pillar (104a, 104b) with a section transverse staircase.   5. Method according to claim 3, characterized in that the cavity region is limited in its lower part by the protective layer against attack (22), the insulating pillar (24) being formed on the   protective layer against attack.   6. Method according to claim 1 or 4, characterized in that step (4) comprises the step which consists in removing by attack the part   selected from the first conductive layer (28) which extends above the insulating pillar (24).   7. Method according to claim 1 or 4, characterized in that   step (4) includes the step of using chemical polishing   mechanical to remove the selected part of the pre-   first conductive layer (28) which extends above the insulating pillar (24). 8. Method according to claim 1 or 4, characterized in that it further comprises, between step (3) and step (4), the step which consists in   forming a second insulating layer (30) on the first conductive layer   trice (28), the second insulating layer filling almost completely   the cavity region; in that step (5) comprises forming the second conductive layer (34a, 34b) so that it penetrates   through the second insulating layer (30); and in that step (6) comprises   takes the removal of the second insulating layer (30).   9. Method according to claim 1 or 4, characterized in that it further comprises, between step (3) and step (4), the following steps:   at least one first film (44) of material is alternately formed   insulating line and a second film (46) of conductive material, on the   first conductive layer (42), and a second iso-   lante (48) on the second film, so as to fill practically   completely the cavity region; in that step (4) further comprises   the step of removing a selected part of the second peel   joint (46), so as to remove an upper part of the second film   cule which extends above the insulating pillar (24); in that step (5)   further includes the step of forming the second layer   conductive (50a, 50b) so that it successively penetrates through the second insulating layer (48), the second film (46) and the first   film (44); and in that step (6) further comprises the step which involves   is to remove the second insulating layer (48) and the first film (44).   10. Method according to claim 1 or 4, characterized in that   that step (5) further comprises the step of forming the se-   conde conductive layer (88a, 88b) so that it has a substantially U-shaped cross section. 11. Method according to claim 1, 2 or 3, characterized in that   that it further comprises, between step (3) and step (4), the following steps   vantes: at least a first film (44) of insulating material and a second film (46) of conductive material are alternately formed on the first conductive layer (42); and a second insulating layer (48) is formed on the second film, so as to fill practically   completely the cavity region; in that step (4) further comprises   the following steps: a layer of photosensitive resin is formed without covering at least the insulating pillar; removing bare portions successively from the second film (46) and the first film (44); part of the photosensitive resin layer is eroded, so as to expose another part of the second film, after   the erosion stage, we remove this other bare part of the second film   cule and a bare part of the first conductive layer, and removing the photoresist layer; in that step (5) further comprises the step of forming the second conductive layer (50a,   b) so that it penetrates successively through the second cou-   insulating che (48), the second film (46) and the first film (44); and in that step (6) further comprises the step of removing   the second insulating layer (48) and the first film (44).   12. Method of manufacturing a semi-memory device   conductors, comprising a substrate (10), a transfer transistor having source / drain regions (16a, 16b) formed in the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions, characterized in that this method comprises the following steps: (1) a first insulating layer (20) is formed on the substrate, the first insulating layer covering the transistor   transfer; (2) an insulating pillar (24) is formed on the first iso- layer   lante (20), the insulating pillar defining regions of cavities on both sides and   else of himself; (3) alternately forming a first film   insulating material (26) and a second film (28) of insulating material   conductor, on the first insulating layer (20), in a region of ca   vity and on the insulating pillar (24); (4) removing a selected portion of the second film (28) which extends above the insulating pillar (24); (5) a first conductive layer (34a, 34b) is formed which penetrates at least through the second film, the first film and the first insulating layer, so as to be electrically connected to one of the source / drain regions ( 16a, 16b), the first conductive layer (34a,   34b) and the second film (28a, 28b) forming in combination an elect   charge storage capacitor storage trode; (6) removing the insulating pillar (24) and the first film (26); (7) forming a layer   dielectric (36a, 36b) on bare surfaces of the first layer   duct and second film; and (8) forming a second layer   conductive (38) on the dielectric layer, the second conductive layer   trice performing the function of an opposite electrode of the capacitor charge storage.   13. The method of claim 12, characterized in that the first conductive layer forms a trunk-shaped conductive layer (34a, 34b) and the second film forms a branch-shaped conductive layer (28a, 28b) having substantially a cross-section. transverse in L, the branch-shaped conductive layer having one end   connected to the trunk-shaped conductive layer.   14. Method according to claim 13, characterized in that the   conductive layer in the form of a trunk (34a, 34b) is practically verti-   wedge and it has a lower end electrically connected to one   source / drain regions (16a, 16b).   15. The method of claim 12, 13 or 14, characterized in that step (2) further comprises the following steps: a thick insulating layer is formed on the layer protecting against attack (102); a photosensitive resin layer (106) is formed on the thick insulating layer, so that the cavity region is exposed; removing a bare portion of the thick insulating layer in the cavity region; part of the photosensitive resin layer (106) is removed by erosion, so as to expose an additional part of the thick insulating layer; removing the additional exposed part of the thick insulating layer to expose the attack protection layer (102), so as to form the insulating pillar (104a, 104b) with a stepped cross section; and we remove the photoresist layer (106).   16. The method of claim 12 or 15, characterized in that step (4) comprises the step of removing by attack the selected part of the second film (28) which extends above the insulating pillar (24).   17. Method according to claim 12 or 15, characterized in that   that step (4) includes the step of using chemical polishing   micro-mechanical to remove by polishing the selected part of the   second film (28) which extends above the insulating pillar (24).   18. Method according to any one of claims 12 or   17, characterized in that it further comprises, between step (3) and step (4), the step which consists in forming a second insulating layer (30) on the   second film (28), so that the second insulating layer   almost completely wrinkles the cavity region; in that step (5) includes the step of forming the first conductive layer (34a, 34b) so that it penetrates through the second insulating layer   (30); and in that step (6) comprises the step of removing the se- insulating layer (30).   19. Method according to any one of claims 12 to 18,   characterized in that step (5) further comprises the step of   forming the first conductive layer (88a, 88b) with a cross-section   practically U-shaped. 20. Method according to claim 12, characterized in that it   further includes the following steps: repeat step (3) to obtain   nir, in the cavity region, two first films (40, 44) of material   insulating line, interlaced with two second films (42, 46) of material   riau conductor; and a second insulating layer (48) is formed on the   wraps the upper film, so that the second insulating layer fills the cavity region almost completely; in that step (4) comprises the following steps: (a) a layer of photosensitive resin is formed on the second upper film so that part of the second upper film is located above the pillar   insulation either bare; (b) after step (a), successive parts are removed-   bare the second upper film and the first upper film; (c) part of the photosensitive resin layer is eroded, so as to expose another part of the second   top film; (d) the other bare part of the second film is removed   ass; and (e) removing the photoresist layer after step (d); in that step (5) further comprises forming the first   conductive layer (50a, 50b) so that it penetrates through the   insulating layer (48); and in that step (6) further comprises   the step of removing the second insulating layer (48).   21. Method of manufacturing a semi-memory device   conductors, comprising a substrate (10), a transfer transistor having source / drain regions (16a, 16b) formed in the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions, characterized in that this method comprises the following steps: (1) forming a first insulating layer (70) on the substrate (10), the insulating layer covering the transfer transistor; (2) a first conductive layer (74a, 74b) is formed which penetrates   through at least the first insulating layer (70), so as to be con   electrically connected to one of the source / drain regions (16a, 16b); (3) an insulating pillar (78) is formed on the first insulating layer, the pi-   insulating tie defining regions of cavities on either side of it   even; (4) alternately forming a first film (80) of insulating material and a second film (82) of conductive material, on the first insulating layer (70), in a cavity region and on the insulating pillar (78) ; (5) removing a selected portion of the second film (82) which extends above the insulating pillar (78); (6) we train   a second conductive layer (86a, 86b) which penetrates at least through   towards the second film and the first film, so as to be   electrically connected to one of the source / drain regions (16a, 16b), the   first and second conductive layers (74a, 74b; 86a, 86b) and the se-   film holder (82a, 82b) forming in combination a storage electrode of the charge storage capacitor; (7) we remove the pillar   insulator (78) and the first film (80); (8) a dielectric layer is formed   stick on bare surfaces of the first and second conductive layers   these (74a, 74b; 86a, 86b) and the second film (82a, 82b); and (9) a third conductive layer is formed on the dielectric layer, the   third conductive layer fulfilling the function of an op-   posed for the charge storage capacitor.   22. The method of claim 21, characterized in that the second film (82a, 82b) has substantially an L-shaped cross section and has one end connected to the second conductive layer (86a, 86b). 23. Method according to claim 22, characterized in that the first conductive layer (74a, 74b) has practically a cross section in T, and the second conductive layer has practically a cross section in U. 24. The method of claim 21, characterized in that it further comprises, between step (1) and step (2), the step which consists in forming a layer of protection against attack (72 ) on the first insulating layer (70).   25. The method of claim 21 or 24, characterized in that step (3) comprises the following steps: a thick insulating layer (104) is formed on the layer for protection against attack (102);   a photosensitive resin layer (106) is formed on the iso-   thick mantle, so that the cavity region is exposed; removing a bare portion of the thick insulating layer in the cavity region; part of the photosensitive resin layer is eroded, so as to expose an additional part of the thick insulating layer; the additional bare part of the thick insulating layer is removed, to expose the attack protection layer (102),   so as to form the insulating pillar with a steep cross-section   bind (104a); and removing the layer of photosensitive resin (106).   26. The method of claim 21 or 25, characterized in that the step (5) comprises the step of removing by attack the selected part of the second film (82) which extends above the insulating pillar (78).   27. Method according to any one of claims 20 to 25,   characterized in that step (5) includes the step of performing   kill a chemo-mechanical polish to polish off the selected part of the second film (82) which extends above the pillar insulator (78).   28. Method according to claim 21 or 25, characterized in that   that it further comprises, between step (4) and step (5), the step which   is to form a second insulating layer (84) on the second film (82), so that the second insulating layer substantially fills the cavity region; in that step (6) comprises the step of forming the second conductive layer (86a, 86b) so that it penetrates through the second insulating layer (84); and in that step (7) includes the step of removing the second insulating layer (84).   29. Method according to claim 21, characterized in that it   further includes the following steps: repeat step (4) to obtain   providing in the cavity region two first films of insulating material interleaved with two second films of conductive material; and a second insulating layer is formed on the second upper film,   so that the second insulating layer practically fills   completely the cavity region; in that step (5) includes the steps   following: (a) a layer of photosensitive resin is formed on the   covers the upper film, so that part of the second upper film above the insulating pillar is exposed; (b) removing successively bare portions of the second upper film and the first upper film; (c) we remove by erosion part of   the layer of photosensitive resin, so as to expose another part   tie of the second upper film; (d) removing the other bare part of the second film; and (e) removing the photoresist layer after the second step (d); in that step (6) further comprises the step of forming the second conductive layer so that it penetrates through the second insulating layer; and in that the step   (7) further comprises the step of removing the second iso- layer lante.   30. Method of manufacturing a semi-memory device   conductors, comprising a substrate (10), a transfer transistor having source / drain regions (16a, 16b) formed in the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions, characterized in that this process comprises   the following steps: (1) an insulating layer (20) is formed on the substrate   trat (10), the insulating layer covering the transfer transistor; (2) forming a conductive layer in the form of a trunk (34a, 34b) having a lower end electrically connected to one of the regions of   source / drain (16a, 16b), the conductive layer in the form of a trunk extends   extending almost vertically from the lower end; (3) we   forms a branch-shaped conductive layer (28a, 28b),   providing at least a first segment and a second segment, the first segment having a first end connected to the conductive layer   in the shape of a trunk (34a, 34b) and a second end connected to the   cond segment, the second segment being aligned at a first angle with respect to the first segment, and the conductive layer in the form of a trunk   (34a, 34b) and the branch-shaped conductive layer (28a, 28b) form   mant in combination a storage electrode of the charge storage capacitor; (4) forming a dielectric layer (36a, 36b) on exposed surfaces of the trunk-shaped conductive layer (34a, 34b) and the branch-shaped conductive layer (28a, 28b); and (5) forming a conductive covering layer (38) covering the layer   dielectric (36a, 36b), the conductive covering layer filled   sant the function of an opposite electrode for the stock capacitor- charge age.   31. Method of manufacturing a semi-memory device   conductors, comprising a substrate (10), a transfer transistor having source / drain regions (16a, 16b) formed in the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions, characterized in that this process comprises   the following steps: (1) an insulating layer (20) is formed on the substrate   trat (10), the insulating layer covering the transfer transistor; (2) forming a trunk-shaped conductive layer (34a, 34b) having a lower end electrically connected to one of the source / drain regions (16a, 16b) of the transfer transistor, the trunk-shaped conductive layer extending substantially vertically from the lower end; (3) a conductive layer is formed in the form of   branch (28a, 28b), comprising at least one segment having an end   mite connected to the trunk-shaped conductive layer (34a, 34b), extending outward from the trunk-shaped conductive layer, the trunk-shaped conductive layer (34a, 34b) and the conductive layer in the form of a branch (28a, 28b) forming, in combination, a storage electrode of the charge storage capacitor; (4) a dielectric layer (36a, 36b) is formed on bare surfaces of the   conductive layer in the form of a trunk (34a, 34b) and of the layer   branching ducting (28a, 28b); and (5) forming a conductive covering layer (38) covering the dielectric layer (36a, 36b), the conducting covering layer fulfilling the function   an opposite electrode for the charge storage capacitor.   32. Method of manufacturing a semi-memory device   conductors, comprising a substrate (10), a transfer transistor having source / drain regions (16a, 16b) formed in the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions, characterized in that this process comprises   the following steps: (1) an insulating layer (20) is formed on the substrate   trat (10), the insulating layer covering the transfer transistor; (2) forming a conductive trunk-like layer (34a, 34b) having a lower end electrically connected to one of the source / drain regions (16a, 16b), the conductive trunk-like layer extending substantially vertically from the lower end; (3) a branch-shaped conductive layer (28a, 28b) is formed, having practically an L-shaped cross section, the branch-shaped conductive layer having one end connected to the trunk-shaped conductive layer, the conductive layer in trunk shape (34a, 34b) and   the branch-shaped conductive layer (28a, 28b) forming, in   binning, a storage electrode of the charge storage capacitor; (4) forming a dielectric layer (36a, 36b) on surfaces   exposed the trunk-shaped conductive layer (34a, 34b) and the   conductive branch-shaped che (28a, 28b); and (5) we form a   conductive covering layer (38) covering the dielectric layer   as (36a, 36b), the conductive covering layer fulfilling the function of an opposite electrode for the charge storage capacitor.