JP3024676B2 - Method of manufacturing semiconductor memory device having tree-type capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a structure of a dynamic random access memory (DRAM) cell mainly including a transfer transistor and a charge storage capacitor.

[0002]

FIG. 1 is a circuit diagram of a memory cell of a DRAM device. As shown in the figure, the DRAM cell includes a transfer transistor T and a charge storage capacitor C. The source of the transfer transistor T is connected to the corresponding bit line BL, and the drain of the transfer transistor T is connected to the storage electrode 6 of the charge storage capacitor C. The gate of the transfer transistor T is connected to the corresponding word line WL, and the opposite electrode 8 of the capacitor C
Connected to a constant power supply. Further, a dielectric film 7 is supplied between the storage electrode 6 and the counter electrode 8.

In a DRAM manufacturing process, a storage capacity of 1
Conventional DRAM with less than M (mega = 1 million) bits
In this case, a two-dimensional capacitor called a planar type capacitor is mainly used. In the case of a DRAM having a memory cell using a planar capacitor, electric charges are accumulated on a main surface of a semiconductor substrate.
The area must be large. Therefore, this type of memory cell is not suitable for a highly integrated DRAM. For a highly integrated DRAM such as a DRAM having a memory of 4 Mbits or more, a three-dimensional capacitor called a stack type or trench type capacitor has been introduced.

[0004] Larger memories of similar size have been obtained with such stacked or trench capacitors. However, in order to realize a highly integrated semiconductor device such as a very large scale integrated circuit (VLSI) having a storage capacity of 64 Mbits, a capacitor having a simple three-dimensional structure such as a conventional stack type or trench type is required. Proved inadequate.

One way to improve the capacitance of a capacitor is to use a so-called fin-type stacked capacitor, which is disclosed in Emma et al.
3D stacked capacitor cell for mega DRAM (3
-Dimensional Stacked Capac
itor Cell for 16M and 64M
DRAMs) "(International Electronic Devices Conference (Inter)
nationalElectron Devices
Meeting), 592-595, December 1988.
Month issue). Finned stacked capacitors include fin-shaped extending electrodes and dielectric films in a plurality of stacked layers. DRAMs with finned stacked capacitors are also disclosed in US Pat.
No. 783 (Taguchi et al.), No. 5,126,810 (Goto), No. 5,196,365 (Goto), No. 5,20
No. 6,787 (Fujioka).

Another measure for improving the capacitance of the capacitor is to use a so-called cylinder-type stacked capacitor, which is a new type of stacked capacitor cell for Wakamiya et al.
l Stacked Capacitor Cell
(for 64-Mb DRAM) "(1989 Symposium on VLSI)
Technology Digest ofTech
ncal Papers), pp. 69-70). Since the cylindrical stacked capacitor includes the electrode and the dielectric film extending in a cylindrical shape, the surface area of the electrode is increased. A DRAM with a stacked cylinder capacitor is also disclosed in U.S. Pat. No. 5,077,688 (Cumanoya et al.).

[0007]

As the degree of integration increases, the size (area occupying the plane) of a DRAM cell on a plane must be further reduced. In general, a decrease in cell size leads to a decrease in charge storage capacity (capacitance), and as the capacitance decreases,
The possibility of occurrence of a soft error due to the generation of α rays increases. Therefore, there is still a need in the art for the design of new structures for storage capacitors that have the same capacitance and at the same time occupy less area on a plane, and for a suitable method of making that structure.

Accordingly, an object of the present invention is to provide a semiconductor memory device having a tree-type capacitor capable of increasing the charge storage area.

[0009]

SUMMARY OF THE INVENTION In accordance with the above and other objects of the present invention, there is provided a new and improved semiconductor memory device and a method of fabricating the same.

A semiconductor memory device according to the present invention includes a tree-type capacitor having a larger area for securely storing electric charges representing data. The tree-type capacitor includes a storage electrode comprising a trunk-like conductive layer and one or more branch-like conductive layers. The trunk-like conductive layer is electrically connected to one of the source / drain regions of the transfer transistor in the semiconductor memory device. In addition, the branch-like conductive layer has 1
The end is connected to the trunk-shaped conductive layer, and can be configured in various shapes so that the surface area can be increased.
The dielectric layer is formed on the exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer, and the overlay conductive layer is formed on the dielectric layer serving as the counter electrode of the tree-type capacitor.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the present invention will become apparent from the following detailed description of preferred but non-limiting embodiments. This will be described below with reference to the accompanying drawings described below.

(First Embodiment) A first embodiment of a semiconductor memory device provided with a tree-type charge storage capacitor according to the present invention will be described with reference to FIGS.
This embodiment of the semiconductor memory device can be manufactured by the first preferred method of manufacturing a semiconductor memory device according to the present invention.

Referring to FIG. 2, the silicon substrate 1
LOCOS (silicon selective oxidation)
Is thermally oxidized by the method, so that, for example, a thickness of about 3
000 Å of field oxide film 12 is formed. Next, by subjecting the silicon substrate 10 to a thermal oxidation process, a gate oxide film 14 having a thickness of, for example, about 150 Å is formed. Further, a polysilicon film having a thickness of, for example, about 2000 Å is deposited on the entire surface of the silicon substrate 10 by chemical vapor deposition (CVD) or low pressure CVD (LPCVD). In order to realize a polysilicon film having a low resistance, appropriate impurities such as phosphorus ions are diffused into the polysilicon film. Preferably, after the heat-resistant metal layer is deposited on the polysilicon film, an annealing step is performed to form polycide, thereby further reducing the resistance of the film. The refractory metal may be tungsten (W), for example, having a thickness of about 20
00 angstroms. Next, as shown in FIG. 2, the polycide is patterned to form gate electrodes (word lines) WL1 to WL4. Further, for example, arsenic ions are diffused into the silicon substrate 10 at an energy of 70 KeV, for example, about 1 × 10 ¹⁵ atoms / cm ^2.
Impurity concentration. At this stage, the word lines WL to W
L4 is used as a mask layer. Thus, drain regions 16a and 16b and source regions 18a and 18b are formed on silicon substrate 10.

Next, FIG. 3 will be described. In the next step, a planarizing insulating layer 20 of, for example, borophosphosilicate glass (BPSG) is
Deposit to a thickness of 0 Å. Further, the etching protection layer 22 is formed by the same method, but this layer may be, for example, a silicon nitride film having a thickness of about 1000 angstroms. Thereafter, a thick insulating layer of, for example, silicon dioxide is deposited on the wafer, for example, at about 700
Deposited to a thickness of 0 Å. Therefore, using conventional photolithography and etching, insulating pillars 24 delimited by recesses 23 are defined. In FIG. 3, insulating columns 24 are provided in many different places.
However, the insulating pillars 24 are actually integrated, which is apparent when viewed from above.

Referring now to FIG. In the next stage, the first insulating layer 26, the polysilicon layer 28, and the second insulating layer 30 are sequentially formed by the CVD method. First
In addition, the second insulating layers 26 and 30 are preferably formed of silicon oxide. The first insulating layer 26 and the polysilicon layer 28 are each deposited to a thickness of, for example, about 1000 angstroms, and the second insulating layer 30 is deposited to a thickness of, for example, about 7,000 angstroms.
Arsenic (As) ions can be diffused into the polysilicon layer 28 to increase conductivity.

Referring now to FIG. 5, in the next step, the wafer surface of FIG. 4 is subjected to chemical mechanical polishing (CMP) until the top of polysilicon layer 28 is smoothed. This separates the remaining portion of polysilicon layer 28 into a number of independent sections, as shown in FIG.

Referring to FIG. 6, the insulating layer 30 is formed by a conventional photolithography method and an etching method.
Polysilicon layer sections 28a and 28b, insulating layer 2
6. Etching is sequentially and selectively applied to the etching protection layer 22, the insulating layer 20, and the gate oxide film 14. Thereby, the storage electrode contact holes 32a and 32
b is formed. Storage electrode contact holes 32a and 32b extend from the upper surface of insulating layer 30 to the upper surfaces of drain regions 16a and 16b, respectively. Next, the storage electrode contact holes 32a and 32a are deposited by depositing a polysilicon film and etching back.
b is replenished with polysilicon layers 34a and 34b.

Referring to FIG. 7, in the next stage,
As an etching end point, wet etching is performed on the wafer provided with the etching protection layer 22 so that the insulating layers 26 and 30 and the insulating pillars 24 can be removed. The combination of the remaining tree trunk-like polysilicon layers 34a and 34b and the branch-like polysilicon layers 28a and 28b forms a tree-like storage electrode for a DRAM capacitor. Trunk-like polysilicon layers 34a and 3
4b is electrically connected to the drain regions 16a and 16b of the transfer transistor in the DRAM, respectively. The cross section of each of the branch-like polysilicon layers 28a and 28b is substantially L-shaped, and a substantially horizontal cross section is in electrical contact with the trunk-like polysilicon layers 34a and 34b. Due to this particular shape, the storage electrode will hereinafter be referred to as a "tree-shaped storage electrode" and hence the capacitor will be referred to as a "tree-type capacitor".

Referring to FIG. 8, in the next stage,
The dielectric films 36a and 36b are respectively composed of a tree-shaped storage electrode (34a, 28a) and a tree-shaped storage electrode (34).
b, 28b). Dielectric films 36a and 3
6b can be formed of, for example, silicon dioxide, silicon nitride, NO (silicon nitride / silicon dioxide), ONO (silicon dioxide / silicon nitride / silicon dioxide). Next, the storage electrodes (34a, 28a) and (34b, 28
A counter electrode 38 of polysilicon facing b) is formed on the dielectric films 36a and 36b. The step of forming the counter electrode 38 includes a first step of depositing a polysilicon layer to a thickness of, for example, about 1000 angstroms by a CVD method, and a second step of diffusing N-type impurities into the polysilicon layer to increase conductivity. And a final step of etching selected portions of the polysilicon layer by conventional photolithography and etching. This is DRAM
The fabrication of the tree-type capacitor inside is completed.

In order to complete the fabrication of the DRAM chip, the steps of fabricating a bit line, bonding a pad,
It must go through an interconnect phase, a passivation phase, and a packaging phase. However, since each of these steps includes only the prior art and departs from the spirit and scope of the present invention, a detailed description thereof will be omitted here.

(Embodiment 2) In the first embodiment described above, the disclosed tree-type capacitor has only one branch-type electrode. However, the number of branches is not limited to one, and may be two or more. Hereinafter, the tree-type capacitor according to the second embodiment including electrodes formed by two branches will be described with reference to FIGS. 9 to 12. The tree-type capacitor according to the second embodiment is based on the wafer structure shown in FIG. FIG. 9 identical to that of FIG.
12 are assigned the same reference numerals.

FIG. 9 will be described with reference to FIG. CVD
The first insulating layer 40, the first polysilicon layer 4
2, insulating layers such as the second insulating layer 44, the second polysilicon layer 46, and the third insulating layer 48 and the polysilicon layer are alternately formed sequentially. The insulating layers 40, 44, and 48 are preferably formed of, for example, silicon oxide. Insulating layers 40 and 44 and polysilicon layers 42 and 46
Are each deposited, for example, to a thickness of about 1000 angstroms, and the insulating layer 48 is deposited, for example, to a thickness of about 7,000 angstroms. The polysilicon layers 42 and 46 can be diffused by arsenic (As) ions to increase the conductivity.

Referring now to FIG. 10, in the next stage, the CMP method is applied to the wafer surface shown in FIG.
The tops of polysilicon layers 42 and 46 are polished. This separates the remaining portions of the polysilicon layers 42 and 46 into a number of independent sections indicated by reference numerals 42a and 46a and 42b and 46b.

Referring to FIG. 11, in the next stage, the storage electrode contact is formed from the upper surface of the insulating layer 48 (see FIG. 10) to the surfaces of the drain regions 16a and 16b by the conventional photolithography and etching. Form a hole. Next, first, after the storage electrode contact holes are filled with the polysilicon layers 50a and 50b by using the CVD method and the polysilicon layer is deposited, an etching back process is performed on the polysilicon layer. Next, a wet etching process is performed on the wafer where the etching protection layer 22 serves as an etching end point so that the insulating layers 40, 44, 48 and the insulating pillars 24 can be removed. Remaining trunk-like polysilicon layer 5
0a and 50b and branch-like polysilicon layers 42a and 46b and 42b and 46b,
One tree-shaped storage electrode is formed. Trunk-shaped polysilicon layers 50a and 50b are electrically connected to drain regions 16a and 16b of transfer transistors in the DRAM, respectively. The cross sections of the branch-like polysilicon layers 42a and 46a and 42b and 46b are substantially L-shaped, and the substantially horizontal cross section is in contact with the trunk-like polysilicon layers 50a and 50b.

Referring to FIG. 12, in the next stage, dielectric films 52a and 52b are formed on tree-shaped storage electrodes (50a, 46a, 42a) and (50b, 46b, 42b), respectively. Next, the opposing polysilicon electrode 54 is connected to the dielectric films 52a and 52b.
Formed on top. The method of forming the counter electrode 54 includes a first step of depositing a polysilicon layer by a CVD method, a second step of diffusing N-type impurities into the polysilicon layer to increase conductivity, and a conventional photolithography method and etching method. A final step of etching selected portions of the polysilicon layer. When the above steps are completed, the fabrication of the tree-type capacitor in the DRAM is completed.

(Embodiment 3) In the first and second embodiments described above, the lowermost portion of the branch portion of the tree-shaped storage electrode is separated from the etching protection layer 22. However, the invention is not limited to such a structure.
A third embodiment of the present invention in which the lowermost layer of the branch-shaped portion of each tree-shaped storage electrode is in contact with the etching protection layer 22 will be described below with reference to FIGS.

The tree type capacitor of the third embodiment is also manufactured based on the structure shown in FIG. Elements in FIGS. 13 and 14 that are the same as those in FIG. 3 have the same reference numerals.

Referring first to FIG. 13 in conjunction with FIG. 3, an insulating layer such as a first polysilicon layer 60, a first insulating layer 62, a second polysilicon layer 64, and a second insulating layer 66 is formed by CVD. Polysilicon layers are formed alternately and sequentially.

Referring now to FIG. 14, in the next stage, the upper surface of the polysilicon layers 60 and 64 is polished by applying the CMP method to the wafer surface shown in FIG. Thereby, the remaining portions of the polysilicon layers 60 and 64 are denoted by reference numerals 60a and 64a and 60b and 64b.
b into a number of independent sections.
Next, a storage electrode contact hole is formed by a conventional photolithography method and an etching method. Further, the storage electrode contact hole is formed in the polysilicon layer 68.
Replenished with a and 68b. Thereafter, wet etching is performed on the wafer where the etching protection layer 22 is the etching end point so that the insulating layers 62 and 66 can be removed.

The remaining trunk-like polysilicon layers 68a and 68b and the branch-like polysilicon layers 60a and 60
By combining 4b, 60b and 64b, two tree-shaped storage electrodes are formed. Trunk-shaped polysilicon layers 68a and 68b are electrically connected to drain regions 16a and 16b of transfer transistors in the DRAM, respectively. The cross-sectional shape of each of the branch-like polysilicon layers 60a and 64a and 60b and 64b is substantially L-shaped, and a substantially horizontal cross section is in contact with the trunk-like polysilicon layers 68a and 68b. In this embodiment, the branch-like polysilicon layer 60 of the tree-like storage electrode is used.
a and 60b are in contact with the etching protection layer 22. This makes it possible to form the dielectric film and the opposing polysilicon electrode as described above with respect to the first, second, and third embodiments. Thus, the fabrication of the tree-type capacitor in the DRAM is completed.

(Embodiment 4) In the above-mentioned three embodiments, the trunk-like portion of the tree-like storage electrode of each tree-type capacitor is a semiconductor element integrally formed. It is not limited to the structure. Hereinafter, a fourth embodiment in which the trunk-shaped portion of each tree-shaped storage electrode includes a plurality of semiconductor elements will be described with reference to FIGS.
This will be described with reference to FIG.

The tree type capacitor of the fourth embodiment is also manufactured based on the structure of FIG. Elements in FIGS. 15-18 that are the same as those in FIG. 2 have the same reference numerals.

First, referring to FIG. 15 together with FIG. 2, a planarization insulating layer 70 is deposited on a BPSG wafer, for example, by a CVD method. Next, an etching protection layer 72 of, for example, silicon nitride is deposited by the same method. Thereafter, etching is performed on selected portions of the etching protection layer 72 and the planarization insulating layer 70 by conventional photolithography and etching, and drain regions 16a and 16b are formed from the upper surface of the etching protection layer 72.
Storage electrode contact holes 76a and 76b are formed over the upper surface of the substrate. Next, a polysilicon layer filling the storage electrode contact holes 76a and 76b is deposited on the wafer by CVD. The polysilicon layer can increase conductivity by diffusing impurities. In addition, T-shaped elements 74a and 74b are defined by conventional photolithography and etching techniques,
Each bottom of a capacitor charge storage electrode for a memory cell in a RAM is formed.

Referring now to FIG. 16, in the next step, a thick insulating layer of, for example, silicon dioxide is deposited on the wafer. Thereafter, a selected portion of the insulating layer is etched by a conventional photolithography method and an etching method, and an insulating column 78 is formed. Further, C
The first insulating layer 80 and the polysilicon layer 8 are formed by using the VD method.
2, and the second insulating layer 84 are sequentially formed.

Next, FIG. 17 will be described. In the next stage, the wafer surface shown in FIG. 16 is subjected to a CMP process, and the upper portion of the polysilicon layer 82 is polished. Thus, the remaining portion of the polysilicon layer 82
It is separated into a number of independent sections, indicated by reference numerals 82a and 82a.

Referring to FIG. 18, in the next stage, selected portions of the second insulating layer 84, the polysilicon layers 82a and 82b, and the first insulating layer 80 are sequentially etched by a conventional photolithography method and an etching method. Then, a contact hole is formed from the upper surface of the insulating layer 84 to the upper surfaces of the T-shaped elements 74a and 74b of the tree-shaped storage electrode. Next, the contact hole is filled with polysilicon, and the upper part 8 of the tree-shaped storage electrode is filled.
6a and 86b are formed. The step of replenishing the contact holes with polysilicon includes a first step of depositing a polysilicon layer by a CVD method and a second step of performing an etching back process on the polysilicon layer. Thereafter, wet etching is performed on the wafer provided with the etching protection layer 72 as an etching end point, and the insulating layer 84 is formed.
And 80 and the insulating pillar 78 can be removed. Thus, the fabrication of the storage electrode of the tree-type capacitor in the DRAM is completed. This embodiment differs from the embodiment of FIG. 7 in that each of the storage electrodes further comprises a substantially horizontal cross section extending from T-shaped elements 74a and 74b at the bottom. Thereby, the first, second, and third
As already described for the embodiment, a dielectric film and a counter polysilicon electrode can be formed. After its formation,
The fabrication of the tree-type capacitor in the DRAM is completed.

(Embodiment 5) In the above-described four embodiments, the trunk-like portion of the tree-like storage electrode is a solid-state semiconductor element, but the present invention is not limited to such a structure. Hereinafter, a fifth embodiment in which the trunk-shaped portion of each tree-shaped storage electrode is hollow will be described with reference to FIGS. 19 and 20.

The tree type capacitor of the fifth embodiment is based on the structure shown in FIG. Elements of FIGS. 19 and 20 that are the same as those of FIG. 5 have the same reference numerals.

Referring first to FIG. 19 together with FIG. 5, when the above-mentioned fabrication reaches the stage of FIG. 5, the insulating layer 30, the branch-like polysilicon layers 28a and 28 are formed by the conventional photolithography and etching.
b, the selected portions of the insulating layer 26, the etching protection layer 22, the planarized insulating layer 20, and the gate oxide film 14 are etched to remove the drain region 16 from the upper surface of the insulating layer 30.
Storage electrode contact holes 87a and 87b are formed over the upper surfaces of a and 16b. Next, a polysilicon layer is formed only on the inner walls of the storage electrode contact holes 87a and 87b by a CVD method, and the polysilicon layer is deposited in such a manner that the holes are not replenished. Thereafter, trunk-like polysilicon layers 88a and 88b are defined for each storage electrode of the memory cell in the DRAM by conventional photolithography and etching. As shown in FIG. 19, the cross section of each of trunk-like polysilicon layers 88a and 88b is substantially U
It is shaped like a letter and provides a wider area where the storage electrode can store a large amount of charge.

Next, referring to FIG. 20, in the next stage, the etching protection layer 2 is used as an etching end point.
A wet etching process is performed on the wafer provided with the insulating layer 2 to remove the insulating layers 30 and 26 and the insulating columns 24. Thus, the fabrication of the storage electrode of the tree-type capacitor in the DRAM is completed. The trunk-like portion of the storage electrode,
This embodiment differs from the embodiment of FIG. 7 in that the trunk-like polysilicon layers 88a and 88b are hollow and the cross-section is U-shaped to increase the surface area of the storage electrode. As a result, the dielectric film and the opposing polysilicon electrode can be formed in the first, second, and third embodiments as described above. After its formation, DR
The fabrication of the tree-shaped capacitor in the AM is completed.

(Embodiment 6) FIGS. 21 and 22 show:
A sixth embodiment of the present invention is shown. Also in this embodiment, the trunk-shaped portion of each tree-shaped storage electrode is hollow. FIG. 17 shows a tree-type capacitor according to the sixth embodiment.
It is produced based on the structure of FIG. 2 identical to that of FIG.
1 and FIG. 22 have the same reference numerals.

First, FIG. 21 will be described with reference to FIG. When the progress of the fabrication reaches the stage of FIG. 17, the conventional photolithography method and etching method are used.
Selected portions of the insulating layer 84, the polysilicon layers 82a and 82b, and the insulating layer 80 are etched to remove the storage electrode T-shaped elements 74a and 74b from the upper surface of the insulating layer 84.
Contact hole 90 extending downward toward the upper surface of
a and 90b are formed. Next, after depositing a polysilicon layer by the CVD method, sidewall spacers 92a and 92b are formed on the inner walls of the contact holes 90a and 90b by etching back. Side wall spacer 92
a and 92b constitute an upper trunk-like portion of the tree-like storage electrode, and have a U-shaped cross section,
A storage electrode having a larger surface area is realized.

Next, referring to FIG. 22, in the next stage, wet etching is performed on the wafer having the etching protective layer 72 as an etching end point, and the insulating layer 8 is formed.
4 and 80 and the insulating pillar 78 are removed. From the above,
Fabrication of the storage electrode of the tree-type capacitor in the DRAM is completed. This embodiment is different from that of FIG. 18 in that the upper part of each trunk electrode is hollow and the cross section is U-shaped. Thus, the dielectric film and the opposing polysilicon electrode can be formed as already described in the description of the first, second, and third embodiments. When the formation is completed, the fabrication of the tree-type capacitor in the DRAM is completed.

(Embodiment 7) In the above-described sixth embodiment, the cross section of the branch portion of the tree-shaped storage electrode is
It is a key-shaped L-shape with two straight segments,
The invention is not limited to such a structure. The number of straight line segments can be increased to three or more. FIG.
With reference to FIG. 28, a seventh embodiment in which the branch portion of each tree-shaped storage electrode has a key-shaped bent portion by four straight segments will be described below.

The tree type capacitor of the seventh embodiment is based on the structure of FIG. 23 to 28 that are the same as those in FIG. 2 are denoted by the same reference numerals.

First, FIG. 23 will be described with reference to FIG. When the progress of the fabrication reaches the stage shown in FIG. 2, the planarization insulating layer 100 of, for example, BPSG is deposited by the CVD method. Next, an etching protection layer is deposited by the same method, which may be, for example, the silicon nitride layer 102. Next, a thick insulating layer of, for example, silicon dioxide is deposited on the wafer. Thereafter, after a photoresist layer 106 is formed by a conventional photolithography method, the exposed silicon dioxide layer is subjected to anisotropic etching to form a projection type insulating layer 104 and a lower insulating layer 103.

Referring now to FIG. 24, in the next step, a part of the photoresist layer 106 is eroded by a photoresist erosion method to reduce both the width and the thickness (height). 106a is formed. Thereby, the photoresist layer 106 before being corroded is formed.
A part of the surface of the projection-type insulating layer 104 formed beforehand is exposed below.

Referring to FIG. 25, the exposed surface of the projection type insulating layer 104 and the lower insulating layer 103 are anisotropic until the silicon nitride layer 102 serving as an etching protective layer is exposed in the next stage. Etching is performed. As a result, the projection type insulating layer 10 having the step-like side walls is formed.
4a is formed. Thereafter, the photoresist layer is removed.

Referring now to FIG. 26, the next stage is the same as the stage shown in FIGS.
The first insulating layer 108, the polysilicon layer, and the second insulating layer 112 are sequentially formed by the
The upper portion of the polysilicon layer is polished by applying the MP manufacturing method.
As a result, the remaining portion of the polysilicon layer
a and 110b into a number of independent sections.

Referring to FIG. 27, at the next stage,
The insulating layer 112 and the polysilicon layers 110a and 11a are formed by the conventional photolithography and etching.
0b, the insulating layer 108, the silicon nitride layer 102, the planarizing insulating layer 100, and the selected portion of the gate oxide film 14 are sequentially etched to form storage electrode contacts from the upper surface of the insulating layer 112 to the upper surfaces of the drain regions 16a and 16b. Holes 114a and 114b are formed. Thereafter, first, a polysilicon layer is deposited by the CVD method, and then a part of the polysilicon layer is etched back, and the storage electrode contact holes 114a and 114a are removed.
4b is supplemented by polysilicon layers 116a and 116b.

Referring to FIG. 28, in the next step, the silicon nitride layer 102 is used as an etching end point.
Wet etching is performed on a wafer provided with insulating layers 112 and 108 made of silicon dioxide and insulating pillars 1.
04a is removed. Thus, the fabrication of the storage electrode of the tree-type capacitor in the DRAM is completed. Thus, the dielectric film and the opposing polysilicon electrode can be formed as already described in the first, second, and third embodiments. When the formation is completed, the fabrication of the tree-type capacitor in the DRAM is completed.

As shown in FIG. 28, the storage electrodes of the tree-type capacitor are composed of trunk-like polysilicon layers 116a and 116b and hook-shaped branch-like polysilicon layers 110a and 110b each composed of four straight segments.
It has. Trunk-shaped polysilicon layers 116a and 116b are electrically connected to drain regions 16a and 16b of transfer transistors in the DRAM.
The horizontal segment corresponding to the lowermost layer of the branch-like polysilicon layers 110a and 110b is in contact with the trunk-like polysilicon layers 116a and 116b.

The insulating pillar or the projection type insulating layer according to the present embodiment is modified to have a shape capable of forming a branch-like polysilicon layer having a larger area for storing charges. However, the individual shapes of the insulating pillar and the protrusion type insulating layer are not limited to those described herein. Therefore, for example, referring to FIG. 3, when a part of the thick film insulating layer is etched, it is possible to employ isotropic etching or wet etching instead of anisotropic etching. Thus, an insulating layer having a shape close to a triangle can be formed instead of a rectangular insulating layer as illustrated. Further, referring to FIG. 3 again, after the insulating pillars 24 are formed, a sidewall insulating layer can be formed on the sidewalls of the insulating pillars 24, whereby insulating pillars having different shapes can be formed. Therefore, the branch-like polysilicon layer can be modified into various shapes.

If it is desired to increase the number of straight segments of the branch-like polysilicon layer, the wafer structure shown in FIGS. 24 and 25 can be adopted for the substrate, and then the photoresist erosion method and the anisotropic etching are applied. Using it repeatedly
A projection-type insulating layer having a large number of step-shaped segments can be formed.

(Embodiment 8) In the above-described seven embodiments, a single layer made of polysilicon is divided into independent sections by the CMP method, and individual storage electrodes are formed using each section. In order to achieve the object, the present invention is not particularly limited to the use of the CMP method. According to the eighth embodiment of the present invention shown in FIGS. 29 to 32, a single layer made of polysilicon can be divided into individual sections by using a conventional photolithography method and an etching method instead of the CMP method. it can.

The tree-type capacitor according to the eighth embodiment is based on the structure shown in FIG. FIG. 29 to FIG.
Elements in FIG. 32 have the same reference numerals.

Referring first to FIG. 29 in conjunction with FIG. 9, when the progress of the fabrication reaches the stage of FIG. 9, the top layer of silicon dioxide 48 is removed by CMP until the top polysilicon layer 46 is exposed. Etched and polished. As a result, a wafer structure as shown in FIG. 29 is formed.

Next, referring to FIG. 30, a photoresist layer 120 is formed by a conventional photolithography method. Thereafter, for the exposed portions of the polysilicon layer 46, the silicon dioxide layer 44, and the polysilicon layer 42,
Anisotropic etching is sequentially performed. As a result of such etching, the polysilicon layers 42 and 46
It is separated into a number of individual sections indicated by 2c and 42d and 46c and 46d.

Referring to FIG. 31, storage electrode contact hole 1 extending from the upper surface of insulating layer 48 to the upper surfaces of drain regions 16a and 16b by conventional photolithography and etching.
22a and 122b are formed. Next, first of all C
By depositing the polysilicon layer using the VD method and etching back a part of the polysilicon layer, the storage electrode contact holes 122a and 122b are filled with the polysilicon layers 124a and 124b.

Referring to FIG. 32, in the next step, the wafer provided with the etching protection layer 22 as an etching end point is subjected to wet etching, and the insulating layers 40, 44, 48 made of silicon dioxide and the insulating pillars 24 are formed.
Is removed. Thus, the production of the storage electrode of the tree-type capacitor is completed. In this state, the dielectric film and the opposing polysilicon electrode can be formed as described above with reference to the first, second, and third embodiments. After the formation, the fabrication of the tree-type capacitor in the DRAM is completed.

The above electrodes are composed of trunk-like polysilicon layers 124a and 124b, and branch-like polysilicon layers 42c and 46c each having three straight segments.
And 42d and 46d. Trunk-shaped polysilicon layers 124a and 124b are electrically connected to drain regions 16a and 16b of a transfer transistor in the DRAM, respectively. Each of the branch-like polysilicon layers 42c and 46c and 42d and 46d has a lowermost horizontal segment in contact with the trunk-like polysilicon layers 50a and 50b.

(Embodiment 9) In the first to seventh embodiments, the uppermost segment of the branch-like polysilicon layer is substantially aligned with the same horizontal plane, and the uppermost segment of the trunk-like polysilicon layer is formed. The segments are substantially parallel to the same vertical plane. However, the invention is not limited to such a structure. According to the ninth embodiment of the present invention shown in FIGS. 33 to 36, the uppermost segment of the branch-like polysilicon layer is not aligned with the horizontal plane.

The tree type capacitor of the ninth embodiment is based on the structure shown in FIG. FIG. 3 identical to that of FIG. 29
Elements in FIGS. 3 to 36 are given the same reference numerals.

Referring first to FIG. 33 together with FIG. 29, when the progress of fabrication reaches the stage of FIG. 29, a photoresist layer 130 is formed by a conventional photolithography method, and a polysilicon layer 46 and a silicon dioxide layer 44 are formed.
Is subjected to anisotropic etching. By this step, the polysilicon layer 46 is formed with the reference numerals 46e and 4e.
It is separated into a number of individual sections indicated by 6f.

Referring now to FIG. 34, in the next step, the photoresist layer 13 is formed by a photoresist erosion method.
0 is corroded to form a photoresist layer 130a having a smaller width and thickness. Therefore, a part of the upper surface of polysilicon layers 46e and 46f is exposed. Further, the exposed portions of the polysilicon layers 46e, 46f, and 42 are subjected to anisotropic etching. By this process,
Portions of the polysilicon layers 46e and 46f are further etched to form smaller polysilicon layers 46g and 46h. Then, the polysilicon layer 42g
The exposed portions of silicon dioxide layers 44 and 40 are again subjected to an anisotropic etch until the top surfaces of and 42h are exposed. Next, the photoresist layer is removed.

Referring further to FIG. 35, in the next stage, storage electrode contact holes 132a and 132b are formed from the upper surface of insulating layer 48 to the upper surfaces of drain regions 16a and 16b by conventional photolithography and etching. Form. Next, first, a polysilicon layer is deposited by a CVD method, and then a part of the polysilicon layer is subjected to an etching back process to thereby form the storage electrode contact hole 1.
32a and 132b are replenished with polysilicon layers 134a and 134b.

Finally, referring to FIG. 36, in the next stage, the etching protection layer 2 is used as an etching end point.
The wafer with 2 is wet etched to remove the insulating layers 40, 44 and 48 of silicon dioxide and the insulating columns 24. Thus, the fabrication of the storage electrode of the tree-type capacitor in the DRAM is completed. In this state, the dielectric film and the opposing polysilicon electrode can be formed as already described in the description of the first, second, and third embodiments. After the formation, the fabrication of the tree-type capacitor in the DRAM is completed.

The storage electrodes include trunk-like polysilicon layers 134a and 134b, and branch-like polysilicon layers 42g and 46g and 42h and 42h and 4h having an L-shaped cross section.
6h is included. Trunk-shaped polysilicon layer 134
a and 134b are electrically connected to the drain regions 16a and 16b of the transfer transistors in the DRAM, respectively. Branch-like polysilicon layers 42g and 46g and 42h and 46h have lowermost horizontal segments in contact with trunk-like polysilicon layers 134a and 134b, respectively.
The substantially vertical segments of g and 46h are higher than those of the branch-like polysilicon layers 42g and 42h.

The fact that the embodiments disclosed above can be applied singly as they are, and that various combinations of storage electrodes of various sizes and shapes can be provided on a single DRAM chip by combining them. It will be clear to the trader. All such variations are within the scope of the present invention.

In the accompanying drawings, the embodiment relating to the drain of the transfer transistor is based on the diffusion region of the silicon substrate, but other modifications, for example, a trench type drain region are also possible.

The elements of the accompanying drawings are shown diagrammatically for the purpose of illustration and are not drawn to scale.
The dimensions of the elements of the invention shown here do not in any way limit the scope of the invention.

While the present invention has been described in terms of representative examples and preferred embodiments, it should be apparent that they are not limited to the disclosed embodiments. Rather, as will be apparent to those skilled in the art, the present invention is intended to cover various modifications and similar variations. Therefore, the scope of the appended claims, which limit the scope of the invention, should be given the broadest interpretation so as to cover all such modifications and similar structures.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory cell of a DRAM device.

FIG. 2 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 1)

FIG. 3 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 2)

FIG. 4 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 3)

FIG. 5 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 4)

FIG. 6 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 5)

FIG. 7 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 6)

FIG. 8 is a cross-sectional view illustrating a first embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 7)

FIG. 9 is a cross-sectional view illustrating a second embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 1)

FIG. 10 is a cross-sectional view illustrating a second embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 2)

FIG. 11 is a cross-sectional view illustrating a second embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 3)

FIG. 12 is a cross-sectional view illustrating a second embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 4)

FIG. 13 is a cross-sectional view illustrating a third embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 1)

FIG. 14 is a cross-sectional view illustrating a third embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 2)

FIG. 15 is a cross-sectional view illustrating a fourth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 1)

FIG. 16 is a cross-sectional view illustrating a fourth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 2)

FIG. 17 is a cross-sectional view illustrating a semiconductor memory cell including a tree-type capacitor according to a fourth embodiment of the present invention and a method of manufacturing the same according to the present invention. (Part 3)

FIG. 18 is a cross-sectional view illustrating a semiconductor memory cell including a tree-type capacitor according to a fourth embodiment of the present invention and a method of manufacturing the same according to the present invention. (Part 4)

FIG. 19 is a sectional view illustrating a fifth embodiment of a semiconductor memory cell having a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 1)

FIG. 20 is a cross-sectional view illustrating a fifth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 2)

FIG. 21 is a sectional view illustrating a sixth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 1)

FIG. 22 is a sectional view illustrating a sixth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 2)

FIG. 23 is a cross-sectional view illustrating a seventh embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 1)

FIG. 24 is a cross-sectional view illustrating a seventh embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 2)

FIG. 25 is a cross-sectional view illustrating a seventh embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 3)

FIG. 26 is a cross-sectional view illustrating a seventh embodiment of a semiconductor memory cell having a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 4)

FIG. 27 is a cross-sectional view illustrating a seventh embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 5)

FIG. 28 is a cross-sectional view illustrating a seventh embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 6)

FIG. 29 is a sectional view illustrating an eighth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 1)

FIG. 30 is a sectional view illustrating an eighth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 2)

FIG. 31 is a sectional view illustrating an eighth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 3)

FIG. 32 is a cross-sectional view for explaining an eighth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention; (Part 4)

FIG. 33 is a cross-sectional view illustrating a ninth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 1)

FIG. 34 is a cross-sectional view illustrating a ninth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 2)

FIG. 35 is a cross-sectional view illustrating a ninth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for fabricating the same according to the present invention. (Part 3)

FIG. 36 is a cross-sectional view illustrating a ninth embodiment of a semiconductor memory cell including a tree-type capacitor according to the present invention and a method for manufacturing the same according to the present invention. (Part 4)

[Explanation of symbols]

 10: Silicon substrate 16a, 16b: Drain region 20: Flattening insulating layer 22: Etching protective layer 28a, 28b: Branch-like polysilicon layer 34a, 34b: Trunk-like polysilicon layer 38: Counter electrode 42a, 42b: Branch-like poly Silicon layers 46a, 46b: Branch-like polysilicon layers 50a, 50b: Trunk-like polysilicon layers 54: Opposing polysilicon electrodes 60a, 60b: Branch-like polysilicon layers 64a, 64b: Branch-like polysilicon layers 68a, 68b: Trunk-like Polysilicon layer 70: Flattening insulating layer 72: Protective layer 74a, 74b: T-shaped element 82a, 82b: Polysilicon layer 86a, 86b: Upper part of tree-shaped storage electrode 88a, 88b: Trunk-shaped polysilicon layer 92a, 92b: Side wall spacer 100: Flatten Marginal 102: silicon nitride layer 110a, 110b: branch-like polysilicon layers 116a, 116 b: trunk-like polysilicon layers 124a, 124b: trunk-like polysilicon layers 134a, 134b: trunk-like polysilicon layer

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-267614 (JP, A) JP-A-5-204428 (JP, A) JP-A-9-181272 (JP, A) JP-A-6-181272 326266 (JP, A) JP-A-8-204148 (JP, A) JP-A-7-211794 (JP, A) JP-A-7-169855 (JP, A) JP-A-9-36333 (JP, A) JP-A-6-196651 (JP, A) JP-A-8-18017 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (30)

(57) [Claims] 1. A semiconductor memory comprising a substrate, a transfer transistor having a source / drain region formed on the substrate, and a charge storage capacitor electrically connected to any one of the source / drain regions. in the manufacturing method for the device, the method comprising (1) forming by laminating the first insulating layer and the etching protective layer covering the transfer transistor on the substrate, the thickness (2) the etching protective layer forming a film insulating layer, said such that a first portion of the thick film insulative layer is exposed, the photoresist layer is formed on the thick insulating layer, the first exposed portion of the thick insulating layer partially by etching, the concave portion to form a region in the first exposure portion, by performing the erosion process on selected portions of the photoresist layer further to expose the second portion of the thick film insulative layer, wherein Etching the second exposure portion, and the recess territory
By performing further etching on the first exposed portion until said etching protection layer is exposed in the band, forming a insulation posts that have a stepped cross-section, (3) the insulating pillars and the First conductive layer covering the concave area
Forming a second insulating layer on the first conductive layer so as to substantially fill the recessed area; and (4) partially forming the first conductive layer while leaving a plurality of sections of the first conductive layer. (5) at least before the second insulating layer and the first conductive layer;
The etching protection layer and the first insulating layer are etched.
Through said opening formed by more penetrating removed source /
A second conductive layer that will be either one electrically connected the drain region in the step of forming the recess region, the second conductive layer forms a trunk-like conductive layer, and the first conductive layer Gab Form a launch-like conductive layer and form the branch- like conductive layer.
One end of the conductive layer is connected to the trunk-like conductive layer, and a stage that form a storage electrode of the charge storage capacitor by a combination of the first conductive layer and the second conductive layer, (6) the insulating Removing the pillar and the second insulating layer ; (7) forming a dielectric layer on the first and second conductive layers; and (8) forming the charge storage capacitor on the dielectric layer. Forming a third conductive layer functioning as a counter electrode of (a). 2. The method according to claim 1, wherein the trunk-like conductive layer is formed on the source /
The method of claim 1, comprising a substantially vertical segment with a bottom end face electrically connected to any one of the drain regions. Wherein said step (4) A method according to claim 1, characterized in that it comprises the step of etching said selected portion of said first conductive layer lying above the insulative pedestal. 4. The method of claim 1, wherein said step (4) comprises polishing said selected portion of said first conductive layer overlying said insulating pillar by applying chemical mechanical polishing. 2. The method according to 1 . Wherein said step (3) is, on the first conductive layer, Ru consists of at least one insulating material first
1 stage of forming a second film made of a film and a conductive material are alternately consists of a step of forming a second insulating layer on the second layer so as to substantially satisfy the recess, and said step (4 ) Further comprises the step of removing a selected upper portion of said second film lying above said insulating pillar; said step (5) comprising: removing said second insulating layer, said second film,
The method may further include forming the opening that sequentially penetrates the first film, and the step (6) further includes removing the second insulating layer and the first film. Claim 1
The method described in. Wherein said step (5) The method of claim 1, further comprising a step of forming the second conductive layer having a cross-section substantially U-shaped. Wherein said step (3) is, on the first conductive layer, forming alternately a second layer consisting of a first layer and a conductive material comprising at least one insulating material, said recessed areas made from a step of forming a second insulating layer on said second layer so as to satisfy substantially and said step (4)
But forming a photoresist layer without covering at least said insulating pillars, the method comprising sequentially removing the exposed portions of the second layer and the first layer, so that another portion of said second film is exposed Partially removing the photoresist layer after the erosion step; removing another exposed portion of the second film and the exposed portion of the first conductive layer after the erosion step; and removing the photoresist layer. And the step (5), wherein the step (5) includes the second insulating layer, the second film,
The method may further include forming the opening that sequentially penetrates the first film, and the step (6) further includes removing the second insulating layer and the first film. Claim 1
The method described in. 8. A semiconductor memory comprising: a substrate; a transfer transistor having a source / drain region formed on the substrate; and a charge storage capacitor electrically connected to one of the source / drain regions. In the method for manufacturing an element, the method includes: (1) forming a first insulating layer covering the transfer transistor on the substrate; and (2) forming an insulating pillar on the first insulating layer, a step of defining a recessed region pillars at both sides thereof, (3) the said first insulating layer in the recess region insulating a pole
A first film made of an insulating material and a second film made of a conductive material are alternately formed, and a second insulating film is formed on the second film so as to substantially fill the recessed region.
Forming an edge layer; (4) removing a selected portion of the second film lying above the insulating pillar; and (5) at least the second insulating layer, the second film, and the second 1 film and the first insulating layer penetrated by etching.
Forming a first conductive layer electrically connected to any one of the source / drain regions through an opening formed by removing the first conductive layer and the second film by a combination of the first conductive layer and the second film; a stage that form a storage electrode of the charge storage capacitor, (6) the insulating pillars and said second insulating layer and removing the first layer, (7) the said first conductive layer and the second Forming a dielectric layer on the exposed surface of the two films; and (8) forming a second conductive layer functioning as a counter electrode of the charge storage capacitor on the dielectric layer. Manufacturing method. 9. The first conductive layer forms a trunk-like conductive layer, the second film forms a branch-like conductive layer having a substantially L-shaped cross section, and one end of the branch-like conductive layer is formed at one end of the branch-like conductive layer. 9. The method of claim 8 , wherein the method is connected to a trunk-like conductive layer. Wherein said trunk-like conductive layer is substantially perpendicular, and claim 9, wherein the has a bottom end surface which is any one electrically connected to the source / drain region the method of. 11. The method of claim 8 , further comprising, between the step (1) and the step (2), forming an etching protection layer on the first insulating layer. the method of. 12. The method according to claim 8 , wherein step (4) comprises etching the selected portion of the second film overlying the insulating pillar. Wherein said step (4) is, by a chemical mechanical polishing method, according to claim 8, characterized in that it comprises the step of polishing the selected portion of the second layer lying above the insulative pedestal the method of. 14. The method of claim 8 , wherein step (5) further comprises forming the first conductive layer having a substantially U-shaped cross section. 15. The step (2) includes: forming a thick film insulating layer on the etching protection layer; and forming a photoresist layer on the thick film insulating layer so that the concave region is exposed. Removing the exposed portion of the thick insulating layer in the recessed region; partially eroding the photoresist layer so that the thick insulating layer is further partially exposed; and etching protection. Forming the insulating pillar having a stepped cross section by further removing the exposed portion of the thick film insulating layer so that the layer is exposed; and removing the photoresist layer. The method of claim 11 , wherein: 16. wherein step (4) A method according to claim 15, characterized by comprising the step of the selected portion to etching of the second layer lying above the insulative pedestal. 17. The method of claim 15, wherein said step (4) comprises polishing said selected portion of said second film overlying said insulating pillars by a chemical mechanical polishing method. the method of. 18. The method of claim 17, wherein step (5) The method of claim 15, further comprising a step of forming the first conductive layer having a cross-section substantially U-shaped. 19. A step of repeating the step (3) to realize the concave region in which two first films made of an insulating material and two second films made of a conductive material are alternately stacked. A second at the top to substantially fill the recessed area
Forming a second insulating layer on the film, and the step (4) includes: (a) forming the second insulating layer on the insulating pillar so that a part of the uppermost second film on the insulating pillar is exposed; Forming a photoresist layer on the upper second film; and (b) sequentially removing the uppermost second film and the exposed portion of the uppermost first film after the step (a). (C) partially eroding the photoresist layer so that another portion of the uppermost second film is exposed; and (d) removing the another exposed portion of the second film. 9. The method of claim 8, further comprising: (e) removing the photoresist layer after step (d).
the method of. 20. A semiconductor comprising: a substrate; a transfer transistor having a source / drain region formed on the substrate; and a charge storage capacitor electrically connected to any one of the source / drain regions. In the method for manufacturing a memory element, the method includes: (1) forming a first insulating layer covering the transfer transistor on the substrate; and (2) electrically connecting to one of the source / drain regions. Forming a first conductive layer penetrating at least the first insulating layer, and (3) forming an insulating pillar on the first insulating layer, wherein the insulating pillar has a concave region on both side surfaces thereof. a step of defining a (4) wherein said first insulating layer in the recess region insulating a pole
The method comprising the second layer consisting of a first layer and a conductive material made of an insulating material are alternately formed, further forming a second insulating layer that substantially fills the recessed area on the second film Doo, ( 5) removing the second film lying above the insulating pillar; and (6) an opening formed by etching through at least the second insulating layer, the second film, and the first film.
Forming a second conductive layer that is electrically connected to any one of the source / drain regions via a combination of the first and second conductive layers and the second film. Form the storage electrode
A stage that, (7) the insulating pillars and said second insulating layer and removing the first layer and to the exposed surface of the second layer (8) said first and second conductive layers Forming a dielectric layer; and (9) forming a third conductive layer functioning as a counter electrode of the charge storage capacitor on the dielectric layer. 21. The method according to claim 20 , wherein the second film has a substantially L-shaped cross section and one end thereof is connected to the second conductive layer. 22. The method of claim 21 , wherein said first conductive layer has a substantially T-shaped cross section. 23. The method of claim 21 , wherein said second conductive layer has a substantially U-shaped cross section. 24. The method of claim 20 , further comprising, between the step (1) and the step (2), forming an etching protection layer on the first insulating layer. the method of. 25. The step (3) includes: forming a thick-film insulating layer on the etching protection layer; and forming a photoresist layer on the thick-film insulating layer so that the concave region is exposed. Removing the exposed portion of the thick-film insulating layer in the recessed region; partially eroding the photoresist layer so that the thick-film insulating layer is further partially exposed; Forming the insulating pillar having a stepped cross section by further removing the exposed portion of the thick film insulating layer so that the layer is exposed; and removing the photoresist layer. The method according to claim 24 , characterized in that: 26. The method of claim 25, wherein step (5) A method according to claim 25, characterized by comprising the step of the selected portion to etching of the second layer lying above the insulative pedestal. 27. The method of claim 26, wherein step (5) is, by a chemical mechanical polishing method, according to claim 25, characterized by comprising the step of polishing the selected portion of the second layer lying above the insulative pedestal the method of. 28. The method of claim 20 , wherein step (5) comprises etching the selected portion of the second film overlying the insulating pillar. 29. wherein step (5) is, by a chemical mechanical polishing method, according to claim 20, characterized by comprising the step of polishing the selected portion of the second layer lying above the insulative pedestal the method of. 30. A step of repeating the step (4) to realize the concave region in which two first films made of an insulating material and two second films made of a conductive material are alternately stacked; A second at the top to substantially fill the recessed area
Forming a second insulating layer on the film, and the step (5) comprises: (a) forming the second insulating layer on the insulating pillar so that a part of the uppermost second film on the insulating pillar is exposed Forming a photoresist layer on the upper second film; (b) sequentially removing the uppermost second film and the exposed portion of the uppermost first film; and (c) the uppermost portion. Partially etching the photoresist layer so that another portion of the second film is exposed; (d) removing the another exposed portion of the second film; and (e) serial to claim 20, characterized by comprising the steps of removing the photoresist layer after stage (d)
The method described.