FR2752485A1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE HAVING A CAPACITOR - Google Patents

Abstract

A method for manufacturing a semiconductor memory device having a substrate (10), a transfer transistor formed on the substrate and a charge storage capacitor electrically connected to a source / drain region (16a) of the transfer transistor , includes in particular the formation of a trunk-shaped electrode (26a) and the formation of a branch-shaped electrode (40a) connected to the drain region of the transfer transistor. The formation of the capacitor is completed by the successive formation of a dielectric layer and a conductive layer on the trunk and branch-shaped electrodes (26a, 40a).

Description

METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE HAVING

  The present invention relates generally to semiconductor memory devices, and more particularly relates to a method for manufacturing a structure of a dynamic random access memory (or DRAM) cell having a transfer transistor and a tree type charge storage capacitor. Figure 1 is a circuit diagram of a conventional memory cell for a DRAM device. As shown in the drawing, a DRAM cell essentially consists of a transfer transistor T and a charge storage capacitor C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain of this transistor is connected to a storage electrode 6 of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposite electrode 8 of the capacitor is connected to a constant voltage source. A dielectric film 7 is formed between the storage electrode 6 and the opposite electrode 8. In the process of manufacturing a DRAM device, a practically two-dimensional capacitor, which is called a capacitor. of plan type, is mainly used for a conventional DRAM device with a memory capacity of less than 1 MB (megabyte). In the case of a DRAM device having a memory cell which uses a planar type capacitor, electrical charges are stored on the main surface of a semiconductor substrate, so that the main surface must have a high area. This type of memory cell is therefore not suitable for a DRAM device with a high level of integration. For a DRAM device with a high level of integration,

  like a DRAM device with more than 4 MB of memory, we introduced a three-dimensional capacitor, which is called a stacked or trench type capacitor. With the stacked or trench type capacitor, it was possible to obtain a larger memory capacity in a similar volume. However, to produce a semiconductor device having an even higher level of integration, such as a very high level of integration circuit (or VLSI) having a capacity of 64 MB, a capacitor having such a simple three-dimensional structure, like the stacked type or the conventional trench type, proves to be insufficient. One solution for increasing the electrical capacity of a capacitor consists in using what is called the stacked fin type capacitor, which is proposed by Ema et al. in "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electronic 15 Devices Meeting, pages 592-595, December 1988. The stacked fin-type capacitor includes electrodes and dielectric films which extend horizontally with a fin shape in a set of stacked layers, to increase the surface areas of the electrodes. DRAM devices having the finned type stacked capacitor are also described in U.S. patents. No. 5,071,783; 5,126,810 and 5,206,787. Another solution for improving the electrical capacity of a capacitor is to use the so-called stacked cylindrical type capacitor, which is proposed by Wakamiya et al. in 25 "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989, Symposium on VLSI Technology, Digest of Technical Papers, pages 69-70. The stacked cylindrical type capacitor includes electrodes and dielectric films which extend vertically with a cylindrical shape, to increase the surface areas of the electrodes. A DRAM device having the stacked cylindrical type capacitor is also described in the U.S. Patent. No. 5,077,688. With the trend toward increased integration density, it is necessary to further reduce the size of the DRAM cell in a plane (that is, the area it occupies in a plan). Generally speaking, a reduction in cell size leads to a reduction

  load storage capacity (electrical capacity). In addition, when

  as the electric capacity is reduced, the probability of occurrence of transient errors under the effect of the incidence of a rays is increased. There is therefore a need in this technique relating to the design of a new structure for a storage capacitor which can provide the same electrical capacity, while occupying a smaller area in a plane, and to a suitable method for fabricate the structure.

  It is therefore an object of the invention to provide a method for fabricating a semiconductor memory device with a tree type capacitor structure which provides increased area for charge storage. A preferred embodiment of the invention provides a method for manufacturing a semiconductor memory device having a capacitor. The semiconductor memory device includes a substrate, a transfer transistor formed on the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions of the transfer transistor. The manufacturing process comprises the formation of a first insulating layer on the substrate, covering the transfer transistor, and the formation of a first conductive layer, which penetrates at least through the first insulating layer, and which is electrically connected to one of the source / drain regions of the transfer transistor. A second insulating layer is then formed and a structure of layers stacked on the second insulating layer is formed. A third insulating layer is formed on the side walls of the stacked layer structure, and a fourth insulating layer is formed on the surfaces of the second and third insulating regions. The third and fourth insulating layers and the insulating layer below the third insulating layer are removed until the surface of the first conductive layer is exposed, thereby forming an opening. A second conductive layer is formed on the surfaces of the stacked layer structure and the second insulating layer, filling the opening. The part of the second conductive layer which is above the structure of stacked layers is removed, after which the structure of stacked layers and the part of the second insulating layer which is below it are removed.

  of the structure of stacked layers, until the surface of the first conductive layer is exposed. The first and second conductive layers are defined so that one end of the second conductive layer is connected to the upper surface of the first conductive layer, the first conductive layer forms a trunk-shaped conductive layer, the second layer the conductive layer forms a branch-shaped conductive layer, and the first and second conductive layers in combination form a storage electrode of the charge storage capacitor. The second insulating layer 10 is removed. A dielectric layer is formed on the exposed surfaces of the first and second conductive layers. A third conductive layer is formed on the surface of the dielectric layer, which has the effect of forming an opposite electrode of the charge storage capacitor. According to one aspect of the invention, the trunk-shaped conductive layer is electrically connected to one of the source / drain regions of the transfer transistor, and it can have a cross-section.

  dirty in T or a cross section in U. The branch-shaped conductive layer generally has a hollow cylindrical shape with a cross section in L. According to another aspect of the invention, a protective layer is formed against attack on the first insulating layer, and a fifth insulating layer is formed on the attack protection layer, before forming the first conductive layer, which penetrates through the fifth insulating layer and the protective layer protection against attack. The fifth insulating layer is removed with the second insulating layer. According to a further aspect of the invention, multiple insulating layers, stacked layer structures and conductive layers are formed to define additional branch-shaped conductive layers. Thus, the first conductive layer forms a trunk-shaped conductive layer, while the other conductive layers form at least two branch-shaped conductive layers, with each branch-shaped conductive layer oriented substantially parallel to the others. , and each having one end

  nected on the upper surface of the first conductive layer. All of the residual insulating layers beyond the first insulating layer are removed and a dielectric layer is formed on the exposed surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layers. According to a further aspect of the invention, the part of the second conductive layer which is located above the structure of stacked layers is removed, by chemomechanical polishing or by etching. A second preferred embodiment of the invention provides a method for manufacturing a semiconductor memory device having a capacitor. The semiconductor memory device includes a substrate, a transfer transistor formed on the substrate, and a charge storage capacitor electrically connected to one of the source / drain regions of the transfer transistor. A first insulating layer is formed on the substrate, so as to cover the transfer transistor. A first conductive layer is formed which penetrates at least through the first insulating layer, and which is electrically connected

  only to one of the source / drain regions of the transfer transistor. A second insulating layer and a layer structure stacked on top of the second insulating layer are formed. A third insulating layer is formed on the side walls of the stacked layer structure, and a fourth insulating layer is formed on the surfaces of the second and third insulating layers. The third and fourth insulating layers and the insulating layer which is located below the third insulating layer are removed so as to expose the surface of the first conductive layer, thereby forming an opening. A second conductive layer is formed on the surface of the structure of stacked layers and the second insulating layer, so as to fill the opening. The second conductive layer is defined by removing the part above the structure of stacked layers. The structure of stacked layers is removed and a fifth insulating layer is formed on the surfaces of the second conductive layer and the second insulating layer. The fifth insulating layer is etched until the surface of the first conductive layer is exposed to form

  a second opening. A third conductive layer is formed on the surface of the fifth insulating layer and in the second opening. The third, second and first conductive layers are defined such that respective ends of the third and second conductive layers are connected to the upper surface of the first conductive layer. The first conductive layer forms a trunk-shaped conductive layer, the second conductive layer forms a first branch-shaped conductive layer, and the third conductive layer forms a second branch-shaped conductive layer. The first, second and third conductive layers together form a storage electrode for the charge storage capacitor. The fifth and second insulating layers are removed. A dielectric layer is formed on the bare surfaces of the first, second and third conductive layers. A fourth conductive layer is formed on the surface of the dielectric layer, which has the effect of forming an opposite electrode of the charge storage capacitor. According to yet another aspect of the invention, multiple insulating layers, stacked layer structures and conductive layers are formed to define additional branch-shaped conductive layers. Thus, the first conductive layer forms a trunk-shaped conductive layer, while the other conductive layers form at least two branch-shaped conductive layers, each branch-shaped conductive layer being oriented substantially parallel to the others. , and each region having one end connected to the upper surfaces of the first conductive layer. All residual insulating layers are removed beyond the first insulating layer, and a dielectric layer is formed on the exposed surfaces of the trunk-like conductive layer and branch-like conductive layers. . Other characteristics and advantages of the invention will be better understood on reading the description which follows of preferred embodiments, given by way of nonlimiting examples. The following description refers to the accompanying drawings, in which: Figure 1 is a circuit diagram of a memory cell

  a DRAM device; FIGS. 2A to 2H are sections illustrating a first embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this arrangement.

  5 sitive; FIGS. 3A to 3E are sections illustrating a second embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this arrangement.

  sitive; FIG. 4 is a section illustrating a third embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this device; FIGS. 5A to 5D are sections illustrating a fourth embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this device; FIGS. 6A and 6B are sections illustrating a fifth embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this device; FIG. 7 is a section illustrating a sixth embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this device; and FIGS. 8A to 8E are sections illustrating a seventh embodiment of a semiconductor memory device according to the invention, and a method according to the invention for manufacturing this device. First Preferred Embodiment A first embodiment of a semiconductor memory device having a tree type charge storage capacitor according to the invention will be described, with reference to FIGS. 2A to 2H . Referring to FIG. 2A, it should be noted that thermal oxidation by the LOCOS technique (local silicon oxidation) is applied to a surface of a silicon substrate 10, and a layer is thus formed.

  of field oxide 12 having for example a thickness of approximately 300 nm. Next, a gate oxide layer 14 having a thickness which is for example about 15 nm is formed, by subjecting the silicon substrate 10 to the thermal oxidation treatment. A layer of polycrystalline silicon having a thickness which is for example about 200 nm is then deposited over the entire surface of the silicon substrate 10, using the CVD (chemical vapor deposition) or LPCVD (deposition) process. chemical in vapor phase at low pressure). In order to obtain a polycrystalline silicon layer having a low resistance, suitable impurities, such as for example phosphorus ions, are implanted in the polycrystalline silicon layer. Preferably a layer of refractory metal is deposited on the layer of polycrystalline silicon, after which an annealing treatment is carried out to form a layer of polycrystalline silicon / silicide, so as to further reduce

  15 boosts the resistance of the layer. The refractory metal can be tungsten (W), and its thickness is for example around 200 nm. Next, the polycrystalline silicon / silicide is subjected to a pattern definition process, to form gate electrodes (or word lines) WL1 to WL4, as shown in Figure 2A. Then, for example, arsenic ions are implanted in the silicon substrate 10, for example at an energy of 70 keV and a dose of approximately 1 × 1015 atoms / cm. In this step, the word lines WL1 to WL4 are used as masking layers. As a result, drain regions 16a and 16b and source regions 18a and 18b are formed in the silicon 10 substrate. Referring next to FIG. 2B, it is noted that in the following step a CVD operation is carried out to deposit an insulating layer 20, consisting for example of borophosphosilicate glass (or BPSG), to a thickness which is for example around 700 nm. The same method is then used to form a layer of protection against attack 22, which may for example be a layer of silicon nitride, having a thickness which is for example around 100 nm. After this, a conventional photolithography and etching treatment is carried out to etch off selected parts of the attack protective layer 22, the insulating layer 20 and the

  gate oxide layer 14, so as to form storage electrode contact holes 24a, 24b, which extend from the upper surface of the attack protection layer 22, up to the upper surface of the drain regions 16a and 16b. A CVD operation is then carried out to deposit a polycrystalline silicon layer 26 on the surface of the attack protection layer 22. To increase the conductivity of the polycrystalline silicon layer 26, it is possible to implant, for example, ions of arsenic in the polycrystalline silicon layer 26. As shown in the drawing, the contact holes 10 of the storage electrode 24a, 24b are filled with the polycrystalline silicon layer 26, and the polycrystalline silicon layer 26 further covers the surface of the attack protection layer 22. A thick insulating layer 28, for example made of silicon dioxide, is then deposited on the surface of the polycrystalline silicon layer 26, up to a thickness of approximately 700 nm . Referring next to FIG. 2C, it should be noted that in the following step a CVD operation is carried out to successively deposit an insulating layer and a layer of sacrificial polycrystalline silicon. Then, a photolithography and conventional attack treatment is carried out.

  20 sique to remove by attack selected parts of the insulating layer and the sacrificial polycrystalline silicon layer, to form solid cylindrical insulating layers 30a, 30b and sacrificial polycrystalline silicon layers 32a, 32b, as shown in the drawing. The insulating layers 30a, 30b may for example be layers of silicon nitride deposited up to a thickness of approximately 100 nm. The thickness of the sacrificial polycrystalline silicon layers 32a, 32b may for example be around 100 nm. The insulating layer 30a and the sacrificial polycrystalline silicon layer 32a form in combination a structure of stacked layers 30a, 32a which is preferably located above the corresponding drain region 16a. Similarly, the insulating layer 30b and the sacrificial polycrystalline silicon layer 32b form in combination another structure of stacked layers 30a, 32b, which is preferably located above the corresponding drain region 16b. 35 Referring next to FIG. 2D, it is noted that in the next step

  In particular, spacers of silicon dioxide, 34a and 34b are formed on the side walls of the respective stacked layer structures, 30a, 32a and 30b, 32b. In this embodiment, the silicon dioxide spacers 34a and 34b can be formed by the following steps: first, a layer of silicon dioxide is deposited to a thickness which is, for example, approximately 100 nm, and the thickness of the layer of silicon dioxide is then reduced by attack. After this, a CVD operation is carried out to deposit an insulating layer 36, for example a layer of silicon nitride, to a thickness which is for example around 200 nm. A chemo-mechanical polishing technique (or CMP) is then used to polish the insulating layer 36 until the upper surfaces of the stacked layer structures 30a, 32a and 30b, 32b are exposed. Referring next to FIG. 2E, it is noted that in the next step, the silicon dioxide spacers 34a and 34b are removed by attack, using the masking structures as masking layers. stacked layers 30a, 32a and 30b, 32b and the insulating layer 36. Then, using as masks the same structures of stacked layers 30a, 32a and 30b, 32b and the insulating layer 36, it is attacked that the insulating layer 28 until the surface of the polycrystalline silicon layer 26 is exposed. Then, using the sacrificial polycrystalline silicon layers 32a, 32b as masks, the insulating layer 36 is removed. Openings 38a and 38b are thus formed. Referring next to FIG. 2F, it is noted that in the next step, a layer of polycrystalline silicon 40 is deposited on the surfaces of the structures of stacked layers 30a, 32a and 30b, 32b and on the insulating layer. 28, to a thickness which is for example around 100 nm, also filling the openings 38a and 38b. To increase the conductivity of the polycrystalline silicon layer 40, it is possible, for example, to implant arsenic ions in this layer. Next, the polycrystalline silicon layer 40 and the sacrificial polycrystalline silicon layers 32a, 32b are polished by chemo-mechanical polishing, until the upper surfaces of the insulating layers 30a, 30b are exposed. Referring next to FIG. 2G, it is noted that in the next step

  In particular, using the polycrystalline silicon layer 40 as a mask, a wet etching operation is carried out so as to remove the insulating layers 30a, 30b and then the insulating layer 28 located below. Then, a conventional photolithography and etching treatment is carried out to successively attack the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26, so as to define the storage electrodes of the charge storage capacitors in each memory unit. By the above-mentioned steps, the polycrystalline silicon layers 10 40 and 26 are divided into two sections 40a, 40b and 26a, 26b. Then, a wet attack treatment is again carried out on the wafer, using the attack protection layer 22 for the end point of the attack, so as to remove the rest of the insulating layer 28. The fabrication of the storage electrodes for the charge storage capacitors of the DRAM device is thus completed. As shown in FIG. 2G, each storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 26a / 26b and a layer of polycrystalline silicon in the form of a branch 40a / 40b, having a cross section in L. The layers of polycrystalline silicon in the form of a trunk 26a, 26b are electrically connected to the drain regions res-

  pectives 16a and 16b of the transfer transistors in the DRAM device, and each of these layers has a T cross section. The polycrystalline branch-shaped silicon layers 40a, 40b generally have a hollow cylindrical shape, although their cross section horizontal 25 can be circular, rectangular or any other shape, depending on the shapes of the respective stacked layer structures 30a, 32a and 30b, 32b. The branch-shaped polycrystalline silicon layers 40a and 40b first extend vertically upward from the upper surfaces of the trunk-shaped polycrystalline silicon layers 26a, 26b, over a distance, and they are then extend ho-

  horizontally outward. Due to the particular shape of the storage electrode of the capacitor of the invention, the storage electrodes are hereinafter called "storage electrodes of the ar35 bre" type, and the capacitors which are thus produced are called of 2752485 12 "tree type charge storage capacitors". Referring next to FIG. 2H, it should be noted that in the next step, dielectric films 42a, 42b are respectively formed on the exposed surfaces of the storage electrodes 26a, 40a and 26b, 40b. The dielectric films 42a, 42b can consist for example of silicon dioxide, silicon nitride, NO (silicon nitride / silicon dioxide), ONO (silicon dioxide / silicon nitride / silicon dioxide), or others. Next, an opposite electrode 44 of polycrystalline silicon is formed on the surfaces of the dielectric films 42a, 42b. The process for the formation of the opposite electrode 44 comprises a first step which consists in depositing a layer of polycrystalline silicon by CVD, up to a thickness which is for example about 100 nm, a second step consisting in diffusing N-type impurities in the polycrystalline silicon layer, so as to increase the conductivity, and a third step consisting in carrying out a conventional photolithography and etching treatment, for etching away selected parts of the silicon layer polycrystalline. The fabrication of the tree type charge storage capacitor in the DRAM device is then completed. Although not shown in Figure 2H, to complete the fabrication of the DRAM chip, subsequent steps include the fabrication of bit lines, patch pads, interconnections and passivations, as well than conditioning. These steps involve only conventional techniques and do not fall within the spirit and the scope of the invention, which means that no detailed description will be presented here. Second Preferred Embodiment In the first preceding embodiment, the trunk-shaped polycrystalline silicon layer has a solid structure with a T-shaped cross section. In the following embodiment, a different manufacturing process is used to form a storage electrode with a different structure, in which the trunk-shaped polycrystalline silicon layer has a hollow structure, so as to increase the surface area of the storage electrode. FIGS. 3A to 3E illustrate a second embodiment

  a semiconductor memory device having a tree type charge storage capacitor according to the invention. This embodiment of the semiconductor memory device can be produced by a second preferred method for manufacturing a 5 semiconductor memory device according to the invention. The tree-type storage electrode of the second embodiment is based on the wafer structure of Figure 2A, using a different manufacturing method to produce a DRAM device storage electrode with a different structure. The elements 10 of FIGS. 3A to 3E which are identical to those of FIG. 2A are designated by the same reference numerals. Referring to Figure 3A in conjunction with Figure 2A, it is noted that a CVD operation is carried out to deposit an insulating layer 46, consisting for example of borophosphosilicate glass (or BPSG), to a thickness which is about 700 nm. Next, a layer of protection against attack 48, for example made of silicon nitride, having a thickness of approximately 100 nm is deposited. Then, a conventional photolithography and etching treatment is carried out to successively remove, by etching, selected parts of the attack protection layer 48, of the insulating layer 46 and of the gate oxide layer 14 , so as to form storage electrode contact holes 50a and 50b which extend from the upper surface of the attack protection layer 48, up to the upper surface of the drain regions 16a and 16b. A layer of polycrystalline silicon 52 is then deposited on the attack protection layer 48. Next, a thick insulating layer 54, for example a layer of silicon dioxide, is deposited on the surface of the polycrystalline silicon layer 52. up to a thickness of about 700 nm. A CVD operation is again carried out to successively deposit an insulating layer and a sacrificial polycrystalline silicon layer on the upper surface of the insulating layer 54, and then a conventional photolithography and etching treatment is carried out to define the insulating layer and the sacrificial polycrystalline silicon layer, so as to form the insulating layer 56 and the sacrificial polycrystalline silicon layer 58, as shown in the drawing. Layer

  insulator 56 may for example be a layer of silicon nitride deposited up to a thickness which is for example around 100 nm. The insulating layer 56 and the sacrificial polycrystalline silicon layer 58 form in combination a structure of stacked layers 56, 58, which is preferably located above and between two adjacent charge storage capacitors. Referring next to FIG. 3B, it should be noted that in the next step, silicon dioxide spacers 60a and 60b are formed on the respective side walls of the stacked layer structure 56, 58. In this embodiment, the spacers in silicon dioxide 60a and 60b can be formed by the following steps: firstly, a layer of silicon dioxide is deposited up to a thickness of approximately 100 nm, after whereby an attacking operation is carried out to reduce the thickness of the layer of silicon dioxide. Next, a CVD operation is carried out to deposit an insulating layer 62, for example a layer of silicon nitride, to a thickness of about 200 nm. chemo-mechanical polishing is then carried out to polish the insulating layer 62 at least until the upper surface of the stacked layer structure 56, 58 is exposed. Referring then to FIG. 3C, it is noted that in the following step, using as attack masks the structures of stacked layers 56, 58 and the insulating layer 62, the elements are removed by attack. - spacing elements in silicon dioxide 60a and 60b. After this, again using as attack masks the coating structures

  ches stacked 56, 58 and the insulating layer 62, we attack the insulating layer 54 until we reach the surface of the polycrystalline silicon layer 52. Then, using as an attack mask the layer As a sacrificial polycrystalline silicon 58, the insulating layer 62 is removed by attack. Openings 64a and 64b are thus formed. Referring next to FIG. 3D, it is noted that a layer 66 consisting of polycrystalline silicon, having a thickness of approximately 100, is deposited on the surfaces of the structures of stacked layers 56, 58 and of the insulating layer 54. nm, also filling the openings 64a and 64b. We then perform a

  chemo-mechanical polishing of the polycrystalline silicon layer and of the sacrificial polycrystalline silicon layers 58, at least until the upper surface of the insulating layer 56 is exposed, so as to form polycrystalline silicon layers 66a and 66b. To increase the conductivity of the polycrystalline silicon layers, it is possible, for example, to implant arsenic ions in the polycrystalline silicon layers. Referring next to FIG. 3E, it will be noted that in the following step, using the polycrystalline silicon layers 66a and 66b as masks, an etching treatment is carried out for successively remove the insulating layer 56 and the insulating layer 54 which is below. Then, a conventional photolithography and etching treatment is carried out to attack the layers of poly-

  crystalline 66a, 66b and the polycrystalline silicon layer 52, so as to define the storage electrodes of the charge storage capacitors in each memory unit. The polycrystalline silicon layers 66a, 66b are attacked above the respective drain regions 16a, 16b. We attack the polycrystalline silicon layer 52 between the

  drain regions 16a, 16b. The steps mentioned above have the effect of dividing the polycrystalline silicon layers 66a, 66b and 52 into sections 66a, 66b and 52a, 52b. Then, a dry attack treatment is again applied to the wafer, using the attack protection layer 48 as the end point of the attack, so as to remove the rest of the insulating layer 54. The fabrication of the electrodes for storing the charge storage capacitors in the DRAM device is thus completed. As shown in FIG. 3E, the storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 52a / 52b and a layer of polycrystalline silicon in the form of a branch 66a / 66b, having a cross section in L. The layers of trunk-shaped polycrystalline silicon 52a, 52b are respectively

  electrically connected to the drain regions 16a and 16b of the transfer transistors in the DRAM device, and they have a U-shaped cross section. The branch-shaped polycrystalline silicon layers 66a, 66b generally have a hollow cylindrical shape, although their horizontal section can be circular, rectangular, or of any

  what other form. The branch-shaped polycrystalline silicon layers 66a, 66b first rise vertically a certain distance from the upper peripheral surface of the trunk-shaped polycrystalline silicon layers 52a, 52b, and they extend - 5 continued horizontally inward. Subsequent processing steps do not differ from conventional processes, and therefore are not described here. Third Preferred Embodiment The foregoing first and second embodiments include branch-shaped electrode layers with L-shaped cross-sections. In cross-section, the branch-shaped electrode layers define two of these. branches. The invention is however not limited to such a configuration. The number of L-shaped branches shown in a cross section of the branch-shaped electrode layer 15 can be only one. In the following embodiment, a storage electrode is described having a branch-shaped electrode having a single branch having a cross section in L. Figure 4 shows a third embodiment of a memory device with semiconductors having a tree type charge storage capacitor according to the invention. This embodiment of the semiconductor memory device can be produced by a third preferred method for manufacturing a semiconductor memory device according to the invention. The tree-type storage electrode of the third embodiment is based on the wafer structure of Figure 3D, and it uses a different manufacturing method to produce a DRAM device storage electrode with a different structure. The elements of FIG. 4 which are identical to those of FIG. 3D are designated by the same reference numbers. Referring to FIG. 3D, jointly with FIG. 4, it is noted that by using the polycrystalline silicon layers 66a, 66b as a mask, a wet attack treatment is carried out to successively remove the layer insulating 56 and the insulating layer 54 35 located below. Then, we carry out a conventional processing of

  photolithography and attack to attack the layers of poly- silicon

  crystalline 66a, 66b and the polycrystalline silicon layer 52, so as to define a storage electrode of the charge storage capacitor in each memory unit. The polycrystalline silicon layers 66a, 66b are etched to remove a vertical end from each layer. The polycrystalline silicon layer 52 is attacked to remove a part located between the drain regions 16a, 16b. The steps mentioned above have the effect of dividing the polycrystalline silicon layer 52 into sections 52a and 52b, and the poly-

  10 crystalline 66a and 66b have a single end connected to the respective polycrystalline silicon layers 52a and 52b. Then, a wet attack treatment is carried out again, using the attack protection layer 48 as the final attack point, to remove the remaining insulating layer 54. The fabrication of the storage electrodes 15 of the charge storage capacitors in the DRAM device is thus completed. As shown in FIG. 4, the storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 52a / 52b, and a layer of polycrystalline silicon in the form of a branch 66a / 66b, having a cross section in L. The layers of trunk-shaped polycrystalline silicon 52a, 52b are electrically connected to the respective drain regions 16a and 16b of the transfer transistors in the DRAM device, and they have T-shaped cross sections. The branch-shaped polycrystalline silicon layers 66a, 66b each have a single branch with an L-shaped cross section, and this branch first rises vertically a certain distance from the upper peripheral edge of the polycrystalline silicon layers.

  trunk-shaped flax 52a, 52b, and then it extends horizontally to another peripheral edge of the trunk-shaped polycrystalline silicon layer 52a, 52b respectively. Subsequent processing steps 30 do not differ from conventional processes, and therefore are not

  write more here. Fourth preferred embodiment In the first, second and third previous embodiments, the storage electrode has only a single electrode layer 35 in the form of a branch with a cross section in L. However, the

  The number of layers of branch-shaped electrodes with L-shaped cross sections is not limited to only one, and it can be two, three, or more, for each storage electrode. In the following embodiment, there is described a storage electrode with two branch-shaped electrode layers, each having a cross section in L. Figures 5A to 5D illustrate a fourth embodiment of a memory device semiconductor having a tree type charge storage capacitor according to the invention. This embodiment of the semiconductor memory device can be manufactured by a fourth preferred method for manufacturing a semiconductor memory device according to the invention. The tree-type storage electrode of the fourth embodiment is based on the wafer structure of Figure 2F, using a different manufacturing process to produce a DRAM device storage electrode with a different structure. The elements of FIGS. 5A to 5D which are identical to those of FIG. 2F are designated by the same reference numerals. Referring to Figure 2F in conjunction with Figure 5A, it is noted that in the next step, using the polycrystalline silicon layer 40 as a mask, a wet etching operation is carried out to remove the insulating layers 30a, 30b. Next, an insulating layer 68, for example made of silicon dioxide, is deposited on the surfaces of the polycrystalline silicon layer 40 and of the insulating layer 25 28. Then, successively is deposited on the surface of the insulating layer 68 an insulating layer and a sacrificial polycrystalline silicon layer. Using conventional photolithography and etching treatment, the insulating layer and the sacrificial polycrystalline silicon layer are defined so as to form the insulating layers 70a, 70b and the sacrificial polycrystalline silicon layers 72a, 72b which are represented. - felt on the drawing. The insulating layers 70a, 70b may for example be a layer of silicon nitride deposited with a thickness of approximately 100 nm. The sacrificial polycrystalline silicon layers 72a, 72b are formed with a thickness which is for example about 100 nm. The insulating layer 70a and the sacrificial polycrystalline silicon layer

  these 72a together form a stacked layer structure 70a, 72a, which is preferably placed above the corresponding drain region 16a. Similarly, the insulating layer 70b and the silicon layer

  Polycrystalline sacrificial cium 72b together form another structure 5 of stacked layers 70b, 72b, which is preferably placed above the corresponding drain region 16b. Next, silicon dioxide spacers 74a and 74b are formed on the respective side walls of the stacked layer structures 70a, 72a and 70b, 72b. In this embodiment, the silicon dioxide spacers 74a and 74b can be formed by the following steps:

  mire, depositing a layer of silicon dioxide to a thickness which is for example about 100 nm, and then reduces by attack the thickness of the layer of silicon dioxide. Referring next to FIG. 5B, it is noted that in the following step, a CVD operation is carried out to deposit an insulating layer 76, for example made of silicon nitride, with a thickness of about - ron 200 nm. Chemo-mechanical polishing is then carried out to polish the insulating layer 76 at least until the upper surfaces of the stacked layer structures 70a, 72a and 70a, 72b are exposed. After this, by using as stack masks the structures of stacked layers 70a, 72a and 70a, 72b and the insulating layer 76, the silicon dioxide spacers 74a and 74b are removed by attack. Then, again using the stacked layer structures 70a, 72a and 70a, 72b and the insulating layer 76 as attack masks, the insulating layers 68 and 28 are attacked until the surface of the layer polycrystalline silicon 26 is reached, so as to form openings 78a and 78b. Referring next to FIG. 5C, it will be noted that in the following step, using the sacrificial polycrystalline silicon layers 72a, 72b as attack masks, the insulating layer 76 is removed by attack. Next, a layer of polycrystalline silicon 80 is deposited on the surfaces of stacked layers 70a, 72a and 70a, 72b and of the insulating layer 68, up to a thickness which is for example around 100 nm, also filling the openings 78a and 78b. To increase the conductivity of the polycrystalline silicon layer 80, it is possible to implant

  ter for example arsenic ions in the polycrystalline silicon layer

  flax 80. Next, a chemo-mechanical polishing operation is carried out to polish the polycrystalline silicon layer 80 and the silicon layers.

  sacrificial polycrystalline cium 70a, 72a and 70a, 72b, at least until the upper surfaces of the insulating layers 70a, 70b are exposed. Then, using the polycrystalline silicon layer 80 as a mask, a wet etching operation is carried out to successively remove the insulating layers 70a, 70b and the insulating layers 68 and 28 located below. Referring next to FIG. 5D, it is noted that in the following step, a conventional photolithography and attack treatment is carried out to successively attack the polycrystalline silicon layer 80, the insulating layer 68, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26, so as to define a storage electrode of the charge storage capacitor in each memory unit. Thus, by the steps mentioned above, the polycrystalline silicon layers 80, 40 and 26 are divided into sections 80a, 80b; 40a, 40b and 26a, 26b, as shown in the drawing. Next, wet attack treatment is carried out to remove the remaining insulating layers 68 and 28, using the attack protective layer 22 as the end point of the attack. The fabrication of a storage electrode for a charge storage capacitor in a DRAM device is thus completed. As shown in FIG. 5D, the storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 26a / 26b and two layers of polycrystalline silicon in the form of branches 80a / 80b and 40a / 40b, each having a cross section transverse in L. The trunk-shaped polycrystalline silicon layers 26a, 26b are electrically connected to the respective drain regions 16a and 16b of the transfer transistors in the device.

  30 tif DRAM, and they have cross sections in T. The two layers of polycrystalline silicon in the form of branch 80a, 80b and 40a, 40b are generally parallel to each other and they have cylindrical shapes hollow, and horizontal cross sections which may be circular, rectangular or any other shape. The 35 layers of polycrystalline branch-shaped silicon 80a, 80b and 40a,

  40b extend vertically upward respectively from the upper surface of the polycrystalline silicon layers 26a, 26b, over a distance, and then extend horizontally outward. The following processing steps do not differ from conventional procedures, and therefore are not described here. If more than two branch-shaped electrode layers are required, additional branches can be made by repeated application of formations of stacked layer structures in accordance with the process described in connection with this embodiment. Fifth embodiment In the first to fourth preceding embodiments, the electrode layers in the form of a branch of the storage electrode all have L-shaped cross sections. The invention is not however limited to such an arrangement. form. The branch electrode layers of the storage electrode may have various other cross-sectional shapes. In the following embodiment, a branch-shaped electrode layer of the storage electrode has an L-shaped cross section, while another has a T-shaped cross section. Figures 6A and 6B illustrate a fifth embodiment 20 of a semiconductor memory device having a tree type charge storage capacitor according to the invention. This embodiment of the semiconductor memory device can be manufactured by a fifth preferred method for manufacturing a semiconductor memory device according to the invention. The tree type storage electrode of the fifth embodiment is based on the wafer structure of Figure 2F, using a different manufacturing process to produce a DRAM device storage electrode with a different structure. The elements of FIGS. 6A and 6B which are identical to those of FIG. 2F are desi-

  30 earned by the same reference numbers. Referring to FIG. 2F in conjunction with FIG. 6A, it is noted that during the next step, using the polycrystalline silicon layer 40 as a mask, a wet etching operation is carried out to remove the insulating layers 30a, 30b. A CVD operation is then carried out to deposit an insulating layer 82, by

  example a layer of silicon dioxide, on the surfaces of the insulating layer 28 and of the polycrystalline silicon layer 40. A conventional photolithography and etching treatment is then carried out to successively attack selected parts of the insulating layer 5 82 and the insulating layer 28, until the surface of the polycrystalline silicon layer 26 is reached, thereby forming openings 84a and 84b. The openings 84a and 84b are preferably located respectively in positions above the corresponding drain regions 16a and 16b. A CVD operation is then performed to deposit a layer of polycrystalline silicon 86, for example up to a thickness of about 100 nm, on the surface of the insulating layer 82, so as to fill the openings 84a and 84b. To increase the conductivity of the polycrystalline silicon layer 86, it is possible, for example, to implant arsenic ions in the polycrystalline silicon layer 86. Referring next to FIG. 6B, it is noted that in the next step A conventional photolithography and attack treatment is carried out in order to successively attack the polycrystalline silicon layer 86, the insulating layer 82, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26, so defining a storage electrode for the charge storage capacitor in each memory unit. The steps mentioned above have the effect of dividing the polycrystalline silicon layers 86, 40 and 26 into sections 86a, 86b; 40a, 40b; and 26a, 26b, as shown in the drawing. Next, a wet attack operation is carried out using the attack protective layer 22 for the end point of the attack, so as to remove the insulating layers 82 and 28. The manufacture of the storage electrodes charge storage capacitors in the DRAM device is therefore completed. As shown in FIG. 6B, the storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 26a / 26b, a layer of polycrystalline silicon in the form of a branch 40a: 40b having a cross section in L, and another layer of branch-shaped polycrystalline silicon 86a / 86b having a T-shaped cross-section. The trunk-shaped polycrystalline silicon layers 26a, 26b are electrically connected to the respective drain regions 16a and 16b of the transfer transistors in the device

  DRAM, and they have a T cross section. The branch-shaped polycrystalline silicon layers 40a, 40b having an L cross section generally have a hollow cylindrical shape, although the horizontal cross section may be circular, rec- 5 tangular or any other form. The branch-shaped polycrystalline silicon layers 40a, 40b rise vertically a certain distance from the upper surface of the trunk-shaped polycrystalline silicon layers 26a, 26b, and then extend horizontally towards the 'outside. The vertical sections of the branch-shaped polycrystalline silicon layers 86a, 86b generally have a hollow cylindrical shape, although the horizontal cross-section may be circular, rectangular or any other shape. The branch-shaped polycrystalline silicon layers 86a, 86b rise vertically a certain distance from the upper surface of the trunk-shaped polycrystalline silicon layers 26a, 26b, and then extend horizontally towards the outside. Sixth preferred embodiment In the following sixth embodiment, a different method is used to form a storage electrode having a different structure. The structure of the storage electrode of this embodiment is very similar to that of the fifth embodiment. The difference lies in the branch-shaped polycrystalline silicon layer, which has a pillar structure in this embodiment, instead of having a T cross section, as in the fifth embodiment. The tree-type storage electrode of the sixth embodiment is based on the wafer structure of Figure 6A, using a different manufacturing method to produce a DRAM device storage electrode with a different structure. The elements in FIG. 7 which are identical to those in FIG. 6A are designated by the same reference numbers. Referring to Figure 6A in conjunction with Figure 7, it is noted that chemo-mechanical polishing is used to polish the layer 35 of polycrystalline silicon 86 at least until the upper surface

  of the insulating layer 82 is exposed, so as to form layers of polycrystalline silicon in pillar 88a and 88b, as shown in the drawing. A wet attack treatment is then carried out using, as a mask, the polycrystalline silicon layer 40, to remove the insulating layer 82 and the exposed part of the insulating layer 28. Next, a conventional photolithography treatment is carried out. and attacking to successively attack selected parts of the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26, until the surface of the protective layer 10 attack 22 is laid bare. A storage electrode for the charge storage capacitor in each memory unit is thus defined. The steps mentioned above have the effect of dividing the polycrystalline silicon layers 40 and 26 into sections 40a, 40b and 26a, 26b, as shown in the drawing. Then using the cou-

  15 che of protection against attack 22 as an end point of the attack, a wet attack treatment is again carried out to remove by attack the insulating layer 28. The manufacture of the storage electrodes of the storage capacitors charging in the DRAM device is thus completed. As shown in FIG. 7, the storage electrode 20 comprises a layer of polycrystalline silicon in the form of a trunk 26a, 36b, a layer of polycrystalline silicon in the form of a branch 40a / 40b having a cross section in L, and a layer of branch-shaped polycrystalline silicon in the form of a pillar, 88a / 88b. The trunk-shaped polycrystalline silicon layers 26a, 25 36b are electrically connected to the respective drain regions 16a and 16b of the transfer transistors in the DRAM device. The branch-shaped polycrystalline silicon layers 40a, 40b which have an L-shaped structure generally have a hollow cylindrical shape, although the horizontal cross section may be circular, rectangular or any other shape. Poly- silicon layers

  crystal in the form of a branch 40a, 40b rise vertically over a certain distance from the upper surface of the trunk-shaped polycrystalline silicon layers 26a, 26b, and they then extend horizontally outwards. The branch-shaped polycrystalline silicon layers 88a, 88b in the form of pillars rise vertically.

  ment from the upper surface of the trunk-shaped polycrystalline silicon layers 26a, 26b and they have a horizontal cross section which can be circular, rectangular or any other shape. Seventh preferred embodiment In the first to sixth preceding embodiments, the bottom surface of the horizontal portion of the poly- silicon layer

  The trunk-like lens is in contact with the attack protection layer, and a micro mechanical chi10 polishing technique is also used to remove and cut the polycrystalline silicon layer above the stacked layer structures. The invention is however not limited to the above. In the following embodiment, the lower surface of the horizontal part of the poly-

  The trunk-shaped lens is separated by a certain distance from the attack protective layer below, so as to increase the surface area of the storage electrode. Another technique is also described, such as the use of a conventional photolithography and etching treatment, for dividing the layer of polycrystalline silicon lying above the structure of stacked layers. FIGS. 8A to 8E illustrating a seventh embodiment of a semiconductor memory device having a tree type charge storage capacitor according to the invention. This embodiment of the semiconductor memory device is produced by a seventh preferred method for manufacturing a semiconductor memory device according to the invention. The tree-type storage electrode of the seventh embodiment is based on the wafer structure of Figure 2A, using a different manufacturing method to produce a DRAM device storage electrode with a different structure. The elements 30 of FIGS. 8A to 8E which are identical to those of FIG. 2A are designated by the same reference numerals. Referring to FIG. 2A, in conjunction with FIG. 8A, it is noted that a CVD operation is carried out to deposit an insulating layer 90, a protective layer against attack 92 and an insulating layer 94. The layer insulating 90 may consist for example of a

  layer of borophosphosilicate glass (or BPSG) deposited with a thickness of approximately 700 nm. The attack protection layer 92 may for example be a layer of silicon nitride deposited with a thickness of approximately 100 nm. The insulating layer 94 may for example be a layer of silicon dioxide deposited with a thickness of approximately 100 nm. A conventional photolithography and etching treatment is then carried out to selectively attack, in succession, the insulating layer 94, the attack protection layer 92, the insulating layer 90 and the gate oxide layer. 14. This has the effect of forming storage electrode contact holes 96a and 96b. The storage electrode contact holes 96 and 96b extend from an upper surface of the insulating layer 94, to an upper surface of the respective drain regions 16a and 16b. A layer of polycrystalline silicon is then deposited on the surface of the insulating layer 94, by filling the contact holes of storage electrode 96a and 96b. After this, a conventional photolithography and etching treatment is again carried out in order to define the polycrystalline silicon layer, so as to form the polycrystalline silicon layer 98 as shown in the drawing. To increase the conductivity of the polycrystalline silicon layer, it is possible, for example, to implant arsenic ions in the polycrystalline silicon layer. As shown in FIG. 8A, the polycrystalline silicon layer 98 fills the contact holes of storage electrode 96a and 96b and it also covers the surface of the insulating layer 94. An insulating layer 100 is then deposited, for example a silicon dioxide layer, on the surface of the polycrystalline silicon layer 98, to a thickness of about 700 nm.

  Referring next to FIG. 8B, it will be noted that in the following step, an insulating layer and a sacrificial polycrystalline silicon layer are successively deposited on the surface of the insulating layer 100. A conventional treatment is then carried out. photolithography and etching to define the insulating layer and the sacrificial polycrystalline silicon layer, so as to form insulating layers of solid cylindrical shape, 102a, 102b, and sacrificial polycrystalline silicon layers 104a, 104b, as shown in the drawings . The horizontal cross sections of the insulating layers 102a and 102b and

  sacrificial polycrystalline silicon layers 104a, 104b can be circular, rectangular or any other shape. The insulating layers 102a, 102b may for example be layers of silicon nitride deposited up to a thickness of approximately 100 nm. The 5 sacrificial polycrystalline silicon layers 104a, 104b are deposited to a thickness which is for example around 100 nm. The insulating layer 102a and the sacrificial polycrystalline silicon layer 104a jointly form a stacked layer structure 102a, 104b, which is preferably located in a position above the corresponding drain region 16b. Similarly, the insulating layer 102b and the sacrificial polycrystalline silicon layer 104b together form a structure of stacked layers 102b, 104b, which is preferably located in a position above the corresponding drain region 16b. Next, silicon dioxide spacers 106a, 106b are formed on the side walls of the respective stacked layer structures 102a, 104a and 102b, 104b. In this embodiment, the spacers of silicon dioxide 106a and 106b can be formed by the following steps: firstly, a layer of silicon dioxide is deposited with a thickness which is for example around 100 nm, after which is reduced by attack the thickness of the silicon dioxide layer. A CVD operation is then carried out to deposit an insulating layer 108, for example a layer of silicon nitride, to a thickness of approximately 200 nm. Chemo-mechanical polishing is then performed to polish the insulating layer 108, at least until the top surface of the stacked layer structures 102a, 104a and 102b, 104b is exposed. Referring next to FIG. 8C, it is noted that in the next step, using as stacking masks the structures of stacked layers 102a, 104a and 102b, 104b and the insulating layer 108, we remove 30 by attacking the silicon dioxide spacers 106a and 106b. Then, using as attack masks the same stacked layer structures 102a, 104a and 102b, 104b, and the same insulating layer 108, the insulating layer 100 is attacked until the surface of the silicon layer polycrystalline 98 is reached. Then,

  using the polycrystalline silicon layers as attack masks

  sacrificial lin 104a, 104b, the insulating layer 108 is removed by attack. Openings 110a and 110b are thus formed. Referring next to FIG. 8D, it is noted that in the following step, a layer of polycrystalline silicon 112 is deposited on the surfaces of the stacked layer structures 102a, 104a and 102b, 104b and of the layer. insulating 100, for example up to a thickness of about 100 nm, and also so as to fill the openings 100a and 110b. To increase the conductivity of the polycrystalline silicon layer 112, it is possible, for example, to implant arsenic ions in the polycrystalline silicon layer 112. After this, a conventional photolithography and etching treatment is carried out to define the layer of polycrystalline silicon 112 and the sacrificial polycrystalline silicon layers 104a, 104b. As a result, the parts which are located above the insulating layers 102a, 102b are divided to form the structure which is shown

  15 felt in the drawing. Referring next to FIG. 8E, it is noted that in the following step, using as masks the polycrystalline silicon layer 112 and the sacrificial polycrystalline silicon layers 104a, 104b, an operation is carried out. wet etching to successively remove, by etching, the insulating layers 102a, 102b and the iso-layer

  aunt 100 lying below. A conventional photolithography and etching treatment is then carried out in order to successively attack the polycrystalline silicon layer 112, the insulating layer 100 and the polycrystalline silicon layer 98, so as to define a storage electrode for the storage storage capacitor charge for each memory unit. The above steps have the effect of dividing the polycrystalline silicon layers 112 and 98 into sections 112a, 112b and 98a, 98b. Then, using the attack protection layer 92 as the end point of the attack, an attack treatment 30 is again carried out to remove the insulating layers 100 and 94. The manufacture of a storage electrode charge storage capacitor in the DRAM device is therefore complete. As shown in FIG. 8E, the storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 98a / 98b and a layer of polycrystalline silicon in the form of a branch 112a / 112b, having a cross section in T. The layers

  of trunk-shaped polycrystalline silicon 98a, 98b are electrically connected to the respective drain regions 16a, 16b of the transfer transistors in the DRAM device. A distance is maintained between the lower surfaces of the horizontal section of the trunk-shaped polycrystalline silicon layers 5 and the upper surfaces of the attack protection layer 92, in order to increase the surface area of the storage electrode. The branch-shaped polycrystalline silicon layers 112a, 112b generally have a hollow cylindrical shape, although the horizontal cross-section may be circular, rectangular or any other shape. The branch-shaped polycrystalline silicon layers 112a, 112b rise vertically a certain distance from the upper surfaces of the trunk-shaped polycrystalline silicon layers 98a, 98b, and then extend horizontally towards the outside.

It will be apparent to specialists in the field of semiconductor manufacturing that the embodiments described above can be applied alone or in combination, so as to provide storage electrodes of various sizes and shapes on a single DRAM chip. It is considered that all of these variants fall within the scope of the invention. Although in the accompanying drawings, the embodiments of the drains of the transfer transistors are based on diffusion zones in a silicon substrate, other variants, such as for example trench-type drain regions, are possible.

The elements in the accompanying drawings are schematic representations for illustrative purposes only, and therefore are not shown on an actual scale. The shapes, dimensions and angles of extension of the elements in the invention which are shown do not constitute limitations of the scope of the invention.

It goes without saying that many other modifications can be made to the device described and shown, without departing from the scope of the invention.

Claims (21)

  1. A method of manufacturing a semiconductor memory device having a substrate (10), a transfer transistor formed on the substrate, and a charge storage capacitor electrically connected to a source / drain region ( 16a, 18a; 16b, 18b) of the transfer transistor, characterized in that it comprises the following steps: (a) forming a first insulating layer (20) covering the transfer transistor on the substrate; (b) forming a first conductive layer (26) which penetrates at least through the first insulating layer (20) and which is electrically connected to the source / drain region (16a, 18a; 16b, 18b) of the transfer transistor ; (c) forming a second insulating layer (28) on the first conductive layer; (d) forming a structure of stacked layers (30a, 32a; 30b, 32b) on the second insulating layer (20); (e) forming a third insulating layer (34a, 34b) on side walls of the stacked layer structure; (f) forming a fourth insulating layer (36) on exposed surfaces of the second and third (28, 34a, 34b) insulating layers; (g) removing the third and fourth insulating layers (34a, 34b; 36) and part of the second insulating layer (28) lying below the third insulating layer, until a part the surface of the first conductive layer (26) is exposed, thereby forming an opening (38a, 38b); (h) forming a second conductive layer (40) on surfaces of the stacked layer structure (30a, 32a; 30b, 32b) and the second insulating layer (28) and filling the opening (38a, 38b) ; (i) removing a portion of the second conductive layer (40) above the structure of stacked layers; (j) removing the structure of stacked layers (30a, 32a; 30b, 32b); (k) removing part of the second insulating layer (28) below a region in which the stacked layer structure was located, to expose the surface of the first conductive layer (26) ; (I) the first and second conductive layers (26, 40) are defined so that a first end of the second conductive layer is connected to an upper surface of the first conductive layer, the first conductive layer forming a trunk-shaped conductive layer (26a, 26b) and the second conductive layer forming a branch-shaped conductive layer (40a, 40b), and the first and second conductive layers forming in combination a storage electrode of the storage capacitor dump; (m) removing a remaining part of the second insulating layer (28); (n) forming a dielectric layer (42a, 42b) on surfaces u of the first and second conductive layers; and (o) forming a third conductive layer (44) on a surface of the dielectric layer, to form an opposite electrode of the charge storage capacitor.   2. The method of claim 1, further comprising forming an attack protective layer (92) over the first insulating layer (90), and forming a fifth insulating layer (94) on the attack protection layer, after step (a) and before step (b); characterized in that step (b) further comprises a step of forming a first conductive layer (98) which penetrates through the fifth insulating layer (94) and the attack protection layer (92 ); and step (m) further comprises a step of removing the fifth insulating layer (94).   3. Method according to claim 1, in which steps (c) to (j) define a method for manufacturing a predefined branch-shaped conductive layer (40) of the charge storage capacitor, characterized in that it comprises in addition to manufacturing at least one additional predefined branch-shaped conductive layer (80), after step (j), step (I) further comprising the definition of each predefined branch-shaped conductive layer additional (80), so that a respective first end of each predefined branch-shaped conductive layer is connected to the upper surface of the first conductive layer, to form an additional branch-shaped conductive layer (80), step (m) further comprising removing remaining portions of any insulating layer, and step (n) further comprising forming a dielectric layer on exposed surfaces of each cond layer additional branch-shaped unit (80).   The method of claim 3, further comprising forming an attack protective layer (92) over the first insulating layer (90), and forming a fifth insulating layer (94). on the attack protection layer, after step (a) and before step (b); characterized in that step (b) further comprises a step of forming a first conductive layer (98) which penetrates through the fifth insulating layer (94) and the attack protection layer (92 ); and step (I) further comprises a step of removing the fifth insulating layer (94).   5. Method for manufacturing a semiconductor memory device having a substrate (10), a transfer transistor formed on the substrate, and a charge storage capacitor electrically connected to a source / drain region ( 16a, 18a; 16b, 18b) of the transfer transistor, characterized in that it comprises the following steps: (a) forming a first insulating layer (20) covering the transfer transistor on the substrate; (b) forming a first conductive layer (26) which penetrates at least through the first insulating layer (20) and which is electrically connected to the source / drain region (16a, 18a; 16b, 18b) of the transfer transistor ; (c) forming a second insulating layer (28) on the first conductive layer; (d) forming a structure of stacked layers (30a, 32a; 30b, 32b) on the second insulating layer (20); (e) forming a third insulating layer (34a, 34b) on side walls of the stacked layer structure; (f) forming a fourth insulating layer (36) on exposed surfaces of the second and third (28, 34a, 34b) insulating layers; (g) removing the third and fourth insulating layers (34a, 34b; 36) and part of the second insulating layer (28) lying below the third insulating layer, until a part the surface of the first conductive layer (26) is exposed, thereby forming an opening (38a, 38b); (h) forming a second conductive layer (40) on surfaces of the stacked layer structure (30a, 32a; 30b, 32b) and the second insulating layer (28) and filling the opening (38a, 38b) ; (i) removing a portion of the second conductive layer (40) above the structure of stacked layers; (j) removing the structure of stacked layers (30a, 32a; 30b, 32b); (k) forming a fifth insulating layer (68) on exposed surfaces of the second conductive layer (40) and the second insulating layer (28); (I) attacking the fifth insulating layer (68) until part of the surface of the first conductive layer (26) is exposed, which forms a second opening (78a, 78b); (m) forming a third conductive layer (80) on the surface of the fifth insulating layer (68) and in the second opening (78a, 78b); (n) defining the third and second and first conductive layers so that respective first ends of the third and second conductive layers (80, 40) are connected to the upper surface of the first conductive layer (26), the first conductive layer forming a trunk-shaped conductive layer (26a, 26b), the second conductive layer forming a first branch-shaped conductive layer (40a, 40b), and the third conductive layer forming a second conductive shaped layer branch (80a, 80b), and the first, second and third conductive layers together forming a storage electrode of the charge storage capacitor; (o) removing remaining parts of the fifth (68) and second (28) insulating layers; (p) forming a dielectric layer on bare surfaces of the first, second and third conductive layers; and (q) forming a fourth conductive layer on the surface of the dielectric layer to form an opposite electrode of the charge storage capacitor.   6. Method according to claim 1, 3 or 5, characterized in that the trunk-shaped conductive layer (26a, 26b) has a T-shaped cross section.   7. Method according to claim 1, 3 or 5, characterized in that the conductive layer in the form of a trunk (52a, 52b) has a U-shaped cross section.   8. Method according to claim 1, 3 or 5, characterized in that the first branch-shaped conductive layer (40a, 40b) has a hollow cylindrical shape with a cross section in L.   9. Method according to claim 8, characterized in that the first branch-shaped conductive layer (40a, 40b) comprises a first segment and a second segment, the first segment extends vertically upwards from the upper surface of the trunk-shaped conductive layer (26a, 26b), and the second segment extends from one end of the first segment.   10. The method of claim 8, characterized in that the second segment of the first branch-shaped conductive layer (40a, 40b) extends horizontally from the end of the first segment, outward.   11. Method according to claim 8, characterized in that the second segment of the first branch-shaped conductive layer (66a, 66b) extends horizontally from the end of the first segment, inwards.   12. The method of claim 8, characterized in that the first segment is connected to the trunk-shaped conductive layer (52a, 52b) at a peripheral edge of the trunk-shaped conductive layer, and the second segment of the first the branch-shaped conductive layer extends horizontally from the end of the first segment, to an opposite peripheral edge of the trunk-shaped conductive layer.   13. The method of claim 1, 3 or 6, characterized in that the second branch-shaped conductive layer (86a, 86b) has a T cross section.   14. The method of claim 5, characterized in that the second branch-shaped conductive layer (88a, 88b) has a pillar shape, and it rises vertically from the upper surface of the conductive layer trunk (26a, 26b). 15. The method of claim 7, characterized in that step (b) comprises forming a part of the first conductive layer (52), having a U-shaped cross section.   16. The method of claim 1, 3 or 5, characterized in that it further comprises a step of forming a layer of protection against attack (22) on the first insulating layer (20), after step (a) and before step (b).   17. The method of claim 1, 3 or 5, characterized in that step (i) further comprises carrying out a chemo-mechanical polishing to remove by polishing part of the second conductive layer (40) being above the stacked layer structure (30a, 32a; 30b, 32b).   18. The method of claim 1, 3 or 5, characterized in that step (i) further comprises the removal by attack of a portion of the second conductive layer (40) above the structure of stacked layers (30a, 32a; 30b, 32b).   19. The method of claim 1 or 5, characterized in that step (d) comprises the following steps: successively forming a first layer (30a, 30b) and a second layer (32a, 32b) on the second layer insulating material (28), the second layer consisting of a conductive material and the first layer consisting of an insulating material; and defining the first and second layers to form a structure of stacked layers (30a, 32a; 30b, 32b).   20. The method of claim 5, further comprising forming an attack protective layer (92) over the first insulating layer (90), and forming a sixth insulating layer (94) on the attack protection layer, after step (a) and before step (b); characterized in that step (b) further comprises the step of forming a first conductive layer (98) which penetrates through the sixth insulating layer (94) and the attack protection layer ( 92); and step (o) further comprises the step of removing the sixth insulating layer (94).   21. The method as claimed in claim 1, 3 or 5, in which steps (c) to (j) define a method for manufacturing a predefined branch-shaped conductive layer (40) of the charge storage capacitor, characterized in that it further comprises the manufacture of at least one additional predefined branch-shaped conductive layer (80), after step (j), step (n) further comprising the definition of each additional predefined branch-shaped conductive layer (80), such that a respective first end of each predefined branch-shaped conductive layer is connected to the upper surface of the first conductive layer, to form a layer additional branched conductive (80), step (o) further comprising removing remaining portions of any insulating layer, and step (p) further comprising forming a dielectric layer on surfaces bare of c each conductive layer in the form of an additional branch (80).