FR2752490A1 - SEMICONDUCTOR MEMORY DEVICE AND CAPACITOR STRUCTURE FOR SUCH DEVICE - Google Patents

Abstract

A semiconductor memory device includes a storage capacitor connected to a source / drain region (16a) of a transfer transistor on a substrate (10). The capacitor includes a trunk-shaped conductive layer (26a, 38a) and a branch-shaped conductive layer (32a) together constituting a storage electrode having a tree shape; a dielectric layer (40a); and an upper conductive layer (42) constituting an opposite electrode of the capacitor. This capacitor provides increased capacity for the same occupied surface on the substrate.

Description

SEMICONDUCTOR MEMORY DEVICE

  AND CAPACITOR STRUCTURE FOR THIS DEVICE

  This invention relates generally to semiconductor memory devices, and more particularly relates to a charge storage capacitor structure of a dynamic random access memory (or DRAM) cell which also includes a transistor.

transfer.

  Figure 1 is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a DRAM cell is essentially constituted by a transfer transistor T and a charge storage capacitor C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain of this transistor is connected to a storage electrode 6 of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposite electrode 8 of the capacitor C is connected to a source of

  constant tension. A dielectric film 7 is formed between the elect

  storage trode 6 and the opposite electrode 8.

  In the manufacturing process of a DRAM device, we use

  essentially reads a two-dimensional capacitor, called a capacitor

  plan type, for a conventional DRAM device with a storage capacity of less than 1 Mbit (M = mega = million). In the case of a DRAM device having a memory cell which uses a capacitor

  planar type, electrical charges are stored on the main surface

  blade of a semiconductor substrate, which means that the main surface must have a high area. This type of memory cell is not suitable

  therefore not for a DRAM device with a high level of integration.

  For a DRAM device with a high level of integration, such as a

  DRAM device with more than 4 Mbit of memory, we have introduced a

  three-dimensional densifier, called a stacked type capacitor or

trench type.

  With stacked or trench type capacitors, it was possible to obtain a larger memory in a similar volume. However, to make a semiconductor device having a

  even higher level of integration, such as a very high level circuit

  integration calf (or VLSI) with a capacity of 64 Mbit, a conden-

  sator having such a simple three-dimensional structure, as the con-

  stacked type or conventional trench type, appears to be

sufficient.

  A solution to improve the capacity of a capacitor

  is to use what is called the stacked capacitor of the type ai-

  lettes, which is proposed by Ema et al. in "3-Dimensional Stacked Ca-

  pacitor Cell for 16M and 64M DRAMs ", International Electron Devices Meeting, pages 592-595, December 1988. The stacked fin type capacitor includes electrodes and dielectric films which extend in fin form in a set of layers DRAM devices having the finned type stacked capacitor are also described in US Pat. Nos. 5,071,783 (Taguchi et al.); 5,126,810 (Gotou); 5,196,365 (Gotou); and 5,206,787 (Fujioka) Another solution to improve the capacitance of a capacitor

  is to use what is called the stacked capacitor of cy- type

  lindrique, which is proposed by Wakamiya et al. in "Novel Stacked Ca-

  pacitor Cell for 64-Mb DRAM ", 1989, Symposium on VLSI Technology, Digest of Technical Papers, pages 69-70. The stacked cylindrical type capacitor includes electrodes and dielectric films which extend in a cylindrical shape so that increase the surface areas of the electrodes. A DRAM device having the capacitor

  stacked cylindrical type is also described in the U.S. patent.

No. 5,077,688 (Kumanoya et al.).

  With the trend towards increased integration density, it is born

  stop further reducing the size of the DRAM cell in a plane (that is, the area it occupies in a plane). Generally speaking, a reduction in cell size leads to a reduction

  load storage capacity (electrical capacity). In addition, when

  that the electrical capacity is reduced, the probability of occurrence of errors

  transient resulting from the incidence of a rays is increased. He of-

  So there is a need in this area for the design of a new structure for a storage capacitor that can provide the same electrical capacity, while occupying a smaller area in a

  plan, and on a suitable process for manufacturing the structure.

  An object of the invention is therefore to provide a metering device.

  semiconductor memory having a structure which includes a conden-

  tree type sater allowing to obtain an increased area for the

charge storage.

  In accordance with previous goals, as well as others, the

  vention provides a new semiconductor memory device and

perfected.

  A semiconductor memory device in accordance with the

  vention comprises a substrate and a transfer transistor on the substrate, the transfer transistor having source / drain regions. The device

  also includes an electrically connected storage capacitor

  ment to one of the source / drain regions of the transfer transistor. The storage capacitor comprises a conductive layer in the form of a trunk having a lower end electrically connected to one of the

  source / drain regions. The conductive layer in the form of a trunk

  also takes a vertical extension which extends in a practical way-

  vertically from the bottom end. The storage capacitor also comprises at least one branch-shaped conductive layer with an L-shaped cross section. One end of the branch-shaped conductive layer is connected to a surface.

  inside of the conductive layer in the shape of a trunk. The layer con-

  conductive in the form of a trunk and the conductive layer in the form of a branch

  together form a storage electrode for the stock capacitor

  age. The storage capacitor further comprises a dielectric layer formed on the exposed surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layer, and an upper conductive layer on the dielectric layer, fulfilling the function of an opposite electrode of the storage capacitor. According to another aspect of the invention, the conductive layer in the form of a trunk

  includes a lower trunk-like part which is electrically connected

  tracing to one of the source / drain regions of the transfer transistor,

  and a part in the form of an upper trunk which extends practically ver-

  tically from an edge of the lower trunk-like part. The lower trunk-shaped portion may have a T or U-shaped cross section, and the upper trunk-shaped portion forms a substantially hollow cylinder which follows the periphery of the lower trunk-shaped portion. According to another aspect of the invention, the semiconductor memory device comprises a substrate and a transfer transistor formed on the substrate, the transfer transistor having source / drain regions. The device further includes a storage capacitor which

  is electrically connected to one of the source / drain regions of the tran-

  transfer sistor. The storage capacitor includes a conductive trunk-like layer having a connected bottom end

  electrically to one of the source / drain regions. The conductive layer

  trice-shaped trice also has an extension which extends

  practically vertically from the lower end. The conden-

  the storage space also includes at least one conductive layer

  branch-shaped trice, comprising at least a first extension segment and a second extension segment, one end of the first extension segment being connected to the inner surface of the layer

  conductive in the shape of a trunk, and the second extension segment extends

  dant at an angle determined from another end of the first

  extension segment. The conductive layer in the form of a trunk and the

  conductive branch-shaped che form the storage electrode of the

  storage capacitor which further comprises a dielectric layer

  formed on bare surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layer, and an upper conductive layer which is formed on the dielectric layer and which

  performs the function of an opposite electrode of the stock capacitor

age.

  According to another aspect of the invention, the semiconductor memory device comprises a substrate and a transfer transistor formed on the substrate, the transfer transistor having source / drain regions. The device also includes a storage capacitor electrically connected to one of the source / drain regions of the

  transfer transistor. The storage capacitor includes a

  conductive trunk-shaped che having a lower end

  electrically connected to one of the source / drain regions. The conductive layer in the form of a trunk further comprises an extension in

  pillar shape that extends almost vertically from the end

  lower half. The storage capacitor also includes at least one branch-shaped conductive layer having one end connected to the inner surface of the trunk-shaped conductive layer and having an outwardly directed extension which extends from

  from the other end. The conductive layer in the form of a trunk and the

  conductive branch-shaped form a storage electrode

  storage capacitor which further comprises a dielect layer

  stick formed on the exposed surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layer, and an upper conductive layer formed on the dielectric layer, which fills the

  function of an opposite electrode of the storage capacitor.

  According to another aspect of the invention, the semiconductor memory device comprises a substrate and a transfer transistor formed on the substrate. The transfer transistor includes source / drain regions. The device also includes a storage capacitor electrically connected to one of the source / drain regions of the

  transfer transistor. The storage capacitor includes a

  conductive trunk-shaped che having a lower end

  electrically connected to one of the source / drain regions. Layer

  conductive in the form of a trunk also has a vertical extension

  cal which extends practically vertically from the lower end

  better. The storage capacitor also comprises at least one conductive branch-shaped layer which is produced in the form of a practically hollow cylinder. One end of the branch-shaped conductive layer is connected to the upper surface of the trunk-shaped conductive layer. The trunk-shaped conductive layer and the branch-shaped conductive layer form an electrode for

  storage of the storage capacitor which further comprises a

  a dielectric layer formed on the exposed surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layer, and an upper conductive layer formed on the dielectric layer, which

  performs the function of an opposite electrode of the stock capacitor

  age. According to another aspect of the invention, the semiconductor memory device comprises a substrate and a transfer transistor formed on the substrate, the transfer transistor having source / drain regions. The device also includes a storage capacitor which is electrically connected to one of the source / drain regions of the transfer transistor. The storage capacitor includes a conductive trunk-like layer having one end

  lower electrically connected to one of the source / drain regions.

  The trunk-shaped conductive layer further comprises an extension

  vertical position which extends practically vertically from the lower end. The storage capacitor also includes

  a first conductive branch-shaped layer having an

  mite connected to the upper surface of the trunk-shaped conductive layer, and having a vertical extension which extends so

  practically vertical from the end. The stock capacitor

  age further comprises at least one second branch-shaped conductive layer having one end connected to the inner surface of the trunk-shaped conductive layer, and having an outwardly directed extension which extends substantially outwardly from

  the end. The trunk-shaped conductive layer and the con-

  branching conductive form a storage electrode for the con-

  storage densifier which also includes a dielectric layer formed on the exposed surface of the trunk-shaped conductive layer and

  of the branch-shaped conductive layer, and a conductive layer

  upper trice formed on the dielectric layer, which performs the function

  an opposite electrode of the storage capacitor.

  Other characteristics and advantages of the invention will be

  better understood on reading the following description of modes of

  embodiment, given by way of nonlimiting examples. The rest of the

  Description refers to the accompanying drawings, in which: Figure 1 is a circuit diagram of a memory cell of a DRAM device; Figures 2A to 2H are sections representing the structure

  of a first embodiment of a semicon- memory cell

  ductors having a shaft type capacitor according to the invention; Figures 3A to 3E are sections showing the structure

  of a second embodiment of a semicon- memory cell

  ductors having a shaft type capacitor according to the invention; Figures 4A to 4D are sections showing the structure

  of a third embodiment of a semicon- memory cell

  ductors having a shaft type capacitor according to the invention; FIGS. 5A to 5C are sections representing the structure

  of a fourth embodiment of a semicon- memory cell

  ductors having a shaft type capacitor according to the invention; Figures 6A to 6D are sections showing the structure

  of a fifth embodiment of a semicon- memory cell

  ductors having a shaft type capacitor according to the invention; Figures 7A to 7D are sections showing the structure

  of a sixth embodiment of a semicon- memory cell

  ductors having a shaft type capacitor according to the invention; Figures 8A to 8E are sections showing the structure

  of a seventh embodiment of a semicon memory cell

  ductors having a shaft type capacitor according to the invention; Figures 9A to 9E are sections showing the structure

  of an eighth embodiment of a semicon memory cell

  ductors having a shaft type capacitor according to the invention; and

  FIGS. 10A to 10D are sections representing the structure

  ture of a ninth embodiment of a semi-memory cell

  conductors having a tree type capacitor according to the invention

  tion. First Preferred Embodiment With reference to FIGS. 2A to 2H, we will describe in detail the

  first preferred embodiment of the invention, relating to a device

  semiconductor memory device, with a tree-type storage capacitor. Referring to FIG. 2A, it is noted that one begins by carrying out a thermal oxidation of the surface of a silicon substrate

  , using for example a local oxidation technique of sili-

  cium (or LOCOS). A field oxide layer 12 having a thickness of approximately 300 nm is thus formed on the surface of the silicon substrate 10. Then, a thermal oxidation treatment is carried out again,

  to form a gate oxide layer 14 having a thickness of about

  ron 15 nm, on the surface of the silicon substrate 10. Then, using a chemical vapor deposition (CVD) technique, or low pressure chemical vapor deposition (or LPCVD), it is deposited on the whole from the surface of the silicon substrate 10 a layer of polycrystalline silicon having a thickness of about 200 nm. To improve the conductivity of the polycrystalline silicon layer, it is possible to implant

  phosphorus ions in the polycrystalline silicon layer. It is preferred-

  maple to deposit a layer of refractory metal and perform a process

  annealing to form a polycrystalline silicon / silicide layer. The conductivity is therefore further enhanced. The refractory metal may for example be tungsten, deposited up to a thickness of

  nm. Then, we implement a classic photoli-

  thography and attack to define a pattern in the polycrystalline silicon / silicide layer. Grids WL1 to WL4 (or word lines WL1 to WL4) are thus formed, as shown in FIG. 2A. Then,

  arsenic ions are implanted in the substrate 10 to form

  drain regions 16a, 16b, and source regions 18a, 18b. During this implantation step, the word lines WL1 to WL4 are used as mask layers, and the ions are implanted with a dose of approximately

  1015 atoms / cm2, at an energy level of around 70 keV.

  Referring next to FIG. 2B, we note that we deposit

  by CVD an insulating leveling layer 20, such as bo-

  rophosphosilicate (or BPSG), with a thickness of about 700 nm. In-

  further, CVD also forms a protective layer against

  plate 22, such as a layer of silicon nitride having a thickness of approximately 100 nm. Then, using conventional photolithography and etching techniques, the attack protection layer 22, the insulating leveling layer 20 and the gate oxide layer 14 are successively attacked. contact 24a,

  24b for storage electrodes on the upper surface of the cover

  che against attack 22, these holes extending to the surface of the drain regions 16a, 16b. A layer of polycrystalline silicon 26 is then deposited. Arsenic ions are preferably implanted

  in the polycrystalline silicon layer 26, to increase the conductivity

  quickly. As shown in Figure 2B, the layer of polycrystalline silicon

  tallin 26 completely fills the contact holes 24a, 24b and it

  also covers the surface of the attack protection layer

22.

  Referring to FIG. 2C, it is noted that there is then deposited on the polycrystalline silicon layer 26 a thick insulating layer, such as a layer of silicon dioxide having a thickness of approximately 700 nm. Conventional photolithography and etching techniques are used to define a pattern in the insulating layer, so as to form

  insulating pillars 28a, 28b, as shown in Figure 2C. The pi-

  insulating wires 28a, 28b are preferably located above the respective drain regions 16a and 16b, on the layer of polycrystalline silicon

  26. Spaces 29 are thus formed between the insulating pillars 28a, 28b.

  Referring to Figure 2D, we note that we successively form

  by CVD an insulating layer 30, a layer of poly-

  crystalline 32 and an insulating layer 34. The insulating layers 30 and 34 may consist, for example, of silicon dioxide. The thickness of

  each layer among the insulating layer 30 and the poly-silicon layer

  lens 32 can be for example around 100 nm. The thickness of the insulating layer 34 is preferably such that this layer is capable

  at least completely fill the spaces 29 between the iso-

  lants 28a and 28b. In accordance with the first preferred embodiment,

  The thickness of the insulating layer 34 is approximately 700 nm. To increase

  lie about the conductivity of the polycrystalline silicon layer 32, we can

  implant arsenic ions therein.

  Referring to FIG. 2E, we note that we polish the surface of the structure which is represented in FIG. 2D, by a technique of

  chemo-mechanical polishing (or CMP), at least until the

  puts insulating pillars 28a, 28b to be exposed.

  Referring to FIG. 2F, it is noted that by using techniques

  ques conventional photolithography and etching, we attack the insulating layer 34, the polycrystalline silicon layer 32, the insulating layer 30 and the polycrystalline silicon layer 26, to form an opening 36; The storage capacitor storage electrode for each cell

  of memory is now defined by the placement of the layers

  conductive. In addition, by the attack step mentioned above, the

  poles of polycrystalline silicon 32 and 26 are divided into respective segments

  tifs 32a, 32b and 26a, 26b. Next, polycrystalline silicon spacers 38a, 38b are formed on the side walls of the openings.

  36. According to the first preferred embodiment, one can form

  sea the polycrystalline silicon spacers 38a, 38b in form-

  mant a polycrystalline silicon layer with a thickness of about nm, and reducing by attack the thickness of the polycrystalline silicon layer to form the spacers 38a, 38b. Arsenic ions can be implanted in the polycrystalline silicon layer to

  increase the conductivity of poly- silicon spacers

lens 38a, 38b.

  Referring to FIG. 2G, we note that we perform an at-

  wet tacking using the attack protection layer

  as 22 as the end point of the attack, to remove the layers of

  bare silicon dioxide, which are the insulating layers 34, 30 and the

  insulating ties 28a, 28b. After the wet attack stage, the elect

  DRAM device storage capacitor storage trip is complete. The storage electrode which is shown in Figure 2G

  includes the layers of polycrystalline silicon in the form of a lower trunk

  26a, 26b, the upper trunk-shaped polycrystalline silicon layers 38a, 38b and the branch-shaped polycrystalline silicon layers 32a, 32b, which have a practically L-shaped cross section. The trunk-shaped polycrystalline silicon layers 26a, 1 1 26b are in direct contact with the respective drain regions

  16a, 16b of the transfer transistor. The cross sections of the cou-

  lower polycrystalline silicon pins 26a, 26b have a T-shape. The upper trunk-shaped polycrystalline silicon layers 38a, 38b are connected to the edges of the respective lower trunk-shaped polycrystalline silicon layers 26a, 26b, and they are erected. practically vertically, i.e. normal to the surface of the

  layer of protection against attack 22. The layers of poly-

  upper trunk-shaped lens 38a, 38b form cylinders

  hollow, and their cross sections can be circular or rectan-

  gular. The branch-shaped polycrystalline silicon layers 32a, 32b are connected to the interior surfaces of the respective upper polycrystalline silicon layers 38a, 38b, and they first extend horizontally inward, i.e. to the regions of

  drain, over a determined distance, and they then extend vertically-

  ment, up. The term "tree type storage electrode" here designates the completed storage electrode according to the invention, because its structure is unusual. The capacitor comprising "the tree type storage electrode" is therefore called the

  "tree type storage capacitor".

  Referring to FIG. 2H, it is noted that films are formed.

  dielectric cells 40a, 40b on the surface of the storage electrodes

  respective (26a, 32a, 38a) and (26b, 32b, 38b). Each dielect film

  plate 40a, 40b can be for example a layer of silicon dioxide, a layer of silicon nitride, a structure NO (silicon nitride / silicon dioxide), or an ONO structure (silicon dioxide / nitride of

  silicon / silicon dioxide). Then we form on the surface of the films

  dielectric cells 40a, 40b of the opposite electrodes 42 consisting of polycrystalline silicon. The opposite electrodes are produced by forming by CVD a layer of polycrystalline silicon having a thickness which is for example 100 nm, by doping the layer of polycrystalline silicon, for example with an N-type dopant to increase the conductivity, and by defining a pattern in the polycrystalline silicon layer, by

  the use of conventional photolithography and attack techniques.

  The DRAM cell storage capacitor is thus finished.

  Although this is not shown in Figure 2H, it appears

  It will be clear to those skilled in the art that word lines, connection pads, interconnects, passivations and housings can be made, according to conventional processes, to complete the integrated circuit of DRAM. Since these conventional processes are not related to features of the invention, there is no need to

describe them in detail.

  In the first embodiment, the silicon layer p-

  lowest lycrystalline, 26, is divided into layers of polycrystalline silicon

  tallin trunk-shaped 26a, 26b for each memory cell, as shown in Figure 2F. However, according to another mode

  preferred embodiment of the invention, one can define a pattern in the

  polycrystalline silicon che 26 to form layers of silicon po-

  lycrystalline in the form of lower trunks 26a, 26b for each cell of

  memory, just after the polycrystalline silicon layer 26 has been de-

  laid, as shown in Figure 2B. Subsequent processes are then accomplished in a manner similar to that described above.

  Second preferred embodiment In the first embodiment, each storage electrode comprises a single electrode layer in the form of a branch which has practically a cross section in L. The scope of the invention

  is however not limited to this particular embodiment. The name-

  bre of branch-shaped electrodes having a cross-section practically in

  L can be two, three or more. We describe for the second mode of reaction

  Preferred reading is a storage electrode with two electrode layers in the form of a branch, having practically an L-shaped section.

  We will describe in detail with reference to Figures 3A to 3E the se-

  cond preferred embodiment of the invention, relating to a semiconductor memory device with a storage capacitor

tree type.

  The tree type storage capacitor of the second embodiment is based on the wafer structure of Figure 2C. The elements of FIGS. 3A to 3E which are identical to those of FIG. 2C

  are designated by the same reference numerals.

  Referring to FIGS. 2C and 3A, it is noted that a CVD operation is carried out to alternately form insulating layers and polycrystalline silicon layers, more precisely an insulating layer 44, a polycrystalline silicon layer 46, an insulating layer 48, a polycrystalline silicon layer 50 and an insulating layer 52, in succession, as shown in FIG. 3A. The insulating layers 44, 48 and 52 may for example be made of silicon dioxide. The thickness of the insulating layers 44, 48 and of the polycrystalline silicon layers 46, may for example be 100 nm. The thickness of the insulating layer

  52 can be for example 700 nm, and this layer fills with

  the spaces 29 between the insulating pillars 28a, 28b. We can implant

  ter ions, such as arsenic ions, in silicon layers

  polycrystalline, to improve their conductivity.

  Referring to Figure 3B, note that one can use a chemo-mechanical polishing technique to polish the surface of the structure which is shown in Figure 3A, at least until

  the tops of the insulating pillars 28a, 28b are exposed.

  Referring to FIG. 3C, it is noted that techniques are used.

  classic photolithography and attack picnics to attack the

  insulating che 52, the polycrystalline silicon layer 50, the insulating layer 48, the polycrystalline silicon layer 46, the insulating layer 44 and the polycrystalline silicon layer 26, in succession. So, we form a

  opening 54 and the pattern of the condensate storage electrode is defined

* storage space for each memory cell. In addition, by the stage

  above mentioned attack, we divide the layers of poly-

  lens 50, 46 and 26 in respective segments 50a, 50b, 46a, 46b and 26a,

  26b. Next, polycrystalline silicon spacers are formed

  tallin 56a, 56b on the side walls of the opening 54. In accordance

  in the second preferred embodiment, the test elements can be formed

  polycrystalline silicon pitch 56a, 56b by forming a polycrystalline silicon layer with a thickness of about 100 nm, and reducing by attack the thickness of the polycrystalline silicon layer to form

  the spacers 56a, 56b. We can implant arse ions

  nic in the polycrystalline silicon layer to increase the conductivity

  vity of the polycrystalline silicon spacers 56a, 56b.

  Referring to FIG. 3D, it is noted that a wet attack operation is carried out using the protective layer against attack 22 as the end point of the attack, to remove the layers of dioxide. of bare silicon, which are the insulating layers 52, 48 and 44, and the insulating pillars 28a, 28b. After the wet etching step, the storage electrode of the device storage capacitor DRAM is finished. The storage electrode which is represented in FIG. 3D comprises the lower trunk-shaped polycrystalline silicon layers 26a, 26b, the shaped polycrystalline silicon layers

  upper trunk 56a, 56b, and the two layers of polycrystalline silicon

  branch-shaped tallow 46a, 50a, 46b, 50b, which have practically a cross section in L. The lower trunk-shaped polycrystalline silicon layers 26a, 26b come directly into contact with the respective drain regions 16a, 16b of the transistors transfer. The cross sections of the lower polycrystalline silicon layers 26a, 26b have a T shape. The polycrystalline silicon layers in

  upper trunk shape 56a, 56b are connected to the edges of the necks

  polycrystalline silicon ches in the form of respective lower trunks, 26a, 26b, and they are erected practically vertically. The upper trunk-shaped polycrystalline silicon layers 56a, 56b

  are produced in the form of hollow cylinders whose cross sections

  versales can be circular or rectangular. The two layers of

  branch-shaped polycrystalline silicon 46a, 50a, 46b, 50b are con-

  nected to the interior surfaces of the polycrystalline silicon layers

  respective upper, 56a, 56b, and they extend first hori-

  horizontally inward for a specified distance, after which they

  extend vertically upwards.

  Referring to FIG. 3E, it is noted that films are formed.

  dielectric cells 58a, 58b on the surface of the respective storage electrodes (26a, 46a, 50a, 56a) and (26b, 46b, 50b, 56b). Then we

  forms opposite electrodes 60, made of polycrystalline silicon, on the surface

  face of the dielectric films 58a, 58b. We manufacture the electrodes op-

  laid by forming a polycrystalline silicon layer having for example-

  ple a thickness of 100 nm, by CVD, by doping the polycrystalline silicon layer with for example an N-type dopant, to increase the

  conductivity, and by defining a pattern in the poly- silicon layer

  crystalline, by the use of classical photolithography and attack techniques. The DRAM cell storage capacitor is

then finished.

  Third embodiment In the first second preferred embodiments, the branch-shaped electrode layers of the storage electrode have L-shaped cross sections. The invention is not, however, limited to

  this. A description will be given, for the following preferred embodiment, of a

  branch electrode electrode having a cross section in

pillar shape.

  Referring to FIGS. 4A to 4D, the third will be described in detail.

  5th preferred embodiment of the invention, relating to a semiconductor memory device with a storage capacitor

tree type.

  The tree type storage capacitor of the third embodiment is based on the wafer structure of FIG. 2C,

  and it includes additional elements. The elements on the fig-

  res 4A to 4D which are identical to those of FIG. 2C are designated

  has the same reference numbers.

  Referring to Figures 2C and 4A, it is noted that polycrystalline silicon spacers 62a, 62b are formed on the side walls of the insulating pillars 28a, 28b. According to the third preferred embodiment, the polycrystalline silicon spacers 62a, 62b are manufactured by depositing a layer of polycrystalline silicon with a thickness of approximately 100 nm, and reducing by attack

  the thickness of the polycrystalline silicon layer, to form the elements

  spacers 62a, 62b. To improve the conductivity of the cou-

  In polycrystalline silicon, ions such as arsenic can be implanted therein. A CVD operation is then carried out to deposit a thick insulating layer 64. It is preferable that the space between the

  insulating pillars 28a, 28b is thus filled.

  Referring to FIG. 4B, it is noted that a technique is used.

  chemo-mechanical polishing nick to polish the surface of the structure shown in Figure 4A, preferably until the tops of the insulating pillars 28a, 28b and the silicon spacers

  polycrystalline 62a, 62b are exposed.

  Referring to FIG. 4C, it is noted that techniques are used.

  classic photolithography and attack nics to attack successfully

  the thick insulating layer 64 and the poly- silicon layer

  lens 26; thus, an opening 66 is formed and a pattern is defined for the storage electrode of the storage capacitor for each cell

  of memory. In addition, by the attack step mentioned above, we di-

  targets the polycrystalline silicon layer 26 into respective segments 26a,

  26b. Next, polycrystalline silicon spacers are formed

  tallin 68a, 68b on the side walls of the opening 66; Referring to FIG. 4D, it is noted that a wet attack operation is carried out using the attack protective layer 22 as the end point of the attack, to remove the layers of dioxide. of bare silicon, which are the insulating layer 64 and the

  insulating pillars 28a, 28b. After the wet attack stage, the elect

  DRAM device storage capacitor storage trip is complete. The storage electrode which is shown in Figure 4D

  includes the layers of polycrystalline silicon in the form of a lower trunk

  26a, 26b, the upper trunk-shaped polycrystalline silicon layers 68a, 68b and the branch-shaped polycrystalline silicon 62a, 62b, which have a substantially pillar-shaped cross section. The lower trunk-shaped polycrystalline silicon layers 26a, 26b are directly in contact with the respective drain regions 16a, 16b of the transfer transistors. The cross sections of the lower polycrystalline silicon layers 26a, 26b have a T-shape. The upper trunk-shaped polycrystalline silicon layers 68a, 68b are connected to the edges of the respective lower trunk-shaped polycrystalline silicon layers 26a, 26b,

  and they rise almost vertically. The layers of sili-

  polycrystalline cium in the form of upper trunks 68a, 68b are produced in the form of hollow cylinders, the cross sections of which can be circular or rectangular. The branch-shaped polycrystalline silicon layers 62a, 62b are connected to the upper surface of the lower trunk-shaped polycrystalline silicon layers 26a,

  26b, and they extend in a vertical direction. In accordance with the three-

  Fifth preferred embodiment, the polycrystalline silicon layers 62a, 62b are produced in the form of practically hollow cylinders whose cross sections depend essentially on the cross section of the insulating pillars 28a, 28b, which can be circular or rectangular. The branch-shaped polycrystalline silicon layers 62a, 62b are placed between the polycrystalline silicon layers in

  upper trunk shape 68a, 68b.

  Fourth preferred embodiment The fourth embodiment is described below.

  preferred storage capacitor, which includes electrical layers

  branch-shaped trodes that have an L-shaped cross section, and

  branch-shaped electrode layers which have a cross-section

  dirty pillar shaped. The fourth preferred embodiment is formed.

  d by combining aspects of the first and third embodiments

  preferred. We therefore create a structure that combines the characteristics

  than the first and third preferred embodiments.

  Referring to FIGS. 5A to 5C, we will describe in detail the

  fourth preferred embodiment of the invention, relating to a device

  semiconductor memory positive with a storage capacitor

tree type.

  The storage capacitor of the fourth embodiment is based on the wafer structure of Figure 2C. The elements in FIGS. 5A to 5E which are identical to those in FIG. 2C are designated

  by the same reference numbers.

  Referring to FIGS. 2C and 5A, it is noted that polycrystalline silicon spacers 70a, 70b are formed on the walls

  lateral of the respective insulating pillars 28a, 28b. We make the elements

  polycrystalline silicon spacers by depositing a layer of

  polycrystalline silicon with a thickness of about 100 nm, and reducing

  by attacking the thickness of the polycrystalline silicon layer to form spacers. Then deposited successively, by CVD, an insulating layer 72 and a layer of polycrystalline silicon

  74. After this, a thick insulating layer is deposited.

  Referring to FIG. 5B, we note that we realize the struc-

  which is represented using the processes described above.

  ment in relation to FIGS. 2E and 2F. In other words, a chemo-mechanical polishing technique is used to polish the surface of the

  structure which is shown in FIG. 5A, until the summits

  put insulating pillars 28a, 28b, the tops of the space elements-

  polycrystalline silicon 70a, 70b and the vertices of the

  polycrystalline silicon 74 are exposed.

  Conventional photolithography and etching techniques are used to attack in succession the insulating layer 76, the polycrystalline silicon layer 74, the insulating layer 72 and the polycrystalline silicon layer 26; thus, an opening 78 is formed and the pattern of the storage electrode of the storage capacitor is defined for each cell.

  of memory. In addition, by the attack step mentioned above, we di-

  targets the polycrystalline silicon layers 74 and 26 in respective segments 74a, 74b and 26a, 26b. Then we form spacers in

  polycrystalline silicon 80a, 80b on the side walls of the opening 78.

  Referring to FIG. 5C, it is noted that one performs an at-

  wet tacking using the attack protection layer

  as 22 as the end point of the attack, to remove the bare silicon dioxide layers, which are the insulating layers 76 and 72 and the

  insulating pillars 28a, 28b. After the wet attack stage, the elect

  DRAM device storage capacitor storage trip is complete. The storage electrode which is shown in Figure 5C

  includes the layers of polycrystalline silicon in the form of a lower trunk

  layers 26a, 26b, the upper trunk-shaped polycrystalline silicon layers 80a, 80b, the branch-shaped polycrystalline silicon layers 70a, 70b which have practically a pillar-shaped cross section, and the polycrystalline silicon-shaped layers branch 74a, 74b, which have practically a cross section in L.

  The layers of polycrystalline silicon in the form of a lower trunk

  lines 26a, 26b are in direct contact with the drain regions

  respective 16a, 16b of the transfer transistors. The cross sections

  dirty lower polycrystalline silicon layers 26a, 26b have a

  T-shape. The layers of polycrystalline silicon in the shape of a trunk

  80a, 80b are connected to the edges of the silicon layers for

  lycristalline in the form of respective lower trunks, 26a, 26b, and they

  rise almost vertically. Poly- silicon layers

  crystalline upper trunk 80a, 80b are produced under the

  shape of hollow cylinders whose cross sections can be circumvented

  circular or rectangular. The branch-shaped polycrystalline silicon layers 74a, 74b, which have practically an L-shaped cross section,

  are connected to the inner surface of the poly- silicon layer

  upper lens 80a, 80b, they extend horizontally towards the inside

  anterior distance over a predetermined distance, and then extend substantially vertically. The polycrystalline silicon layers in

  branch shape 70a, 70b, which have a practical cross-section

  Pillar-shaped, are connected to the upper surfaces of the lower trunk-shaped polycrystalline silicon layers 26a, 26b, and they extend practically vertically. The branch-shaped polycrystalline silicon layers 70a, 70b are produced in the form

of practically hollow cylinders.

  Fifth preferred embodiment Another storage electrode having a structure similar to that described is described for the fifth preferred embodiment.

  described in the fourth embodiment, but made of a material

different way.

  We will describe in detail, with reference to FIGS. 6A to 6D, the cin-

  the fifth preferred embodiment of the invention, relating to a device

  semiconductor memory device with a storage capacitor

tree type.

  The storage capacitor of the fifth embodiment is based on the wafer structure of Figure 2C. The elements of FIGS. 6A to 6D which are identical to those of FIG. 2C are designated

  by the same reference numbers.

  Referring to FIGS. 2C and 6A, it is noted that layers of polycrystalline silicon and insulating layers are deposited alternately by CVD. As shown in FIG. 6A, a layer of polycrystalline silicon 84, an insulating layer 86, a layer of polycrystalline silicon 88 and an insulating layer are deposited in succession.

thick 90.

  Referring to FIG. 6B, it is noted that a technique is used.

  chemo-mechanical polishing tool to polish the surface of the structure

  which is represented in FIG. 6A, until the vertices of the peaks

  insulating ties 28a, 28b are exposed.

  Referring to FIG. 6C, it is noted that techniques are used.

  conventional photolithography and etching nics for successively attacking the insulating layer 90, the polycrystalline silicon layer 88, the insulating layer 86, the polycrystalline silicon layer 84 and the polycrystalline silicon layer 26; thus, an opening 92 is formed and a pattern is defined for the storage electrode of the storage capacitor for

  each memory cell. In addition, by the attack step mentioned above

  above, the polycrystalline silicon layers 88, 84 and 26 are divided into respective segments 88a, 88b, 84a, 84b and 26a, 26b. We then train

  polycrystalline silicon spacers 94a, 94b on the sides

lateral kings of the opening 92.

  Referring to Figure 6D, it is noted that a wet attack operation is carried out, using the attack protective layer 22 as the end point of the attack, to remove the layers of bare silicon dioxide which are the insulating layers 90 and

  86 and the insulating pillars 28a, 28b. After the attack stage by humane

  mide, the storage electrode of the DRAM device storage capacitor is complete. The storage electrode which is represented in FIG. 6D comprises the lower polycrystalline silicon layers 26a, 26b, the upper trunk-shaped polycrystalline silicon layers

  94a, 94b, and the two layers of polycrystalline silicon in the form of bran-

  che 84a, 88a, 84b, 88b, which have a practically L-shaped cross section. The lower trunk-shaped polycrystalline silicon layers

  26a, 26b are in direct contact with the respective drain regions

  ves 16a, 16b of the transfer transistors. The cross sections of the lower polycrystalline silicon layers 26a, 26b have a T-shape. The upper trunk-shaped polycrystalline silicon layers

  94a, 94b are connected to the edges of the polycrystalline silicon layers

  flax in the form of respective lower trunks, 26a, 26b, and they rise practically vertically. The polycrystalline silicon layers in

  form of upper trunk 94a, 94b are produced in the form of cy-

  hollow linders whose cross sections may be circular or rectangular. The two layers of branch-shaped polycrystalline silicon 84a, 88a, 84b, 88b are connected to the interior surfaces of the

  polycrystalline silicon layers in the form of upper trunk respectively

  ves, 94a, 94b, and they first extend horizontally inward

  laughing for a predetermined distance, and then they extend in a

  practically vertical lesson. The structure in accordance with this embodiment

  preferred tion differs from the second preferred embodiment (Figures 3A to

  3E) by the fact that the lower parts of the poly-

  crystal in the form of a branch 84a, 84b are directly in contact with the upper surfaces of the lower trunk-shaped polycrystalline silicon layers 26a, 26b. Therefore, the structure of the electrode

  storage according to the fifth preferred embodiment is if

  related to the structure of the second preferred embodiment.

  Sixth preferred embodiment For the sixth preferred embodiment, there is described a storage electrode having a different structure, which is manufactured

  by a different process. The structure of the storage electrode con-

  form to the sixth preferred embodiment is very similar to the

  structure according to the second preferred embodiment. A differ-

  The difference between the two embodiments consists in that the layer of polycrystalline silicon in the form of a lower trunk of the storage electrode according to the sixth preferred embodiment comprises a

  hollow part. Therefore, the surface area of the storage electrode-

age is increased.

  Referring to Figures 7A to 7D, we will describe in detail the

  sixth preferred embodiment of the invention, relating to an arrangement

  semiconductor memory device having a storage capacitor

tree type.

  The storage capacitor of the sixth preferred embodiment is based on the wafer structure of Figure 2A. The elements in FIGS. 7A to 7D which are identical to those in FIG. 2A are

  designated by the same reference numerals.

  Referring to Figures 2A and 7A, we note that we deposit

  by CVD, for flattening, an insulating layer 96, such as a layer

  borophosphosilicate glass (or BPSG). Then we train by CVD

  a layer of protection against attack 98, such as a layer of ni-

  trure of silicon. Then, using classical pho-

  tolithography and attack, the attack protection layer 98, the insulating layer 96 and the gate oxide layer 14 are successively attacked; contact holes 100a, 100b are thus formed for storage electrodes, which extend from the upper surface

  from the attack protection layer 98 to the surface of the

  drain regions 16a, 16b. Then a layer of poly- silicon is deposited.

  crystalline 102. To increase the conductivity of the silicon layer

  polycrystalline, we implant in the latter ions such as arse-

  nic. As shown in FIG. 7A, the layer of polycrystalline silicon

  linen 102 covers the surface of the attack protection layer 98 and the interior side walls of the contact holes 100a, 100b, but it does not completely fill the contact holes 100a, 100b. As a result, the polycrystalline silicon layer 102 is hollow and has a U-shaped cross section.

  Referring to FIG. 7B, it is noted that a layer is deposited

  thick insulating che, such as a layer of silicon dioxide having a thickness of about 700 nm. The thick insulating layer is then defined using conventional photolithography techniques and

  attack, so as to form insulating pillars 104a, 104b, as

  shown in Figure 7B. The insulating pillars 104a, 104b are preferably located above the respective drain regions 16a and 16b, on the polycrystalline silicon layer 26, and they completely fill the hollow structure of the polycrystalline silicon layer 102. Spaces

  106 are thus formed between the insulating pillars 104a, 104b.

  A process similar to that described in accordance with

  ment to the second preferred embodiment, in relation to FIGS. 3A to 3D, for manufacturing the storage electrode conforming to the sixth

preferred embodiment.

  Referring to FIG. 7C, it is noted that a CVD operation is carried out to alternately form insulating layers and

  polycrystalline silicon layers, more precisely an iso- layer

  lante 106, a layer of polycrystalline silicon 108, an insulating layer 110, a layer of polycrystalline silicon 112 and a thick insulating layer 114, in succession. A chemical mechanical polishing technique can be used to polish the surface of the structure until

  minus the tops of the insulating pillars 104a, 104b are exposed.

  Referring to FIG. 7D, it is noted that techniques are used.

  conventional photolithography and etching nics for successively attacking the insulating layer 114, the polycrystalline silicon layer 112, the insulating layer 110, the polycrystalline silicon layer 108, the insulating layer 106 and the polycrystalline silicon layer 102; thus, an opening 118 is formed and the pattern of the storage electrode of the storage capacitor is defined for each memory cell. Moreover,

  by the attack step mentioned above, the layers of poly-

  lens 112, 108 and 102 are respectively divided into segments 112a, 112b, 108a, 108b and 102a, 102b. Next, polycrystalline silicon spacers 116a, 116b are formed on the side walls of the opening 118. A wet attack operation is then carried out using the attack protection layer 98 as a end point of the attack, to remove the layers of bare silicon dioxide, which are the insulating layers 114, 110 and 106, and the insulating pillars 104a, 104b. After the wet etching step, the storage electrode of the DRAM device storage capacitor is finished.

  The storage electrode which is shown in Figure 7D is very similar to the structure shown in Figure 3D. The difference between

  the two structures is that the layers of polycrystalline silicon

  tallin in the form of a lower trunk 102a, 102b of the sixth embodiment

  preferred sation are hollow. Therefore, the surface of the electrode

storage is increased.

  Seventh preferred embodiment For the seventh preferred embodiment, a storage electrode having a different structure which is manufactured is described.

  by a different process. The structure of the storage electrode con-

  The shape of the seventh preferred embodiment is very similar to the structure according to the second preferred embodiment. The difference

  between the two embodiments is that the silicon layer

  polycrystalline cium-shaped lower trunk of the storage electrode

  according to the seventh preferred embodiment does not come into conflict

  tact with the upper surface of the attack protection layer

  than lower, but is separated from it by a determined distance. The

  the surface of the storage electrode is therefore increased.

  Referring to Figures 8A to 8E, the seventh preferred embodiment of the invention will be described in detail, relating to a semiconductor memory device with a storage capacitor.

tree type.

  The storage capacitor of the seventh preferred embodiment is based on the wafer structure of Figure 2A. Different processing steps are then performed to make a different structure. The elements in FIGS. 8A to 8E which are identical to

  those of FIG. 2A are designated by the same numerical references.

  ques. Referring to FIGS. 8A and 2A, we note that we deposit

  by CVD an insulating layer 120, such as a layer of boro- glass

  phosphosilicate (or BPSG) for leveling. A protection layer against attack 122. is then formed by CVD.

  by CVD an insulating layer 124, such as silicon dioxide. In-

  Next, using conventional photolithography and etching techniques, the insulating layer 124, the attack protective layer 122, the insulating layer 120 and the gate oxide layer 14 are attacked in succession. contact holes 126a, 126b for the storage electrode, which extend from the upper surface of the insulating layer 124 to the surface of the drain regions 16a, 16b. A layer of polycrystalline silicon 128 is then deposited. As

  shown in FIG. 8A, the layer of polycrystalline silicon 128 rem-

  completely folds the contact holes 126a, 126b and covers the

surface of the insulating layer 124.

  Referring to FIG. 8B, it is noted that a layer is deposited

  thick insulating che, such as a layer of silicon dioxide, having a thickness of about 700 nm. Next, the thick insulating layer is defined by a conventional photolithography and etching technique, so as to form insulating pillars 130a, 130b, as shown in FIG. 8B. The insulating pillars 130a, 130b are preferably located above the respective drain regions 16a and 16b, on the polycrystalline silicon layer 128. Spaces 129 are thus formed between the

insulating pillars.

  Next, a process similar to that described in accordance with the second preferred embodiment, in connection with FIGS. 3A to 3D, is carried out to produce the storage electrode in accordance with

  mement to the seventh preferred embodiment.

  Referring to FIG. 8C, it is noted that a CVD operation is carried out to alternately form insulating layers and layers of polycrystalline silicon, more precisely a layer

  insulator 132, a layer of polycrystalline silicon 134, an iso- layer

  lante 136, a layer of polycrystalline silicon 138 and an iso-

  140 thick mantis, in succession. We can use a po-

  chemo-mechanical smoothing to polish the surface of the structure until

  that at least the tops of the insulating pillars 130a, 130b are exposed.

  Referring to Figure 8D, we note that we use

  conventional photolithography and etching nics for successively attacking the insulating layer 140, the polycrystalline silicon layer 138, the insulating layer 136, the polycrystalline silicon layer 134, the insulating layer 132, and the polycrystalline silicon layer 128; thus, an opening 142 is formed and the pattern of the storage electrode of the storage capacitor is defined for each memory cell. Moreover,

  by the attack step mentioned above, the layers of poly-

  lens 138, 134 and 128 are divided into respective segments 138a,

  138b, 134a, 134b and 128a, 128b. Then we form elements of space

* polycrystalline silicon cement 144a, 144b on the side walls of

opening 142.

  Referring to Figure 8E, it is noted that a wet attack operation is carried out using the attack protective layer 122 as the end point of the attack, to remove the dioxide layers. of bare silicon, which are the insulating layers 140,

  136, 132 and 124, and the insulating pillars 130a, 130b. After the atta-

  only when wet, the storage capacitor of the storage capacitor

  DRAM device age is complete. The storage electrode which is re-

  shown in Figure 8E is very similar to the structure shown in Figure 3D. The difference between the two structures is that

  than the lower horizontal surface of the polycrystalline silicon layers

  lower trunk-shaped flax 128a, 128b does not come into contact with the upper surface of the attack protection layer 122 which is below. The surface of the storage electrode is therefore increased. Eighth preferred embodiment In the first to seventh preferred embodiments, the branched electrode layers of the storage electrodes are either vertical structures with single segments, or folded structures with two segments that have a cross section practically in L. The scope of the invention is however not limited to these structures. The number of segments assigned to the different parts of the branch-shaped electrode layer can be three, four

  or more. A branch-shaped electrode layer with four segments

  ment is described in detail for the eighth preferred embodiment.

  Referring to Figures 9A to 9E, we will describe in detail the

  eighth preferred embodiment of the invention, relating to an arrangement

  semiconductor memory device with a storage capacitor

tree type.

  The storage capacitor of the eighth preferred embodiment is based on the wafer structure of Figure 2B. Different processing steps are then performed to make a different structure. The elements of FIGS. 9A to 9E which are identical to those

  of Figure 2A are designated by the same reference numerals.

  Referring to FIGS. 9A and 2B, it is noted that a thick insulating layer, such as a layer of silicon dioxide having a thickness of approximately 700 nm, is deposited on the polycrystalline silicon layer 26. A photosensitive resin layer 52 is then formed, by a conventional photolithography technique, and an anisotropic attack on this layer is also carried out to form parts of the insulating layer. The insulating layers 150a, 150b are thus formed with

  spaces 157 between them, as shown in FIG. 9A.

  Referring to FIG. 9B, it is noted that a technique is used.

  photosensitive resin erosion method for removing portions of the photosensitive resin layer 152, so as to leave smaller and thinner photosensitive resin layers, 152a, 152b. Parts of the upper surfaces of the insulating layer, 150a, 150b, are thus

laid bare.

  Referring to FIG. 9C, we note that we use an atta-

  that anisotropic to remove the exposed parts of the insulating layers 150a, b and the remaining exposed insulating layer, until the layer of

  polycrystalline silicon 26 is exposed. We thus form iso-

  staircase shaped gloves, 150c, 150c. Then remove the layer of

photosensitive resin.

  Next, a process similar to that used to make the first preferred embodiment, which is described in connection with FIGS. 2D to 2G, is implemented to form the storage electrode.

  according to the eighth preferred embodiment.

  Referring to FIG. 9D, it is noted that one deposits successively

  by CVD an insulating layer 154, a layer of poly-

  crystalline 156 and a thick insulating layer 158. A chemo-mechanical polishing technique is then used to polish the surface of the structure until the upper surfaces of the insulating pillars

c, 150d are laid bare.

  Referring to FIG. 9E, it is noted that techniques are used.

  conventional photolithography and etching nics for successively attacking the insulating layer 158, the polycrystalline silicon layer

  156, the insulating layer 154 and the polycrystalline silicon layer 26; so

  if we form an opening 155 and we define the pattern of the electrode

  storage of the storage capacitor for each memory cell.

  The etching step mentioned above also has the effect of dividing the polycrystalline silicon layers 156 and 26 into respective segments 156a, 156b and 26a, 26b. Next, polycrystalline silicon spacers 159a, 159b are formed on the side walls of the opening 155. A wet etching operation is carried out using the

  protective layer against attack 22 as the end point of the attack

  that to remove the bare silicon dioxide layers, which are the insulating layers 158 and 154, and the insulating pillars 150c, 150d. After

  the wet attack step, the condensate storage electrode

  DRAM device storage is complete. As shown in Figure 9E, the storage electrode includes the silicon layers

  polycrystalline in the form of lower trunks 26a, 26b, the layers of sili-

  polycrystalline cium in the form of upper trunks 159a, 159b, and the co-

  branch-shaped polycrystalline silicon plates 156a, 156b, which are folded structures with four segments having a cross section

  dirty practically in the shape of a double L. The layers of poly-

  crystal in the form of a branch 156a, 156b are first connected to the interior surfaces of the upper trunk-shaped polycrystalline silicon layers 159a, 159b, they extend horizontally inward for a determined distance, they extend to again practically vertically over another determined distance, they then extend horizontally inward for another distance

  determined, and then they extend vertically upwards.

  In accordance with this preferred embodiment, the configurations

  the insulating pillars and the insulating layer with defined spaces

  define the configuration and angles of the polycrystalline silicon layer

  branch-shaped linen. Therefore, the configuration of the insulating pillars and insulating layers with spaces, corresponding to

  the invention is not limited to the particular embodiment which is defined

  crit. In fact, techniques are envisaged for modifying the confi-

  guration described to give a different final form, in accordance with the eighth preferred embodiment. For example, if an isotropic attack or a wet attack is used instead of an anisotropic attack to attack the thick insulating layer, shown on the

  Figure 2C, the resulting insulating layer will have a triangular shape. Se-

  a variant, also as shown in FIG. 2C, after the formation of the insulating pillars 28a, 28b, if insulating spacing elements are also formed on the side walls of the insulating pillars 28a,

  28b, one obtains insulating pillars having different configurations.

  The branch-shaped polycrystalline silicon layer can therefore be formed in several different configurations having different angles,

  according to the eighth preferred embodiment.

  According to the design of the preferred embodiment, if one wishes to obtain polycrystalline silicon layers in the form of a branch with more segments, one can perform erosion operations of photosensitive resin and anisotropic attack of the layer once or more. insulating with spaces, to form an insulating pillar having

  a staircase shape with multiple steps.

  Ninth Preferred Embodiment In the first through eighth preferred embodiments,

  always uses a chemo-mechanical polishing technique to remove

  to the polycrystalline silicon layer above the pillars

  insulators. The scope of the invention is not however limited by the use of

  tion of this technique. In the ninth preferred embodiment, a conventional photolithography and etching technique is used to remove the layer of polycrystalline silicon on the insulating pillar. A

  storage electrode with a different structure is therefore formed.

  Referring to Figures 10A to 10D, we will describe in detail the

  ninth preferred embodiment of the invention, relating to a device

  semiconductor memory positive with a storage capacitor

tree type.

  The storage capacitor of the ninth embodiment

  is based on the wafer structure of Figure 2C. We use a process

  extra to make a storage electrode

  tif DRAM with a different structure. The elements of FIGS. 10A to

  D which are identical to those of FIG. 2C are designated by the same-

my digital references.

  Referring to FIGS. 10A and 2C, it is noted that, by CVD, layers of polycrystalline silicon and insulating layers are deposited. As shown in FIG. 10A, an insulating layer 160, a silicon layer, is deposited on the silicon layer 26

  polycrystalline 162, an insulating layer 164, a layer of poly-

  crystalline 166 and a thick insulating layer 168. The insulating layers

  , 164, 168 may for example be layers of silicon dioxide

  cium. The thickness of the insulating layers 160, 164 and of the silicon layers

  polycrystalline cium 162, 166 may for example be 100 nm. Layer

  thick insulation 168 is preferably thick enough to replace

  crease the space on the surface of the polycrystalline silicon layer 166.

  Referring to FIG. 10OB, it is noted that conventional photolithography and etching techniques are used to successively attack the insulating layer 168, the polycrystalline silicon layer 166, the insulating layer 164, the polycrystalline silicon layer 162, the insulating layer 160 and the polycrystalline silicon layer 26; thus, an opening 170 is formed and the pattern of the storage electrode of the storage capacitor is defined for each memory cell. The etching step mentioned above also has the effect of dividing the polycrystalline silicon layers 166, 162 and 26 into respective segments 166a, 166b, 162a, 162b and 26a, 26b. Next, polycrystalline silicon spacers 172a, 172b are formed on the side walls.

from opening 170.

  Referring to FIG. 10C, it is noted that conventional photolithography and etching techniques are used to successively attack the polycrystalline silicon layers 166a, 166b, the insulating layers 164 and the polycrystalline silicon layers 162a, 162b ; openings 174a, 174b are thus formed. Consequently, the polycrystalline silicon layers 166a, 166b and 162a, 162b on the insulating pillars 28a, 28b are partially attacked to expose the layers of

  silicon dioxide between the layers of polycrystalline silicon.

  Referring to FIG. 10D, it is noted that a wet attack operation is carried out using the attack protective layer 22 as the end point of the attack, to remove the layers of dioxide. of bare silicon, which are the insulating layers 168, 164, 160 and the insulating pillars 28a, 28b. After the lane attack stage

  wet, the storage electrode of the available storage capacitor

  DRAM sitive is over. The storage electrode which is shown in Figure 10D includes the lower polycrystalline silicon layers

  26a, 26b, the layers of polycrystalline silicon in the form of an upper trunk

  172a, 172b, and the two layers of branch-shaped polycrystalline silicon 162a, 166a, 162b, 166b, having three segments. The two layers of branch-shaped polycrystalline silicon 162a, 166a,

  162b, 166b are first connected to the inner surface of the layers

  polycrystalline silicon trunk-shaped upper 172a, 172b,

  they extend horizontally inward over a specified distance

  mined, they then extend upward again,

  approximately vertical, over another determined distance, and they then extend horizontally inward over another determined distance.

  It will be clear to those skilled in the art that the characteristics

  that the preferred embodiments contemplated above can also be applied together, in combination, to form

  storage electrodes and storage capacitors having

  for structures. The structures of these storage electrodes and

  storage capacitors are all within the scope of the invention.

  Although in the appended drawings, the embodiments of the drains of the transfer transistors are represented in the form of zones diffused in a silicon substrate, other variants,

  such as for example trench type drain regions, are possible

  and are contemplated in accordance with the invention.

  The elements in the accompanying drawings are shown schematically, for display purposes, and do not correspond to

  a real scale of the structure of the invention. The dimensions of the elements

  ment of the invention which are shown do not limit the scope of the invention. It goes without saying that many other modifications can be made to the device described and shown, without departing from the scope of the invention.

Claims (23)

  1. A semiconductor memory device, comprising: (a)   a substrate (10); (b) a transfer transistor on the substrate, the transistor   transfer tor having a source / drain region (16a, 16b); and (c) a storage capacitor electrically connected to the region of   source / drain, characterized in that the storage capacitor   takes: a trunk-shaped conductive layer (26a, 26b) having a lower end electrically connected to the source / drain region (16a, 16b), the trunk-shaped conductive layer further having a   inner surface and a vertical extension (38a, 38b) extending pra-   vertically vertically from the lower end; a diaper   branch-shaped conductor (32a, 32b), having a cross-section   dirty in L, one end of the branch-shaped conductive layer being connected to the inner surface of the trunk-shaped conductive layer, and the trunk-shaped conductive layer and the branch-shaped conductive layer forming a storage electrode storage capacitor; a dielectric layer (40a, 40b) on the exposed surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layer; and an upper conductive layer (42) on the dielectric layer (40a, 40b) fulfilling the function of a   opposite electrode of the storage capacitor.   2. Semiconductor memory device according to the claim   tion 1, characterized in that the branch-shaped conductive layer comprises two branch-shaped conductive layers (46a, 46b;   50a, 50b) practically parallel, each of the two conductive layers   these branch-shaped having an L-shaped cross section, and in that a respective end of each of the two conductive branch-shaped layers is connected to the inner surface of the layer   conductive in the form of a trunk (26a, 26b; 56a, 56b).   3. Semiconductor memory device according to the claim   tion 1, characterized in that the branch-shaped conductive layer (156a, 156b) has a double L cross section. 4. A semiconductor memory device, comprising: (a)   a substrate (10); (b) a transfer transistor on the substrate, the transistor   transfer tor having a source / drain region (16a, 16b); and (c) a storage capacitor electrically connected to the region of   source / drain, characterized in that the storage capacitor   takes: a conductive trunk-shaped layer (26a, 26b) having a lower end electrically connected to one of the source / drain regions (16a, 16b), the conductive trunk-shaped layer further having an inner surface and a vertical extension (172a, 172b) extending substantially vertically from the lower end; a branch-shaped conductive layer (162a, 162b; 166a, 166b),   comprising at least a first extension segment and a second segment   extension, a first end of the first extension segment   sion being connected to the inner surface of the trunk-shaped conductive layer, and the second extension segment extending under a   certain angle from a second end of the first segment of ex-   voltage; the conductive layer in the form of a trunk and the conductive layer   branch-shaped trice forming an electrode of the storage capacitor; a dielectric layer on bare surfaces of the trunk-shaped conductive layer and the conductive-shaped layer   plugged; and an upper conductive layer on the dielectric layer   that, fulfilling the function of an opposite electrode of the capacitor storage.   5. Semiconductor memory device according to the claim   tion 4, characterized in that the branch-shaped conductive layer   (162a, 162b; 166a, 166b) further includes a third segment of ex-   tension extending at a certain angle from the second segment extension.   6. Semiconductor memory device according to the claim   tion 5, characterized in that the first extension segment and the third   fifth extension segment extend almost horizontally and the   second extension segment extends almost vertically.   7. Semiconductor memory device according to the claim   tion 4, characterized in that the branch-shaped conductive layer comprises two practically parallel branch-shaped conductive layers (162a, 162b; 166a, 166b), and in that one respective end of each of the two shaped conductive layers of branch is connected to the inner surface of the conductive layer in the form of trunk (26a, 26b; 172a, 172b).   8. A semiconductor memory device, comprising: (a)   a substrate (10); (b) a transfer transistor on the substrate, the transistor   transfer tor having a source / drain region (16a, 16b); and (c) a storage capacitor electrically connected to the region of   source / drain, characterized in that the storage capacitor   takes: a trunk-shaped conductive layer (26a, 26b) having a lower end electrically connected to the source / drain region (16a, 16b); the trunk-shaped conductive layer further having an interior surface and a pillar-like extension (68a, 68b) extending substantially vertically from the bottom end;   a branch-shaped conductive layer (62a, 62b), having an ex-   end connected to the inner surface of the trunk-shaped conductive layer and extending outwardly from the end, the trunk-shaped conductive layer and the branch-shaped conductive layer forming a storage electrode storage capacitor; a dielectric layer on bare surfaces of the trunk-shaped conductive layer and the conductive-shaped layer   plugged; and an upper conductive layer on the dielectric layer   that, fulfilling the function of an opposite electrode of the storage capacitor.   9. Semiconductor memory device according to the claim   tion 8, characterized in that the pillar-shaped extension (68a, 68b) of the conductive layer in the form of a trunk comprises a part practically hollow.   10. Semiconductor memory device according to the claim   cation 8, characterized in that a conductive layer in the form of a branch   che has a bent cross section with multiple segments.   11. Semiconductor memory device according to the claim   cation 8, characterized in that the storage capacitor comprises a set of branching conductive layers extending   practically horizontally, and in that one end of each cou-   conductive branch-shaped is connected to the internal surface   of the conductive layer in the form of a trunk.   12. A semiconductor memory device, comprising: (a)   a substrate (10); (b) a transfer transistor on the substrate, the transistor   transfer tor having a source / drain region (16a, 16b); and (c) a storage capacitor electrically connected to the region of   source / drain (16a, 16b), characterized in that the stock capacitor   age includes: a trunk-shaped conductive layer (26a, 26b) having a lower end electrically connected to the source / drain region (16a, 16b), the trunk-shaped conductive layer further having an upper surface and an extension vertical (68a, 68b) extending substantially vertically from the lower end; a branch-shaped conductive layer (62a, 62b), having a substantially cylindrical hollow shape, one end of the conductive layer   in the form of a branch being connected to the upper surface of the neck   conductive trunk-shaped, and the conductive layer in the form of   trunk and the conductive layer in the form of a branch forming an elec-   storage capacitor for storage capacitor; a dielectric layer on bare surfaces of the trunk-shaped conductive layer and the branch-shaped conductive layer; and a conductive layer   higher on the dielectric layer, fulfilling the function of an electro   opposite trode of the storage capacitor.   13. A semiconductor memory device, comprising: (a)   a substrate (10); (b) a transfer transistor on the substrate, the transistor   transfer tor having a source / drain region (16a, 16b); and (c) a storage capacitor electrically connected to the region of   source / drain, characterized in that the storage capacitor   takes: a trunk-shaped conductive layer (26a, 26b) having a lower end electrically connected to the source / drain region (16a, 16b), the trunk-shaped conductive layer further having an upper surface, an inner surface and a vertical extension (80a, 80b) extending substantially vertically from the lower end; a first branch-shaped conductive layer (70a, b) having one end connected to the upper surface of the trunk-shaped conductive layer and extending outwardly   practically vertical from the end; at least a second cou-   branch-shaped conductive che (74a, 74b) having one end connected to the inner surface of the trunk-shaped conductive layer, and extending practically outward from the end,   the conductive layer in the form of a trunk and the first and second layers   conductive branches in the form of a branch forming a stock electrode   storage capacitor age; a dielectric layer on sur-   bare faces of the trunk-shaped conductive layer (26a, 26b; 80a,   b) and first and second conductive layers in the form of a branch   che (70a, 70b; 74a, 74b); and an upper conductive layer on the dielectric layer, performing the function of an opposite electrode of the storage capacitor.   14. A semiconductor memory device according to one which   conch of claims 1, 4, 12 and 13, characterized in that the cou-   The trunk-shaped conductive che further comprises: a lower trunk-shaped portion (26a, 26b) electrically connected to the source / drain region (16a, 16b) and having a T-shaped cross section with   a board; and a portion in the form of an upper trunk extending practically-   vertically from the edge of the lower trunk-shaped part better.   15. Semiconductor memory device according to the claim   cation 14, characterized in that the conductive layer in the form of a branch   che comprises a set of conductive layers in the form of a branch   che extending substantially parallel, and in that a respective end of each layer of the set of branch-shaped conductive layers is connected to the upper surface of the part   lower trunk shape (26a, 26b).   16. A semiconductor memory device according to the claim   cation 14, characterized in that the inner surface of the layer   conductive in the form of a trunk is an inner surface of the upper trunk shape.   17. Semiconductor memory device according to the claim   cation 13, characterized in that the first conductive layer in the form   of branch (70a, 70b) is practically a hollow cylinder.   18. Semiconductor memory device according to the claim   cation 13, characterized in that the second conductive layer in the form   of branch (74a, 74b) has a bent cross section with segments multiple elements.   19. Semiconductor memory device according to the claim   cation 13, characterized in that the second branch-shaped conductive layer (s) comprise a set of additional branch-shaped conductive layers extending substantially parallel, and in that a respective end of each layer of the set of additional branch-shaped conductive layers is connected to the inner surface of the shaped conductive layer trunk.   20. A semiconductor memory device according to one   conch of claims 1, 4, 12 and 13, characterized in that the cou-   The conductive trunk-shaped che also comprises:   lower trunk form (102a, 102b) electrically connected to the   source / drain regions (16a, 16b) and having a U-shaped cross section with an edge; and an upper trunk-shaped portion (116a, 116b) extending substantially vertically from the edge of the portion   lower trunk shape (102a, 102b).   21. Semiconductor memory device according to one of   claims 14 or 20, characterized in that the shaped part   upper trunk is practically a hollow cylinder.   22. Semiconductor memory device according to the claim   cation 21, characterized in that a horizontal section of the part in   upper trunk shape is practically circular or rectangular.   23. A storage capacitor for a semiconductor memory device, the semiconductor memory device comprising a substrate (10) and a transfer transistor on the substrate, the transfer transistor having a source / drain region (16a, 16b) , the storage capacitor comprising: (a) a storage electrode intended to be connected to the source / drain region (16a, 16b); (b) a dielectric (40a, 40b) on the storage electrode; and (c) an opposite electrode (42)   on the dielectric, characterized in that the storage electrode comprises   takes: a trunk-shaped conductor (26a, 26b; 38a, 38b) having a lower end electrically connected to the source / drain region (16a, 16b), the trunk-shaped conductor further having a surface   interior and a vertical extension extending almost vertically-   ment from the lower end; and a branch-shaped conductor (32a, 32b) having an L-shaped cross section, one end of the branch-shaped conductor being connected to the interior surface   of the trunk-shaped conductor (26a, 26b; 38a, 38b).