NL1005631C2 - Semiconductor memory device. - Google Patents

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates generally to semiconductor memory devices and more particularly to a structure of a DRAM (dynamic random access memory) cell consisting essentially of a transfer transistor and a charge storage capacitor.

10 2. Description of the Related Art

Figure 1 is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a DRAM cell mainly consists of a transfer transistor T and a charge storage capacitor C. A source 15 of the transfer transistor T is connected to a corresponding bit line BL and the drain is connected to a storage electrode 6 of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposite electrode 8 of the capacitor C is connected to a constant power source. A dielectric film 7 is present between the storage electrode 6 and the opposite electrode 8.

In the manufacturing process of DRAMs, a two-dimensional capacitor, also known as a planar capacitor, is mainly used in conventional DRAMs with a storage capacity of less than 1M (mega = million) bits. In a DRAM with a memory cell using a planar capacitor, electrical charges are stored on the major surface of a semiconductor substrate so that the major surface must cover a large area. This type of memory cell is therefore not suitable for a DRAM with a high degree of integration. For a 5 highly integrated DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, also referred to as stacked capacitor (stacked type) or slot type (trench type), has been introduced.

With stacked type or 10 slot type capacitors, it is possible to obtain a larger memory in an equal volume. However, for realizing a semiconductor device of even higher integration degree such as a VLSI (very-large-scale integration) circuit with a capacity of 64M bits, a capacitor 15 of a simple three-dimensional structure such as the conventional stacked-type or slot-type capacitor to be inadequate.

A solution to improve capacitor capacitance is to use a fin-type stacked-capacitor as suggested in the article "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electron Devices Meeting, pages 592-595, December 1988 from Ema et al. The fin-type stacked capacitor includes electrodes and dielectric films extending in fin form in a plurality of stacked layers. DRAMs equipped with fin-type stacked capacitors are also disclosed in U.S. Patent 5,071,783 (Taguchi et al), 5,126,810 (Gotou), 5,196,365 (Gotou), and 5,206,787 (Fuj ioka).

Another solution for improving the capacitance of a capacitor is to use a 1005631 3 stacked capacitor of the so-called cylindrical type as suggested in the article "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pages 69-70 of Wakamiya and 5 others. The cylindrical-type stacked capacitor includes electrodes and dielectric films that extend in a cylindrical shape to increase the surface area of the electrodes. A DRAM provided with a cylindrical-type stacked capacitor is also disclosed in U.S. Patent No. 5,077,688 (Kumanoya et al.).

From JP-A 5-198770 (abstract and figure) a semiconductor memory device is known on which the independent present claims 1, 8 and 16 are based, which comprises a tree-shaped capacitor with a trunk-shaped conductive layer and branch-shaped conductive layers connected thereto. .

From US 5 604 148 a semiconductor memory device is known with a tree-shaped capacitor with a trunk-shaped conductive layer with parallel straight branch-like conductive layers hanging from its underside.

In view of the trend towards increased integration density, the size of the DRAM cell in a plane (the area occupied in the plane) should be further reduced. Generally speaking, a reduction in the size of the cell leads to a reduction in the charge storage capacity (capacity). Moreover, as the capacity decreases, the probability of limited errors (soft 30 errors) due to the incident of α-rays increases. Thus, there is still a need in this technique to design a new structure of a storage capacitor that can achieve the same capacity in a smaller planar area as well as a suitable method of manufacturing the structure.

5 SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a semiconductor memory device structured with a tree capacitor that allows an increased area for charge storage.

In accordance with the foregoing and other objects of the invention, a new and improved semiconductor memory device and a method of manufacturing it are provided.

A semiconductor memory device according to the invention has an increased-area tree-shaped capacitor for reliably storing thereon electric charges representative of data. The tree-shaped capacitor comprises a storage electrode consisting of a trunk-shaped conductive layer and one or more branch-like conductive layers. The stem-shaped conduction layer is electrically coupled to one of the source / drain regions of the transfer transistor in the semiconductor memory device and is substantially upright. The branch-shaped guiding layer 25 is connected at one end to the trunk-shaped guiding layer and can be structured in various shapes which allow the branch-shaped guiding layer to have an increased surface area. A dielectric layer is formed over exposed surfaces 30 of the trunk conductor layer and the branch conductor layer and a covering conductor layer is formed over the dielectric layer and serves as the opposite electrode for the tree capacitor.

A method of manufacturing a semiconductor memory device according to the invention comprises a substrate, a transfer transistor with source / drain regions in the substrate and a tree-shaped capacitor electrically coupled to one of the source / drain regions. An insulating layer covering the transfer transistor is formed over the substrate. A stem-shaped conductive layer is formed to penetrate through the insulating layer and thereby be electrically connected to one of the source / drain regions. A guiding layer is formed over the trunk-shaped guiding layer. Another conductive layer electrically connected to the stem-shaped conductive layer and the first conductive layer is then formed. Portions of the first and second conductive layers are selectively etched away to form branch-shaped conductive layers so that the trunk-shaped conductive layer and the branch-shaped conductive layers in combination determine a storage electrode for the tree-shaped capacitor. A dielectric layer is formed over exposed surfaces of the branch-shaped conduction layers and a further conduction layer is formed over the dielectric layer to serve as an opposite electrode of the charge storage capacitor. A method of manufacturing an embodiment of such a semiconductor memory device according to the invention comprises forming a first insulating layer over the substrate covering the transfer transistor. Then, in accordance with the invention, at least one stem-shaped conductive layer is formed over the first insulating layer so that the stem-shaped conductive layer penetrates through the first insulating layer, thereby electrically connecting it to one of the source / drain regions. Then, a first conductive layer is formed over the trunk-shaped conductive layer and over the first insulating layer. Portions of the first guiding layer that lie above the stem-shaped guiding layer are then selectively removed. A second conductive layer electrically connected to the stem-shaped conductive layer and the first conductive layer is then formed. Portions of the first and second conductive layers are selectively etched away to form branch-shaped conductive layers so that the trunk-shaped conductive layer and the branch-shaped conductive layers in combination define a storage electrode for the tree-shaped capacitor. A dielectric layer is formed over exposed surfaces of the branch-shaped conduction layers and a third conduction layer is formed over the dielectric layer to serve as an opposite electrode of the charge storage capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

20

Other objects, features and advantages of the invention will become apparent from the following detailed description of the non-limiting preferred embodiments. The description is made with reference to the accompanying drawings in which: Figure 1 is a circuit diagram of a memory cell of a DRAM device, Figures 2A to 2G are cross-sectional views showing the processing steps for manufacturing a first embodiment of a semiconductor memory cell with a tree-shaped capacitor according to the invention, 1005631 7 Figures 3A to 3D are cross-sectional views showing the processing steps for manufacturing a second embodiment of a semiconductor memory cell with a tree-shaped capacitor according to the invention, Figures 4A to 4C are cross-sectional views showing the machining steps for fabricating a third embodiment of a semiconductor memory cell having a tree capacitor according to the invention, FIGS. 5A to 5C are cross-sectional views showing the machining steps for fabricating a fourth onion Embodiment of a semiconductor memory cell with a tree capacitor according to the invention, Figures 6A to 6D are cross-sectional views showing the processing steps for manufacturing a fifth embodiment of a semiconductor memory cell with a tree capacitor according to the invention. invention, Figures 7A to 7E are cross-sectional views illustrating the machining steps for fabricating a sixth embodiment of a semiconductor memory cell having a tree capacitor according to the invention, Figures 8A to 8E are cross-sectional views illustrating the machining steps for manufacturing a seventh embodiment of a semiconductor memory cell having a tree-shaped capacitor according to the invention, Figures 9A and 9B are cross-sectional views showing the manufacturing steps for manufacturing b. ! 8 of an eighth embodiment of a semiconductor memory cell with a tree capacitor according to the invention, Figures 10A to 10E are cross-sectional views showing the processing steps for fabricating a ninth embodiment of a semiconductor memory cell having a tree capacitor according to the invention. the invention, Figures 11A and 11B are cross-sectional views illustrating the processing steps for fabricating a tenth embodiment of a semiconductor memory cell having a tree-shaped capacitor according to the invention, Figures 12A to 12C are cross-sectional views which the processing steps shown for fabricating an eleventh embodiment of a semiconductor memory cell having a tree-shaped capacitor according to the invention and Figures 13A to 13B are cross-sectional views showing the processing steps for fabricating a twelfth embodiment of a semiconductor memory cell with a tree-shaped capacitor according to the invention.

25 DETAILED DESCRIPTION OF THE

PREFERRED EMBODIMENTS

First preferred embodiment

A description will be given of a first embodiment of a semiconductor memory device with a tree-shaped charge storage capacitor according to the invention with reference to Figures 2A to 2G. De- 1005 v.

This embodiment of the semiconductor memory device is manufactured using a first preferred method of manufacturing a semiconductor memory device according to the invention.

Figure 2A shows that a surface of a silicon substrate 10 is subjected to thermal oxidation using the LOCOS (local oxidation or silicon) technique to form a field oxidation film 12 having a thickness of, for example, about 3,000 Å (angstrom). Then, a gate oxidation film 14 having a thickness of, for example, about 150 Å is formed by subjecting the silicon substrate 10 to a thermal oxidation process. Thereafter, a polysilicon film having a thickness of, for example, about 2,000 Å is applied to the entire surface of the silicon substrate 10 by the CVD (chemical vapor deposition) method or the LPCVD (low pressure CVD) method. In order to obtain a polysilicon film of high conductivity, suitable impurities such as phosphorions are diffused into the polysilicon film. To further increase the conductivity of the film, for example, a heat-resistant metal layer may be applied over the polysilicon film and an annealing treatment is performed to form polycide. The heat resistant metal layer may consist of a tungsten (W) layer applied to a THICKNESS of, for example, about 2,000 A.

Thereafter, a conventional photolithographic and etching process is used to determine and form a polysilicon metalization layer over the wafer serving as word lines WL1 to WL4, see Figure 2A. Using the 30 word lines WL1 to WL4 as masks, an ion implantation process is then performed on the wafer to diffuse a contaminant (such as arsenic ions) into the silicon substrate 1005631 10 10 with an energy of, for example, about 70 KeV and a concentration of, for example, about 1 x 1015 atoms per square centimeter. As a result of this ion implantation, the drain regions 16a and 16b and 5 source regions 18a and 18b are formed in the silicon substrate 10.

In the next step, see Figure 2B, the CVD method is used to apply a planarizing insulating layer 20 such as a layer of borophosphosilicate glass 10 (BPSG) to a thickness of, for example, about 7,000 A. Next, the same method is used for applying an etch protection layer 22 such as a silicon nitride layer over the insulating planarization layer 20 to a thickness of, for example, about 1,000 A. Thereafter, a conventional photolithographic and etching process is used to determine and selectively etch away portions of the etch protection layer 22 and the insulating planarization layer 20 so that storage electrode contact holes 24a, 24b are formed extending from an upper surface of the etch protection layer 22 to the surface of the drain regions 16a, 16b. Then, a thick polysilicon layer is applied over the wafer to a thickness of, for example, about 7,000 A. The thick polysilicon layer can further be diffused with an impurity such as arsenic ions to increase conductivity. Thereafter, a conventional photolithographic and etching operation is performed on the thick polysilicon layer to define and form polysilicon columns 26a, 26b extending from the surface of the drain regions 16a, 16b 30 upwardly through the storage electrode contact holes 24a, 24b. As a result, a recess 25 is determined between the second polysilicon columns 26a, 26b. The 1005631 π polysilicon columns 26a, 26b are to be used as stem-shaped conductive layers in the storage electrodes for the tree-shaped capacitor according to the invention.

In the next step, see Figure 2C, the CVD-5 method is repeatedly used to successively form a first insulating layer 28, a polysilicon layer 30 and a second insulating layer 32 over the wafer. The first and second insulating layers 28, 32 preferably consist of silicon oxide layers. The first insulating layer 28 and the polysilicon layer 30 are each applied to a thickness of, for example, approximately 1,000 A. The second insulating layer 32 must be applied to a minimum of a thickness that fills the recess 25 between the two polysilicon columns 26a, 26b which at this embodiment is at least 7,000 A 15. Furthermore, the polysilicon layer 30 can be diffused with impurities such as arsenic ions to increase conductivity.

In the next step, see Figure 2D, a chemical / mechanical polishing (CMP) operation is performed on the surface of the wafer of Figure 2C to polish away an upper portion of the polysilicon columns 26a and 26b.

Figure 2E then shows that in the next step, a polysilicon layer 34 is formed over the wafer with a thickness of, for example, about 7,000 A. Furthermore, the polysilicon layer 34 can be diffused with impurities such as arsenic ions to increase conductivity. Thereafter, a conventional wafer photolithographic and etching operation is performed to define and selectively etch parts of the polysilicon layer 34, the second insulating layer 32 and the polysilicon layer 30. As a result of this process, the polysilicon layer 34 to 1005631 becomes 12 separate sections 34a and 34b and the polysilicon layer 30 is cut into separate sections 30a and 30b. These sections 34a, 34b and 30a, 30b are to be used as branch-shaped conductive layers in the storage electrodes for the tree-shaped capacitor according to the invention. For discernment purposes, the polysilicon sections 34a, 34b are referred to herein as "upper branch-like guide layers" and the polysilicon sections 30a, 30b are referred to as "hanging branch-like guide layers".

Figure 2F shows that in the subsequent step a wet etching treatment is performed on the wafer with the etching protection layer 22 serving as the etching end point to remove the exposed insulating layers 32, 28. Herewith is the formation of the storage electrodes of the trunk-shaped capacitor for DRAM- cells in the wafer completed.

As shown in Figure 2F, the storage electrodes thus formed are composed of the stem-shaped polysilicon layers 26a, 26b, the upper branch-shaped polysilicon layers 20a, 34b and the substantially L-shaped hanging branch-shaped polysilicon layers 30a, 30b. The stem-shaped polysilicon layers 26a, 26b are electrically coupled to the drain regions 16a and 16b of the transfer transistor in the DRAM, respectively. The upper branch-shaped polysilicon layers 34a, 34b are each connected with the middle portion to the upper of the trunk-shaped polysilicon layers 26a, 26b and are arranged substantially at right angles to them. The substantially L-shaped hanging branch-shaped polysilicon layers 30a, 30b each extend downwardly from the bottom of the upper branch-shaped polysilicon layers 34a, 34b over a predetermined distance and are then bent and extend horizontally.

1005631 13

Figure 2G shows that in the next step, the dielectric films 36a, 36b are formed over the tree storage electrode 26a, 30a, 34a and the 26b, 30b, 34b, respectively. These dielectric films 36a, 36b may be made of dielectric materials such as silicon dioxide (SiO2), silicon nitride, NO (silicon nitride / silicon dioxide), ONO (silicon dioxide / silicon nitride / silicon dioxide), or the like. Then, an opposite electrode made of polysilicon opposite the storage electrodes 26a, 30a, 34a and 26b, 30b, 34b is formed over the dielectric films 36a, 36b. The process for forming the opposite electrode 38 comprises a first step of applying a polysilicon layer using the CVD method to a thickness of, for example, about 1,000 A, a second step of diffusion of impurities from the n- type in the polysilicon layer to increase conductivity as well as a final step of using conventional pholithithographic and etching operations to determine and selectively etch parts of the polysilicon layer. The manufacture of the tree-shaped capacitors in the DRAM has thus been completed.

To complete the manufacture of the DRAM chip, the subsequent steps include the manufacture of 25 bit lines, terminal islands, interconnections, passivations and packaging. These steps involve only conventional techniques and are not related to the essence of the invention so that a detailed description thereof will not be provided.

Second embodiment 110 0 5 6 3 1 30 14

In the foregoing first embodiment, the disclosed tree-shaped capacitor includes only a few hanging branches (ie, branch-shaped polysilicon layers 3 0a, 3 0b) below the top branch-shaped conductive layers (eg, polysilicon layers 34a, 34b).

However, the number of hanging branches is not limited to one and can be two or more. The second embodiment of the invention is a tree-shaped capacitor with two sets of hanging branches consisting of conductive layers which will be described below with reference to Figures 3A to 3D.

The tree-shaped capacitor of the second embodiment is based on the wafer structure of Figure 2B. Elements in Figures 3A to 3D that are identical to those in Figure 2B are designated by the same reference numerals.

Figure 3A together with Figure 2B shows that the CVD method is used to successively form successive layers of insulation and polysilicon on the wafer of Figure 2, comprising a first insulation layer 40, a first polysilicon layer 42, a second insulation layer 44, a second polysilicon layer 46 and a third insulating layer 48. The insulating layers 40, 44, 48 consist of insulating material such as silicon oxide. The insulating layers 40, 44 and the polysilicon layers 42, 46 are each applied to a thickness of, for example, about 1,000 A and the insulating layer 48 is applied to a thickness of, for example, about 7,000 A. Furthermore, the polysilicon layers 42, 46 can be diffused with impurities such as arsenic ions to increase conductivity.

In the next step, see Figure 3B, the CMP process is performed on the surface of the wafer of Figure 3A to polish off an upper part of the wafer until the top of the polysilicon columns 26a, 26b is exposed.

In the subsequent step, see Figure 3C, a polysilicon layer 50 is applied over the wafer to a thickness of, for example, about 1,000 A. Further, the polysilicon layer 50 can be diffused with impurities such as arsenic ions to increase conductivity. Thereafter, conventional wafer photolithography and etching is performed to define and selectively etch away portions of the polysilicon layer 50, the third insulating layer 48, the second polysilicon layer 46, the second insulating layer 40, and the first polysilicon layer 42. As a result From this process, the polysilicon layer 50 is cut into separate sections 50a and 50b, the polysilicon layer 46 is cut into separate sections 46a and 46b, and the polysilicon layer 42 is cut into separate sections 42a and 42b. These sections 50a, 50b, 46a, 46b, 42a, 42b serve for use as branch conductor layers in the storage electrodes for the tree capacitor of the invention.

For purposes of discernment, the polysilicon sections 50a, 50b are referred to herein as "upper branch-shaped guide layers" and the polysilicon sections 46a, 46b, 42a, 42b are referred to as "hanging branch-shaped guide layers".

Next, the wafer is etched wet with the etch protection layer 22 serving as the etching end point for removing the exposed insulating layers 40, 44, 48. This completes the formation of the storage electrodes for the tree capacitor of the DRAM cells in the wafer. decorated.

As shown in Figure 3C, the storage electrodes thus formed consist of stem-shaped polysilicon layers 1005631 16 26a, 26b, the upper branch-shaped polysilicon layers 50a, 50b and the substantially L-shaped hanging branch-shaped polysilicon layers 42a, 46a and 42b, 46b. The stem-shaped polysilicon layers 26a, 26b are electrically coupled to drain regions 16a and 16b of the transfer transistors in the DRAM, respectively. The upper branch-shaped polysilicon layers 50a, 50b are joined to the top of the trunk-shaped polysilicon layers 26a, 25b and are disposed substantially at right angles thereto. The two pairs of substantially L-shaped hanging branch-shaped polysilicon layers 46a, 42a and 46b, 42b each extend downwardly from the bottom of the upper branch-shaped polysilicon layers 50a, 50b over a defined distance and are then bent to extend horizontally.

In the next step, see Figure 3D, dielectric films 52a, 52b are formed on the tree storage electrodes 50a, 46a, 42a and 50b, 46b, 42b, respectively. After this, an opposite polysilicon electrode 54 is formed over the dielectric films 52a, 52b. The process for forming the opposite electrode 54 comprises a first step of applying a polysilicon layer using the CVD method, a second step of diffusing n-type impurities into the polysilicon layer to increase the conductivity thereof and a final step of using conventional photolithographic and etching operations to selectively etch away portions of the polysilicon layer. After this, the manufacture of the tree-shaped capacitors in the DRAM is finished.

30

Third preferred embodiment 1005631 17

In the foregoing first and second embodiments, the one pair of hanging branches nearest the stem-shaped guiding layer is separated from the etching protection layer below (ie, the etching protection layer 22). However, the invention is not limited to such a structure. The third embodiment of the invention includes a tree-shaped capacitor in which the one pair of hanging branches is closest to the trunk-shaped conduction layer in contact with the etch protection layer as will be described below with reference to Figures 4A to 4C.

The tree-shaped capacitors of the third embodiment are also based on the structure of Figure 2B. Elements in Figures 4A to 4C which are identical to those of Figure 2B are identified by the same reference numerals.

As Figure 4A shows together with Figure 2B, the wafer of Figure 2B is subjected to a CVD operation to successively form successive layers of insulating material and polysilicon, including a first polysilicon layer 56, a first insulating layer 58, a second polysilicon layer 60 and a second insulating layer 62.

Then, see Figure 4B, the CMP process is performed on the surface of the wafer of Figure 4A to etch away an upper portion of the wafer until the surface of the upper portion of the first polysilicon layer 56 located above the polysilicon columns 26a, 26b or until the top of the polysilicon columns 26a, 26b is exposed.

In a next step, see figure 4C, a silicon layer 64 is applied to the wafer. Thereafter, a conventional photolithographic and etching operation is performed 1005631 18 on the wafer to determine and selectively etch parts of the polysilicon layers 56, 60 and 64. As a result of this process, the polysilicon layer 56 is cut into separate pieces 56a and 56b, the polysilicon layer 60 is cut into 5 separate sections 60a and 60b and the polysilicon layer 64 is cut into separate sections 64a and 64b. These sections 56a, 56b, 60a, 60b, 64a, 64b serve as branch conductor layers in the storage electrodes for the tree-shaped capacitor according to the invention.

The wafer is then wet etched with the etch protection layer 22 acting as the etching end point to remove the exposed insulating layers 58,62. This completes the formation of the storage electrodes of the tree-shaped capacitor of DRAM cells in the wafer.

As shown in Figure 4C, the storage electrodes thus formed consist of the stem-shaped polysilicon layers 26a, 26b, the upper branch-shaped polysilicon layers 64a, 64b and two pairs of substantially L-shaped hanging branch-shaped polysilicon layers 56a, 60a and 56b, 60b. The stem polysilicon layers 26a, 26b are electrically coupled to the drain regions 16a and 16b of the transfer transistors in the DRAM, respectively. The top branch polysilicon layers 64a, 64b are bonded to the top of the trunk polysilicon layers 26a, 26b and are arranged substantially at right angles to them. The two pairs of substantially L-shaped hanging branch-shaped polysilicon layers 56a, 60a and 56b, 60b each extend downwardly from the bottom of the branch-shaped polysilicon layers 64b, 64b and then bend to extend horizontally. stretch. A distinctive part of this embodiment from the previous embodiments is that the horizontal segments of the pairs of substantially L-shaped hanging branch-shaped polysilicon layers 56a, 56b each come into contact with the etch protection layer 22.

5 Fourth preferred embodiment

The fourth preferred embodiment is substantially the same in structure as the previous third embodiment, but differs in the processing steps used to form the structure. These different processing steps will be described below with reference to Figures 5A to 5C.

The tree-shaped capacitor of the fourth embodiment is based on the structure of Figure 2B. Elements in Figures 5A to 5C which are identical to those in Figure 2B are identified by the same reference numerals.

After the formation of the wafer structure of Figure 2B, first see Figure 5A together with Figure 2B, insulating spacers 66a, 66b are formed consisting of insulating materials such as silicon dioxide (SiO 2) on the side walls of the polysilicon columns 26a, 26b . The process of forming the insulating spacers 66a, 66b includes a first step using the CVD method for depositing a silicon dioxide (SiO 2) layer to, for example, a thickness of 1,000 Å and a second step of reset the silicon dioxide (SiO2) layer. Thereafter, the CVD method is repeatedly applied to successively apply a first polysilicon layer 68, a first insulating layer 70, a second polysilicon layer 72, and a second insulating layer 74.

In the next step, see Figure 5B, the CMP operation is performed on the surface of the wafer of fi 1005631 20 gure 5A to polish off an upper part of the wafer until the surface of the upper segment of the first polysilicon layer 68 or the top of the polysilicon columns 26a, 26b is exposed.

In the next step, see Fig. 5C, a polysilicon layer 76 is applied over the wafer. Thereafter, a conventional wafer photolithographic and etching operation is performed to determine and selectively etch away portions of the polysilicon layers 68, 62 and 76. As a result of this process, the polysilicon layer 68 is cut into separate sections 68a and 68b, the polysilicon layer 72 cut into separate sections 72a and 72b and the polysilicon layer 76 is cut into separate sections 76a and 76b. These sections 68a, 68b, 72a, 72b, 76a, 76b will be used as branch conductor layers of the charge storage electrodes of the tree capacitor of the invention.

After this, the wafer is etched wet with the etch protection layer 22 serving as the etching end point for removing the exposed insulating layers 70, 74. Also, the formation of the storage electrodes for the tree capacitor of DRAM cells in the wafer is completed.

As Fig. 5C shows, the storage electrodes thus formed consist of the stem-shaped polysilicon layers 26a, 26b, the upper branch-shaped polysilicon layers 76a, 76b, a pair of substantially L-shaped hanging branch-shaped polysilicon layers 72a, 72b, and another pair of substantially L-shaped hanging branch-shaped guide layers 68a, 68b. The stem-shaped polysilicon layers 26a, 26b are electrically coupled to the drain regions 16a and 16b of the transfer transistors in the DRAM, respectively. The branch-shaped polysilicon layers 76a, 76b are joined to the top of the trunk-shaped polysilicon layers 26a, 26b and are substantially at right angles thereto. The substantially L-shaped hanging branch-shaped polysilicon layers 72a, 72b each extend downwardly from the bottom of the upper branch-shaped polysilicon layers 76a, 76b over a defined distance and are then bent to extend horizontally. Each of the substantially L-shaped hanging branch-shaped polysilicon layers 68a, 68b is in contact with the top segment with the top of the polysilicon columns 26a, 26b with the two vertical segments separated from each other by the insulating spacers 66a, 66b with respect to of the side walls of the polysilicon columns 26a, 26b and wherein the two bottom horizontal segments are in contact with the etch protection layer 22.

15

Fifth preferred embodiment

The fifth preferred embodiment of the invention comprises a tree-shaped capacitor having two pairs of substantially L-shaped hanging branches, a pair of 20 hanging branches of which are closest to the trunk-shaped conduction layer and have vertical segments in contact with the side walls of the trunk-shaped conduction layer and horizontal segments separated from the etch protection layer located below. This embodiment will be described below with reference to Figures 6A to 6D.

The tree-shaped capacitor of the fifth embodiment is based on the structure of Figure 2A. Elements in Figures 6A to 6D which are identical to those in Figure 2A are designated by the same reference numerals.

Starting from the wafer of Figure 2A, see Figure 6A together with Figure 2A, the CVD method 1005631 22 is applied to apply an insulating planarization layer 80 such as a borophosphosilicate glass (BPSG) layer. Then, the same method is used to successively form an etch protection layer 82, which preferably consists of a silicon nitride layer and an insulating layer such as a silicon dioxide (SiO 2) layer 84, to a thickness of, for example, about 1,000 A. Then, a conventional photolithographic and etching operation used for defining and selectively etching away parts of the insulating layer 10 (SiO 2) 84, the etching protective layer 82 and the insulating plating layer 80. As a result of this process, storage electrode contact holes 85a, 85b are formed which form from the top surface of the insulating layer ( SiO2) 84 extend to the surface of the drain regions 16a, 16b. Then, a thick polysilicon layer is applied over the wafer to a thickness of, for example, about 7,000 A. The thick polysilicon layer can be further diffused with impurities such as arsenic (As) ions to increase its conductivity. Thereafter, a conventional photolithographic and etching operation is performed on the thick polysilicon layer to define and form the polysilicon columns 86a, 86b extending upwardly from the surface of the drain regions 16a, 16b through the storage electrode contact holes 85a, 85b.

In the next step, see Figure 6B, the CVD method is successively used to form alternative layers of insulation and polysilicon, comprising a first polysilicon layer 88, a first insulating layer 90, a second polysilicon layer 92 and a second insulating layer 94.

In the next step, see Figure 6C, the CMP process is applied to the surface of the wafer of Figure 6B to polish away an upper portion of the 1005631 23 wafer until the surface of the upper segment of the first polysilicon layer is 88 or continue to polish down until the tops of the polysilicon columns 86a, 86b are exposed.

Figure 6D shows that in the next step, a poly silicon layer 96 is applied over the wafer. Thereafter, a conventional photolithographic and etching operation is performed on the wafer to successively selectively etch the polysilicon layers 88, 92 and 96. As a result of this process, the polysilicon layer 88 is cut into separate sections 88a and 88b, the polysilicon layer 92 is separate sections 92a and 92b and the polysilicon layer 96 is cut into separate sections 96a and 96b. These sections 88a, 88b, 92a, 92b, 96a, 96b serve as branch conductive layers in the storage electrodes of the tree-shaped capacitor according to the invention for use.

Then, the wafer is etched wet with the etch protection layer 82 serving as the etching end point to remove the exposed insulating layers 94, 90 and 84.

This completes the formation of the storage electrodes for the tree capacitor of DRAM cells in the wafer.

Figure 6D shows that the storage electrodes thus formed comprise the stem-shaped polysilicon layers 86a, 86b, the upper branch-shaped polysilicon layers 96a, 96b as well as two pairs of substantially L-shaped hanging branch-shaped polysilicon layers 88a, 92a and 88b, 92b. The stem-shaped polysilicon layers 86a, 86b are electrically coupled to the drain regions 16a, 16b of the transfer transistors in the DRAM, respectively. The top branch polysilicon layers 96a, 96b are bonded to the top of the trunk polysilicon layers 86a, 86b and are substantially 1005631 24 disposed at right angles thereto. The two pairs of substantially L-shaped hanging branch-shaped polysilicon layers 88a, 92a and 88b, 92b each extend downwardly from the bottom of the branch-shaped polysilicon layers 96a, 96b and then deflect to extend horizontally. Furthermore, the vertical segment of the substantially L-shaped hanging branch-shaped polysilicon layers 88a, 88b are each in contact with the side walls of the trunk-shaped polysilicon layers 86a, 86b and have a horizontal segment spaced from the etch protection layer 82.

Sixth preferred embodiment

In the foregoing embodiments, the hanging branches are each substantially L-shaped and consist of two straight segments coupled together at right angles. However, the invention is not limited to such a structure and the hanging branches may consist of three or more segments. The sixth embodiment of the invention includes a tree-shaped capacitor with a hanging branch-shaped conductive layer consisting of four segments, which will be described with reference to Figures 7A to 7E.

The tree-shaped capacitor of the sixth embodiment is based on the structure of Figure 2A. Elements in Figures 7A to 7E which are identical to those in Figure 2A are designated by the same reference numerals.

The wafer of Figure 2A, see Figure 7A together with Figure 2A, is subjected to the CVD method of applying an insulating planarization layer 98 such as a borophosphosilicate glass (BPSG) layer. The same method is then used to form an etch protection layer 100 such as a silicon nitride layer. Thereafter, a conventional photolithographic and etching operation is used to define and selectively etch away portions of the etch protection layer 100 and the insulating planarization layer 98 to form storage electrode contact holes 102a, 102b extending from the top surface of the etch protection layer 100 to the surface of the drain areas 16a, 16b. Then, a thick polysilicon layer 104 is applied to the wafer 10 to a thickness of, for example, 7,000 A. The thick polysilicon layer can further be diffused with impurities such as arsenic ions to increase conductivity. Thereafter, a conventional photolithographic processing is used to form a photoresist layer 106 which is used as a mask for etching the exposed portion of the thick polysilicon layer. As a result, protruding polysilicon layers 104a, 104b are formed which extend upwardly from the surface of the drain regions 16a, 16b through the storage electrode contact holes 102a, 102b.

In the next step, see Figure 7B, a photo-resist erosion technique is used to remove a surface portion of the photoresist layer 106, leaving a dilute photoresist layer 106a. This also makes it possible to expose an edge portion of the protruding polysilicon layers 104a, 104b.

In a next step, see Figure 7C, an anisotropic etching operation is used on the wafer until the etching protection layer 100 is exposed. The photoresist layer 106a is then removed. As a result of this process, the protruding polysilicon layers 104a, 104b are each formed into layers 104c, 104d with a stepped shape 5! 26 shaped sidewalls 104e. In this embodiment, the stepped side walls 104e are each formed with at least one shoulder-shaped portion 104f.

The next steps, see Figure 7D, are essentially the same as those used to form the wafer of Figures 2C and 2D. First, the CVD method is successively used to form a first insulating layer 108, a polysilicon layer 110 and a second insulating layer 112. Then, the CMP operation is performed on the wafer to polish off an upper portion of the wafer until the top of the protruding polysilicon layers 104c, 104d are exposed.

Figure 7E shows that in the next step, a polysilicon layer 114 is applied over the wafer to a thickness of, for example, about 1,000 A. The polysilicon layer 114 can be diffused with impurities such as arsenic ions to increase conductivity. Thereafter, a conventional photolithographic and etching operation is applied to the wafer to selectively define and etch portions of the polysilicon layer 114, the second insulating layer 112, and the polysilicon layer 110. As a result of this process, the polysilicon layer 114 is cut into separate sections 114a, 114b and the polysilicon layer 110 is cut into separate sections 110a, 110b. These sections 114a, 114b and 110a, 110b serve for use as branch-shaped conductive layers in the storage electrodes of the tree-shaped capacitor according to the invention.

Then, the wafer is etched wet with the etch protection layer 100 serving as the etching end point to remove the exposed insulating layers 112, 108. This completes the formation of the storage electrodes for the 1005631 27 tree-shaped capacitor of DRAM cells in the wafer.

As shown in Figure 7E, the storage electrodes thus formed consist of the stem-shaped protruding polysilicon layers 104c, 104d, the upper branch-shaped polysilicon layers 114a, 114b, and two pairs of four-segment hanging branch-shaped polysilicon layers 110a, 110b. The stem-shaped protruding polysilicon layers 104c, 104d are electrically coupled to the drain regions 16a and 16b of the transfer transistors in the DRAM, respectively. The top branch polysilicon layers 114a, 114b are bonded to the top of the trunk protruding polysilicon layers 104c, 104d and are substantially at right angles to them. The four-segment hanging branch-shaped polysilicon layers 110a, 110b extend downwardly from the bottom of the branch-shaped polysilicon layers 114a, 114b with four substantially straight segments.

In accordance with the invention, the multi-segment hanging branch-shaped polysilicon layers are not limited to the previously disclosed four-segment branches. Should five or more segments be desired, photoresist erosion and anisotropic etching can be repeatedly performed on the wafer of Figures 7B and 7C to contour the side walls of the protruding polysilicon layers with more shoulder-like portions.

Seventh Preferred Embodiment In the previous six embodiments, the CMP process is used to cut polysilicon layers into separate sections. However, the invention is not limited to the use of the CMP process. Alternatively, conventional photolithographic and etching methods can be used to cut the same silicon layers into separate sections. The use of such methods is described below with reference to Figures 8A to 8E.

The tree-shaped capacitors of the seventh embodiment are based on the structure of Figure 2B. Elements in Figures 8A to 8E that are identical to those in Figure 2B are designated by the same reference numerals.

Starting from the wafer of Figure 2B, first see Figure 8A together with Figure 2B, a CVD method is applied for successively forming a first insulating layer 116, a first polysilicon layer 118, a second insulating layer 120, a second polysilicon layer 122 and a third insulating layer 124, each of which is applied to a thickness of, for example, approximately 1,000 A. The insulating layers 116, 120, 124 each preferably consist of silicon dioxide (SiO 2) layers. Furthermore, the polysilicon layers 118, 122 can be diffused with impurities such as arsenic ions to increase conductivity.

In the next step, see Figure 8B, a conventional photolithographic processing is used to form a photoresist layer 126 over the wafer. Thereafter, anisotropic etching is performed on the wafer for successively etching away exposed parts of the third insulating layer (SiO2) 124, the second polysilicon layer 122, the second insulating layer (SiO2) 120, the first polysilicon layer 118, and the first insulating layer (SiO2) 116 until the top of the polysilicon columns 26a, 26b is exposed. As a result of this process, storage electro contact holes 128a, 128b are formed which extend from the top surface of the photoresist layer 126 to the top of the polysilicon columns 26a, 26b through which the insulating layers (SiO 2) 116 , 120, 124 and the polysilicon layers 118, 122 are cut into separate sections. The photoresist layer 126 is then removed.

Figure 8C shows that in the next step, a poly-silicon layer 130 is applied over the wafer to fill the storage electrode contact holes 128a, 128b. Thereafter, a conventional photolithographic and etching operation is used to define and form two substantially T-shaped polysilicon layers 130a, 130b connected to the top of the polysilicon columns 26a, 26b. In these embodiments, the T-shaped polysilicon layers 130a, 130b and the polysilicon columns 26a, 26b in combination form the stem-shaped conduction layer in the tree-shaped capacitor of the present invention.

Alternatively, the polysilicon can be refilled into the storage electrode contact holes 128a, 128b to form columnar conductive layers. Preferably, the refilling process comprises a first step of applying a polysilicon layer using the CVD method and a second step of etching back the polysilicon layer or alternatively, the refilling process comprises a first step of applying a polysilicon layer only to a certain thickness on the inner wall of the storage electrode contact holes 128a, 128b (which are not completely filled by the polysilicon layer) and a second step of performing a conventional photolithographic and etching operation on the wafer to form U-shaped conductive layers on the top of the polysilicon columns 26a, 26b.

1005631 30

As shown in Figure 8D, in the next step, a conventional photolithographic and etching operation is used to define and selectively etch away portions of the third insulating layer (SiO2) 124, the second polysilicon layer 122, the second insulating layer (SiO2) 120, and the first polysilicon layer 118. As a result of this process, the polysilicon layer 118 is cut into separate sections 118a and 118b and the polysilicon layer 122 is cut into separate sections 122a and 122b. These sections 118a, 118b and 122a, 122b will be used as branch conductor layers at the storage electrodes for the tree capacitor of the invention.

In the next step, see Figure 8E, the wafer is etched wet with the etch protection layer 22 serving as the etching end point for removing the exposed insulating layers (SiO 2) 124, 120 and 116. This completes the formation of the storage electrodes for the tree capacitor of DRAM cells in the wafer completed.

As shown in Figure 8E, the storage electrodes thus formed consist of the columnar stem-shaped polysilicon layers 26a, 26b, the substantially T-shaped stem-shaped polysilicon layers 130a, 130b, and two pairs of three-segment hanging branch-shaped polysilicon layers 118a, 122a and 118b, 122b . The columnar stem-shaped polysilicon layers 26a, 26b are electrically coupled to the drain regions 16a and 16b of the transfer transistors in the DRAM, respectively. The substantially T-shaped stem-shaped polysilicon layers 130a, 130b are joined to the top of the columnar stem-shaped polysilicon layers 30 26a, 26b. The two pairs of the three-segment hanging branch-shaped polysilicon layers 118a, 122a and 118b, 122b are each connected to the vertical segment of the 10, substantially T-shaped stem-shaped polysilicon layers 130a, 130b.

Eighth Preferred Embodiment The eighth embodiment of the invention is similar in structure to the previous seventh embodiment except that the substantially T-shaped stem-shaped guide layer herein is modified into a columnar stem with a hollow interior. This embodiment is described below with reference to Figures 9A and 9B.

The tree-shaped capacitor of the eighth embodiment is based on the structure of Figure 8B. Elements in Figures 9A and 9B which are identical to those in Figure 8B are designated by the same reference numerals.

CVD method is used, see Figures 9A and 8B first, to deposit a polysilicon layer on the wafer of Figure 8B which is then etched back to form sidewall spacers 132a, 132b on the inner walls of the storage electrode contact holes 128a, 128b. The sidewall spacers 132a, 132b each form a columnar stem-shaped guide layer connected to the top of the polysilicon columns 26a, 26b.

In the next step, see Figure 9B, a conventional photolithographic and etching operation is used to define and selectively etch the third insulating layer 124, the second polysilicon layer 122, the second insulating layer 120 and the first polysilicon layer 118. As a result of this process the polysilicon layer 118 is cut into separate sections 118a and 118b and the polysilicon layer 120 is cut into separate sections 122a and 122b. These sections 118a, 118b and 122a, 122b serve as branch-shaped conductor layers at the storage electrode for the tree-shaped capacitor of the invention.

The wafer is then etched wet with the etch protection layer 22 serving as the etching end point to remove the 5 exposed insulating layers (SiO 2) 124, 120 and 116. This completes the formation of the storage electrodes of the tree-shaped capacitor of the DRAM cells in the wafer.

As shown in Figure 9B, the storage electrodes thus formed consist of the columnar stem-shaped polysilicon layers 26a, 26b, the likewise columnar stem-shaped polysilicon layers 132a, 132b, each of which may be provided with a hollowed-out interior and two pairs of three-segment branch-shaped polysilicon layers 118a, 122b and 118b, 122b. This embodiment differs from the foregoing embodiment shown in Figure 8E only in that the T-shaped polysilicon layers 130a, 130b are replaced by the columnar polysilicon layers 132a, 132b each having a hollow interior.

Ninth preferred embodiment

The ninth embodiment is a tree-shaped capacitor with a T-shaped stem-shaped conductive layer which will be described below with reference to Figures 10A to 10E.

The tree-shaped capacitor of the ninth embodiment is based on the wafer structure of Figure 2A. Elements in Figures 10A to 10E that are identical to those of Figure 2A are identified by the same reference numerals.

10 0 5 6 3 1 33

The CVD method is used, see Figure 10A together with Figure 2A, to form an insulating planarizing layer 150a on the wafer of Figure 2A such as a borophosphosilicate glass (BPSG) layer. Then, the same method is used to form an etch protection layer 152 such as a silicon nitride layer. Thereafter, a thick insulating layer such as a silicon dioxide (SiO2) layer is applied over the wafer to a thickness of, for example, about 7,000 A. Thereafter, a conventional photolitho-10 graphic and etching operation is used to define and form insulating columns 154a, 154b which are substantially above the drain areas 16a, 16b.

In the next step, see Figure 10B, the CVD method is applied to successively form a first insulating layer 156, a first polysilicon layer 158 and a second insulating layer 160, each of which is applied to a thickness of, for example, approximately 1,000 A. The insulating layers 156, 160 each preferably consist of silicon dioxide (SiO 2) layers. Furthermore, the polysilicon layer 158 can be diffused with impurities such as arsenic ions to increase conductivity.

In the next step, see Figure 10C, a conventional photolithographic processing is used to form a photoresist layer 162 over the wafer. Thereafter, anisotropic etching is applied to the wafer to etch away exposed parts of the second insulating layer (SiO2) 160, the first polysilicon layer 158, the first insulating layer (SiO2) 156, the insulating columns 154a, 154b, the etching protective layer 152, the insulating planarizing layer 150 and the gate oxide film 14 until the top surface of the drain regions 16a, 16b is exposed. As a result of this process, storage electrode contact holes 164a, 164b are formed extending from the top surface of the drain regions 16a, 16b to the top surface of the second insulating layer 160.

In the next step, see Figure 10D, a polysilicon layer 166 is applied which fills the storage electrode contacts holes 164a, 164b. Then, a conventional photolithographic and etching operation is used to define and shape the polysilicon layer 166 into two T-shaped stem-shaped guide layers 166a, 166b which are electrically connected to the drain regions 16a, 16b.

In the next step, see Figure 10E, a conventional photolithographic and etching operation is performed on the wafer to define and selectively etch away parts of the second insulating layer 160 and the first polysilicon layer 158. As a result of this process, the polysilicon layer 158 cut into separate sections 158a and 158b. These sections 158a, 158b will be used as branch conductor layers in the storage electrodes for the tree capacitor of the invention.

Next, the wafer is etched wet with the etch protection layer 152 serving as the end point to remove the exposed insulating layers (SiO 2) 160, 156 and the remaining part of the insulating columns 154a, 154b. This completes the formation of the storage electrodes for the tree capacitor of the DRAM cells in the wafer.

As shown in Figure 10E, the storage electrodes thus formed consist of the substantially T-shaped stem-shaped polysilicon layers 166a, 166b and the three-segment hanging branch-shaped polysilicon layers 158a, 158b.

Tenth preferred embodiment 1005631 35

The tenth embodiment is substantially similar in structure to the ninth embodiment disclosed above except that the substantially T-shaped stem-shaped guiding layers are hollowed out to increase the charge storage area. This embodiment is described below with reference to Figures 11A and 11B.

The tree-shaped capacitor of the ninth embodiment is based on the structure shown in Figure 10C. Elements in Figures 11A and 11B which are identical to those in Figure 10C are denoted by the same reference numerals.

The CVD method, first see Figure 11A together with Figure IOC, is used to apply a polysilicon layer 168 to the wafer of Figure IOC in such a way that the polysilicon layer 168 is deposited on the interior walls of the storage electrode contacts 164a, 164b. deposited to only a specific thickness, still providing a hollowed-out interior in the storage electrode contact holes 164a, 164b. Thereafter, a conventional photo-lithographic and etching operation is used to define and selectively etch away portions of the polysilicon layer 168. As a result of this process, the remaining polysilicon layers 168a and 168b each serve as a substantially T-shaped stem conductive layer with a hollow interior 25 for the storage electrode.

In the next step, see Figure 11B, a conventional photolithographic and etching operation is performed on the wafer to determine and selectively etch away portions of the second insulating layer 160 and the first polysilicon layer 158. As a result of this process, the polysilicon layer 158 cut into separate sections 158a and 158b. These sections 158a, 158b will be used as branch-shaped conductor layers at the storage electrodes for the tree-shaped capacitor of the invention.

After this, the wafer is etched wet with the etch protection layer 152 serving as the etching end point for removing the exposed insulating layers (SiO 2) 160, 156 and the remaining portion of the insulating columns 154a, 154b. This completes the formation of the storage electrodes for the tree-shaped capacitor of DRAM cells in the wafer.

As shown in Figure 11B, the storage electrodes thus formed consist of the substantially T-shaped stem-shaped polysilicon layers 168a, 168b, each having a hollow interior and the three-segment hanging branch-shaped polysilicon layers 158a, 158b. The embodiment shown in Figure 11B is substantially similar to the previous embodiment shown in Figure 10E except that the substantially T-shaped stem-shaped polysilicon layers 166a, 166b in the previous embodiment has been replaced with the main chamber T-shaped stem-shaped polysilicon layers 168a, 168b each having a hollow interior.

In this tenth and in the ninth embodiment described above, the columnar insulating layers can be formed into other shapes by various means. For example, the photoresist erosion technique can be used to form insulating layers with stepped sidewalls. Also, instead of the structure shown in Figure 10A when isotropic etching such as wet etching is used instead of anisotropic etching, the thick insulating layer can be reformed into a substantially triangular shape and if sidewall spacers are formed on the inner walls of the insulating columns 100a, 154b, 154b, columnar insulating layers of other shapes can be obtained. The branch-shaped conductive layer can thus be formed in different shapes depending on the design choice.

Similarly, the columnar polysilicon layers can be formed with other shapes by various means to increase the surface area thereof. For example, in the case of Figure 2B, isotropic etching can be used instead of anisotropic etching and the thick polysilicon layers can be reformed into a substantially triangular shape.

Eleventh preferred embodiment

In the foregoing first to tenth embodiments, the tree-shaped capacitor comprises only a single level of storage electrodes. However, the number of tree levels is not limited to one but can be two or more. The eleventh embodiment includes a tree-shaped capacitor with two levels of storage electrodes comprising an upper level of storage electrodes stacked on a lower level of storage electrodes which will be described below with reference to Figures 12A to 12C.

The tree-shaped capacitor of the eleventh embodiment is based on the wafer structure of Figure 3B.

Elements in Figures 12A to 12C which are identical to those in Figure 3B are identified by the same reference numerals. The wafer storage electrodes shown in Figure 3B are used as the bottom level of storage electrodes. The following description is directed solely to the formation of the top level of storage electrodes stacked directly on top of the bottom level of storage electrodes.

1005631 38

A polysilicon layer 170, see Figure 12A together with Figure 3B, as well as an insulating layer 171 are successively formed over the wafer of Figure 3B to a thickness of, for example, 1,000 A. The insulating layer 171 preferably consists of a silicon dioxide layer. Thereafter, a conventional photolithographic and etching operation is used to determine and selectively etch portions of the insulating layer 171 to form contact holes 174a, 174b extending from the top surface of the insulating layer 171 to the top surface of the polysilicon layer 170. After this, a thick polysilicon layer is applied over the wafer to a thickness of about, for example, 7,000 A. The thick polysilicon layer can be diffused with impurities such as arsenic (As) ions to enhance its conductivity. Thereafter, a conventional photolithographic and etching operation is performed on the wafer to form the thick polysilicon layer into two columnar polysilicon layers 172a, 172b. These polysilicon columns 172a, 172b extend substantially upright from the top surface of the polysilicon layer 170 through the contact holes 174a, 174b toward the top of the wafer. This allows the polysilicon columns 172a, 172b to be in electrical contact with the bottom level of storage electrodes.

The same process steps, see Figure 12B, as described with reference to Figures 3A to 3B, are again used to form the semiconductor structure shown in Figure 12B, ie the CVD operation is first used for deposition of 30 alternating layers consisting of the insulating layers 176, 180, 184 and the polysilicon layers 178, 182 and then the CMP process is applied to the wafer until the top of the polysilicon columns 172a, 172b.

The same process steps, see Figures 12B and 12C, as described with reference to Figure 3C are used to form the semiconductor structure shown in Figure 12C. First, a polysilicon layer 188 is applied to a thickness of about, for example, 1,000 A. Then a conventional photolithographic and etching operation is used to define and selectively etch away parts of the polysilicon layer 188, the insulating layer 184, the polysilicon layer 182, the insulating layer 180 , the polysilicon layer 178, the insulating layers 176 and 171, the polysilicon layer 170, the insulating layer 48, the polysilicon layer 46, the insulating layer 44, and the polysilicon layer 42. As a result of this process, the polysilicon layer 188 is cut into separate sections 188a and 188b. The polysilicon layer 182 is cut into separate areas 182a and 182b and the polysilicon layer 178 is cut into separate sections 178a and 178b, the polysilicon layer 170 is cut into separate sections 179a and 179b, the polysilicon layer 46 is cut into separate sections 46a and 46b, and the polysilicon layer 42 is cut into separate sections 42a and 42b.

These sections 188a, 188b, 182a, 182b, 178a, 178b, 170a, 170b, 46a, 46b, 42a and 42b serve as branch conductor layers for the tree-shaped capacitors of the DRAM cells in the wafer.

Then, the wafer is etched wet with the etch protection layer 22 serving as an etching end point to remove the exposed insulating layers 184, 180, 176, 30 171, 48, 44 and 40. This makes the formation of the storage electrodes for the tree condenser of DRAM cells in the wafer completed.

10 0 5 6 3 ί 40

As Figure 12C shows, the storage electrodes thus formed consist of two levels of storage electrodes, the lower level comprising stem-shaped conductive layers 26a, 26b, the upper branch-shaped conductive layers 5 170a, 170b, the substantially L-shaped hanging branch-shaped conductive layers 42a, 46a and 42b, 46b and the upper level comprises the stem-shaped guide layers 172a, 172b, the upper branch-shaped guide layers 188a, 188b and the substantially L-shaped hanging branch-shaped guide layers 178a, 182a and 178b, 182b. This embodiment has the advantage of a significant increase in the charge storage area of the tree-shaped capacitor.

Twelfth Preferred Embodiment In the foregoing embodiments, the bottoms of the polysilicon columns are directly electrically connected to the drain regions of the transfer transistors in the DRAM cells. However, the invention is not limited to such a structure. The twelfth embodiment relates to a tree-shaped capacitor in which the polysilicon columns are electrically connected via a conductive layer to the drain regions of the transfer transistors as described below with reference to Figures 13A and 13B.

The tree-shaped capacitor of the twelfth embodiment is based on the wafer structure of Figure 2A. Elements in Figures 13A and 13B that are identical to those in Figure 2A are identified by the same reference numerals.

The CVD method, see Figure 13A together with Figure 2A, is used to apply an insulating planarization layer 190 such as a layer consisting of boro-1005651 41 phosphosilicate glass (BPSG) to the wafer of Figure 2A. Then, the same method is used to form an etch protection layer 192 such as a silicon nitride layer. Thereafter, a conventional photolithographic and etching operation is used to selectively remove portions of the etch protection layer 192 and the insulating planarization layer 190 to form storage electrode contact holes 194a, 194b extending from the top surface of the etch protection layer 192 to the surface 10. of the drain areas 16a, 16b. Then a thick poly-silicon layer is applied over the wafer. The thick polysilicon layer can be further diffused with impurities such as arsenic ions to increase conductivity. Thereafter, a conventional photolithographic and etching process is used to selectively etch away the thick polysilicon layer to reform the thick polysilicon layers into substantially T-shaped polysilicon layers 196a, 196b extending from the surface of the drain regions 16a, 16b in the vertical direction. through the storage 20 electrode contact holes 194a, 194b. Alternatively, the formation of the polysilicon layers can be performed together with the formation of the storage electrodes for the charge storage capacitor of each DRAM cell.

Figure 13B shows that in the next step, an insulation layer 198 such as a silicon dioxide layer is applied over the wafer. Thereafter, a conventional photo-lithographic and etching operation is used to determine and selectively etch portions of the insulating layer 198 to form windows 200a, 200b through the insulating layer 30 198 and exposing the top surface of the substantially T-shaped polysilicon layers 196a, 196b to lay. Thereafter, a thick polysilicon layer is applied over the wafer to a thickness of, for example, about 7,000 A. Further, the thick polysilicon layer can be diffused with impurities such as arsenic (As) ions to enhance conductivity. Then, a conventional photolithographic and etching operation is used to define and selectively etch away portions of the thick polysilicon layer to form polysilicon columns 202a, 202b extending from the top surface of the substantially T-shaped polysilicon layers 196a, 196b up through windows 200a. 200b 10 above the top of the wafer. The polysilicon columns 202a, 202b serve as the top of the stem-shaped conduction layers for the charge storage capacitor of the DRAM cell.

To complete the manufacture of the DRAM-15 chip, the wafer of Figure 13B can be further processed in steps as described above with respect to the first through the eighth and eleventh embodiments.

It will be apparent to those skilled in the semiconductor manufacturing art that the previously disclosed embodiments can be used either alone or in combination to provide storage electrodes of various sizes and shapes on a single DRAM chip. These variations are all within the scope of the invention.

Although in the accompanying drawings the embodiments of the drains of the transfer transistors are based on diffusion regions in a silicon substrate, other variations, for example trench type drain regions, are possible.

Elements in the attached drawings are schematic diagrams for demonstration purposes and do not represent the actual scale. Under no circumstances should the dimensions of the 1005631 43 elements of the invention shown be construed as limiting the scope of the invention.

Although the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as will be apparent to those skilled in the art. The scope of the appended claims defining the invention should therefore be accorded the broadest interpretation to cover all such modifications and corresponding structures.

15 1005631

Claims (26)

A semiconductor memory device comprising: (a) a substrate, (b) a transfer transistor formed on said substrate, which transfer transistor includes 5 source / drain regions and (c) a tree capacitor electrically connected to one of said source drain / drain regions, the tree-shaped capacitor comprising: (i) at least one trunk conductor layer having a top and a bottom and electrically coupled to one of said source / drain regions, which at least trunk conductive layer extending substantially upwardly from said underside, (ii) at least one upper branch-shaped conductive layer electrically connected to said top of said trunk-shaped conductive layer, said at least upper branch-shaped conductive layer provided with a bottom surface, and (Iii) at least one hanging branch-like guiding layer which is connected at one end to the bottom surface of said at least present top branch-like conductive layer, said at least present trunk-like conductive layer, said at least present top branch-like conductive layer and said at least present hanging branch-like conductive layer in combination form a storage electrode for said tree-shaped capacitor, ( iv) a dielectric layer formed over exposed surfaces of the at least one present 1005631 stem-shaped guiding layer, the at least present upper branch-shaped guiding layer and the at least one hanging branch-shaped guiding layer and (v) a covering conducting layer covering said dielectric layer covering conductive layer serves as an opposing electrode of said tree-shaped capacitor, said at least present hanging branch-shaped conductive layer comprising: a first pair of hanging branch-shaped conductive layers with substantially an L-shape In a cross-sectional view, said first pair of substantially L-shaped hanging branch-like conductive layers each end-connected to the bottom surface of the at least one upper branch-shaped conductive layer present, and further comprising said tree-shaped capacitor: a second pair of substantially L-shaped hanging branch-shaped guide layers arranged substantially parallel to said first pair of substantially L-shaped hanging branch-shaped guide layers, each of said second pair of substantially L-shaped hanging branch-shaped guide layers having one end connected to it. said bottom surface of said at least present upper branch-like guiding layer. 2. A semiconductor memory device according to claim 1, characterized in that the second pair of substantially L-shaped hanging branch-shaped guide layers is arranged below said first pair of substantially L-shaped hanging branch-shaped guide layers. Semiconductor memory device according to claim 1, characterized in that said first pair of hanging branch-shaped guide layers substantially L-shaped in 1005b3i is disposed substantially symmetrically with respect to said at least present stem-shaped guide layers. 4. A semiconductor memory device according to claim 1, characterized in that said top branch polysilicon layer has a substantially middle portion connected to said top of said at least present stem polysilicon layer and is disposed substantially at right angles with respect to said at least stem-shaped guiding layer present. Semiconductor memory device according to claim 4, characterized in that the at least present hanging branch-shaped guide layer has a first segment as well as a second segment, wherein said first segment 15 is substantially upright and is connected to said bottom surface of said at least present upper branch-shaped guiding layer and said second segment extends horizontally from one end of said first segment. A semiconductor memory device according to claim 1, characterized in that said at least present hanging branch-shaped guide layer has a surface which is in contact with said at least present stem-shaped guide layer. Semiconductor memory device according to claim 1, characterized in that the at least present stem-shaped conductive layer comprises a substantially T-shaped segment at the top. 8. Semiconductor memory device comprising: 30 (a) a substrate, 10 0 5 6 3 1 (b) a transfer transistor formed on said substrate, which transfer transistor includes source / drain regions and (c) a tree capacitor which is electric 5 connected to one of said source / drain regions, the tree-shaped capacitor comprising: (i) at least one trunk conductive layer having a top and a bottom electrically coupled to said one source / drain region at least one stem-shaped guide layer extending substantially upwardly from said bottom, (ii) at least one upper branch-shaped guide layer having a bottom surface and electrically connected to said top of the at least one stem-shaped guide layer and (iii) at least one hanging branch-shaped guiding layer with a first segment and a second segment, the second segment being connected to and at an angle to o view of said first segment, said first segment being connected at one end to the bottom surface of said at least present upper branch-like guide layer, said at least present stem-shaped guide layer, said at least present upper branch-like guide layer and said at least one hanging branch-shaped guide layer in combination forms a storage electrode for said tree-shaped capacitor, (iv) a dielectric layer formed over exposed surfaces of said at least present stem-shaped guide layer, said at least present upper branch-shaped guide layer and said present lower branch-shaped conductive layer and 1005631 (v) a covering conductive layer covering said dielectric layer, said covering conductive layer serving as opposite electrode of said tree-shaped capacitor, said at least one present suspended branch-shaped guiding layer comprises: a first pair of hanging branch-shaped guiding layers with substantially an L-shaped cross-section, which first pair of substantially L-shaped hanging branch-shaped guiding layers are each connected at one end to said bottom surface of said ten least upper branch-shaped guiding layer present and that said at least present hanging branch-shaped guiding layer further comprises: a second pair of substantially L-shaped hanging branch-shaped guiding layers which are arranged substantially parallel to said first pair of substantially L-shaped hanging branch-shaped guiding layers, wherein each of said second pair of substantially L-shaped hanging branch-like guide layers is end-connected to said bottom surface of said at least present upper branch-like guide layer. 9. A semiconductor memory device according to claim 8, characterized in that said second pair of substantially L-shaped hanging branch-shaped guide layers is arranged below the first pair of substantially L-shaped hanging branch-shaped guide layers. 10. A semiconductor memory device according to claim 8, characterized in that said first pair of substantially L-shaped hanging branch-shaped guide layers are arranged substantially symmetrically with respect to said at least stem-shaped guide layers present. 1005651 11. A semiconductor memory device according to claim 8, characterized in that said upper branch-shaped polysilicon layer has a substantially middle region which is connected to said top of said at least present stem-shaped polysilicon layer and is disposed substantially at right angles to of the at least stem-shaped guiding layer present. A semiconductor memory device according to claim 11, characterized in that said first segment 10 of said at least present hanging branch-like guide layer is substantially upright and is connected to said bottom surface of said at least present upper branch-like guide layer and said second segment extends horizontally from a first end of said first segment. 13. A semiconductor memory device according to claim 12, characterized in that said at least present hanging branch-shaped conduction layer further comprises a third segment connected to said second segment and a fourth segment connected to said segment. 14. A semiconductor memory device according to claim 8, characterized in that said at least present hanging branch-shaped guiding layer has a surface which is in contact with said at least present trunk-shaped guiding layer. 15. A semiconductor memory device according to claim 14, characterized in that said at least present stem-shaped conductive layer further comprises a substantially horizontal segment at the top. 16. Semiconductor memory device comprising: (a) a substrate, 1005631 (b) a transfer transistor formed on said substrate, which transfer transistor includes source / drain regions and (c) a tree capacitor electrically connected to one of said source / drain regions, wherein the tree-shaped capacitor comprises: (i) at least one trunk conductive layer having a top and a bottom electrically connected to said one source / drain region, which at least present stem-shaped conductive layer comprises at least one columnar portion extending substantially upwardly from said bottom, (ii) at least one upper branch-like conductive layer electrically connected to said top of said at least present stem-shaped conductive layer, and (iii ) at least one hanging branch-like guide layer comprising a number of serially connected segments which is one end connected to the bottom surface of said at least present upper branch-shaped guide layer, said at least present stem-shaped guide layer, said at least present upper branch-shaped guide layer and said present hanging branch-shaped guide layer in combination form a storage electrode for said tree-shaped capacitor, (iv) a dielectric layer formed over exposed surfaces of the at least present stem-shaped conductive layer, the at least present upper branch-shaped conductive layer and the at least present lower branch-shaped conductive layer, and 1005631 (v) a covering conductive layer which covering said dielectric layer, said covering conductive layer serving as an opposite electrode of said tree-shaped capacitor, characterized in that the at least present hanging branch-shaped conductive layer comprises a number of pairs of hanging branch-shaped conductive layers at, wherein each pair is arranged substantially symmetrically with respect to said at least present stem-shaped guide layer and each hanging branch-shaped guide layer is connected at one end to said bottom surface of said at least present upper branch-shaped guide layer. 17. Semiconductor memory device according to claim 16, characterized in that the at least present hanging branch-shaped conduction layer comprises four segments. A semiconductor memory device comprising: (a) a substrate, (b) a transfer transistor formed on said substrate, which transfer transistor includes 20 source / drain regions, and (c) a tree capacitor electrically connected to one of said source / drain regions, characterized in that the tree-shaped capacitor comprises: (i) at least one stem-shaped conductive layer having a top and a bottom electrically coupled to said one said source / drain region, which at least one stem-shaped guiding layer present at least one column-shaped part which extends substantially upwardly from said bottom end, (ii) at least one hanging branch-shaped guiding layer with at least a first segment, a two-part 5; the segment and a third segment which second segment is connected to and at an angle to said first segment, which said third segment is connected to and at an angle to said second segment and which first segment to a end is connected to a side surface of said at least present stem-shaped conductive layer and said at least present stem-shaped conductive layer and said at least hanging branch-shaped conductive layer in combination form a storage electrode for said tree-shaped capacitor, (iii) a dielectric layer formed over exposed surfaces of said at least present stem-shaped conductive layer and said at least 15 suspended branch-shaped conductive layer and (v) a covering conductive layer covering said dielectric layer, said covering conductive layer serving as an opposite electrode of said tree-shaped capacitor. Semiconductor memory device according to claim 18, characterized in that said columnar part of said at least present stem-shaped conductive layer has a hollow interior. 20. A semiconductor memory device according to claim 19, characterized in that said at least present stem-shaped conduction layer is substantially U-shaped in cross section. 21. A semiconductor memory device according to claim 18, characterized in that the at least stem-shaped conduction layer comprises: * 1001 a bottom segment with a top and electrically connected to said copy of said source / drain regions and a top segment having a substantially T-5 shaped cross section and connected to the top of said bottom segment. 22. A semiconductor memory device according to claim 21, characterized in that the at least one hanging branch-shaped guiding layer present is connected to said upper segment of said present trunk-shaped guiding layer. 23. A semiconductor memory device according to claim 18, characterized in that said at least present stem-shaped conductive layer comprises: a lower segment with a top and electrically connected to said copy of said source / drain regions and an upper segment which is substantially T-shaped in cross-section and includes a hollowed-out interior, the top segment of which is connected to said top of said bottom segment. 24. A semiconductor memory device according to claim 18, characterized in that said at least present hanging branch-shaped guide layer is connected to said top of said at least present stem-shaped guide layer. 25. A semiconductor memory device according to claim 18, characterized in that the at least present stem-shaped conductive layer is substantially T-shaped in cross section. 26. A semiconductor memory device according to claim 23, characterized in that said first segment 10 0 5 of said hanging branch-shaped guiding layer is connected to a surface of said at least present trunk-shaped conducting layer, said second segment extending upwards and connected to said first segment and wherein said third segment is horizontally connected to said second segment. 1005631