JPS6123360A - Semiconductor memory and manufacture of the same - Google Patents

Abstract

PURPOSE:To realize high packing density of memory cell by arranging in series in the depth direction a transistor and a capacitor at the side surface of groove formed on the main surface of a semiconductor substrate. CONSTITUTION:Not only a capacitor 14 but also a transistor forming a single memory cell are formed vertically within the groove in series in the depth direction. Thereby, the gate length of transfer gate 13 can be set in the sufficient length in order to suppress a sub-threshold lead current without giving influence on the memory cell area, while the channel length can also be set in the sufficient length without preventing high packing density of memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device comprising a single transistor and a single capacitor, a so-called one-transistor type dynamic memory cell, and a method for manufacturing the same.

[Prior art]

Conventionally, a trench-embedded capacitor has been proposed as a capacitor for this type of memory cell. 6th
The figure is a cross-sectional view showing an example of the configuration of a memory cell using such a capacitor, and the contact hole 2A1 of the bit line 2, the transfer gate 3, and the groove capacitor 4 are formed on the surface of the silicon substrate 10 by alignment in one lithography process. They are arranged side-by-side on a plane with allowances in mind.

5 is an element isolation region, 6 is a conductor layer forming one electrode of the capacitor, 7 is a channel cut region, 8 is an insulating film, 9A and 9B are high impurity concentration regions forming the source and drain, 9B is a semiconductor region containing an impurity of a conductivity type opposite to that of the substrate 1, which constitutes the counter electrode of the capacitor.

In the above configuration, in order to reduce the memory cell area, the planar area of the bit line contact hole 2A1, transfer gate 3, and groove capacitor 4 is reduced, the above-mentioned alignment margin is reduced, and the element isolation region 5
It will not appear unless the 0 width is also reduced.

However, if the dimensions of the transfer gate 3 are reduced in the five-table configuration shown in the figure, there is a problem in that the subthreshold leakage current increases. Further, when reducing the planar area of the trench capacitor 4, there is a problem that a very deep trench must be formed in order to secure the capacitance necessary for memory operation. Furthermore, the element isolation region 6
If the zero width is reduced and the spacing between the groove capacitors is narrowed, there is a problem that bunch-through current tends to flow between the groove capacitors, causing inter-cell interference, and as a result, it is difficult to reduce the memory cell area to about 10 μd or less. Met.

[Object and structure of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can reduce the memory cell area and be highly integrated, and a method for manufacturing the same.

The semiconductor memory device of the present invention that achieves such an object has a structure in which a side surface of a groove formed on the main surface of a semiconductor substrate is
Transistors and capacitors are arranged in series in the direction in which the groove is searched.

Further, in the manufacturing method of the present invention, after forming a first groove in a substrate and forming a transistor so that the groove is not completely buried in the side surface thereof, the remaining bottom of the first groove is used as an opening. Either a second trench is formed and a capacitor is formed on the side surface of the second trench, or a mask material is formed on the side surface of the first trench so that the trench is not completely buried. A second trench having an opening at the bottom of the first trench is formed, a capacitor is formed on the side surface of the second trench, and a transistor is then formed on the side surface of the first trench from which the mask material is removed. In either method, the transistor and capacitor are formed in a self-aligned manner. Hereinafter, the present invention will be explained in detail using Examples.

〔Example〕

FIG. 1 is a cross-sectional view showing one embodiment of the present invention, in which 11 is a p-type silicon substrate, 12 is a bit line made of aluminum, 12A is a bit line contact hole, and 13 is a polysilicon film which also serves as a word line. 14 is a trench capacitor, 15 is an inter-element isolation region, 1
6 is a cell plate made of polysilicon constituting one electrode of the capacitor, 17 is a channel cut region, and p+ regions 18A, 111B, and 18C are insulating films heavily doped with impurities of the same conductivity type as the substrate 11. , 19A
.

19B is the n+ region 1 that constitutes the source and drain region.
9C is in the n region.

As is clear from the figure, in this embodiment, not only the capacitors constituting one memory cell but also the transistors are formed vertically in the trench in series with the capacitor in the direction in which the trench is searched. The gate length often affects the memory cell area, and the channel length
The length can be made sufficient to suppress subthreshold leakage current without hindering the increase in the density of memory cells. In addition, a first
A transfer gate 18 is formed on the side surface of the trench via a gate insulating film 18A without completely filling the trench, and a capacitor 14 is provided in a second trench having an opening at the bottom of the remaining GL trench. As described later, both can be formed in a self-aligned manner without a single lithography process.
An alignment margin is only required between the edge of the first trench forming the transfer gate 13 and the bit line contact hole 12. Further, a transfer gate 1a and groove capacitor 14 is arranged in a ring shape around the bit line contact hole 12A, and a channel cut p region 1 is provided between the cell plate 16 and the substrate 11.
7 and an isolation insulating film 18C made of a thick oxide film (this is not necessarily required), interference between cells is suppressed as much as possible.

Note that in this embodiment, the substrate 1 constituting the groove capacitor 14
A semiconductor region 1@C containing impurities of opposite polarity to the substrate 11 is provided on the surface of the cell plate 11, but this is because when the cell plate potential is below the power supply voltage (power supply voltage - 2 + threshold voltage) This is also for the purpose of accumulating sufficient charge in the groove capacitor, and is not necessarily necessary if the cell plate potential is sufficiently larger than the power supply voltage.
The source/drain n region 19 for the transfer gate 13 has sufficient contact with the bit line 12, so it is thought that the insulating film thickness of the %n region 111B is large at the first trench edge and the electric field is weakened. Therefore, the +n region 1@B at the connection portion with the trench capacitor 14 is not necessarily necessary in order to eliminate that influence. In addition, the n+ region 1@A only needs to be made slightly larger than the bit line contact hole 12A, and if the circuit is designed to allow an increase in resistance at the junction, a Schottky junction may be sufficient to connect it to the bit line. stomach.

FIG. 2 is a plan pattern diagram for four memory cells of this embodiment. Each memory cell is connected to a bit line Bl.

It is formed in each intersection area between B2, etc. and the word lines Wl, W2, etc., for example, the minimum processing size is 0.3 μm, and the total margin is 0.3.
When using a design rule on the order of μm, it is possible to reduce the memory area to 3 to 4 voices, which is 1/2 to 1/3 of the area of a conventional planar memory cell, without reducing the capacitor capacity. However, a significant increase in density can be achieved.

Next, an example of a method for manufacturing such a semiconductor memory device will be described with reference to FIG.

First, a first thermal oxide film 20 is deposited on a silicon substrate 11 for a thickness of 30 minutes.
The n+ layer 21 is formed to a thickness of 0 to 500 Å on the surface of the silicon substrate 11 by ion implantation. Next, a silicon nitride film 2 is deposited on the first thermal oxide film 20 by a known deposition method.
2 to 1000-2000λ2 silicon oxide film 23 to 30
A multilayer film is formed by sequentially depositing the resist to a thickness of 00 to 4000 A. After coating the entire surface with resist, a grid-like resist pattern 26 having a width of about 1 μm is formed in one lithography step (see Fig. 3(a). )).

Using this resist pattern 26 as an etching mask, the multilayer film is removed by reactive ion etching (RIE) to expose the surface of the silicon substrate 110 (see FIG. 3).

After removing the resist pattern 26, the silicon substrate 1 is etched by reactive ion etching using the multilayer film as a mask.
A first trench A for forming a vertical transistor is formed by etching the surface by about 1 μm (FIG. 3(C)).

After cleaning the inner surface of the groove with a fluoro-nitric acid solution to remove contamination damage caused by etching, the inner surface of the groove is subjected to thermal oxidation to remove the upper oxide film 23, which is a part of the multilayer film. 200-300A, which is the gate insulating film of a vertical transistor
After forming a thick thermal oxide film 27, an n region 28 which will become a source/drain region is formed at the bottom of the groove by ion implantation, but as mentioned above, this n region 28 is not necessarily necessary. Figure 3(d)).

Next, polycrystalline silicon 2e, which will become the gate electrode of the vertical transistor, is deposited at a thickness of about 2500 to 3000A using a known technique so that the inside of the groove is not completely buried, and then the surface of polycrystalline silicon 2s is completely covered. After forming an oxide film 30 by thermal oxidation to a thickness of about 300 to 500 Å, a silicon oxide film 33 is deposited to a thickness of 1000 to 2000 Å, and a silicon oxide film 51 is deposited to a thickness of 3000 to 4000 Å (see Fig. 3(e)). )).

The silicon oxide film 51, silicon nitride film 33, and silicon oxide film 30 on the flat surface are removed by reactive ion etching to expose the surface of the polycrystalline silicon 290 (FIG. 3(f)).

Next, after removing the silicon oxide film 51 on the inner surface of the groove, thermal oxidation is performed to selectively form an oxide film 41 only on the exposed surface of the polycrystalline silicon 29 (FIG. 3(g)).

An opening is formed between the polycrystalline silicon 29 constituting the gate electrode inside the trench, and reactive ion etching is performed to form a silicon nitride film 33. The silicon oxide film 30, the polycrystalline silicon 28, the silicon oxide film 21, and one area of the silicon substrate are etched to form a capacitor portion #4B having a thickness of about 2 μm (FIG. 3(h)).

After cleaning the inner surface of the groove, phosphorus-added silicon oxide film 3
6 is embedded in the trench, and an n region 3) is formed on the silicon substrate 11 of the trench capacitor portion by thermal oxidation (see FIG. 3 (1)).
)).

After removing the phosphorus-doped silicon oxide film 36 inside the groove capacitor section, the thermal oxide film 38 of the capacitor is again coated with 50 to 10
It is formed to a thickness of 0A, and a p+ region 34 is formed on the flat surface of the bottom of the multi-groove capacitor portion by ion implantation. Subsequently, the polycrystalline silicon 40 that will become the cell plate is heated by a known method.
Adhere to ooo~4000A thickness (Figure 3 (j))
.

The polycrystalline silicon 40 on the upper flat surface of the multi-groove is removed by reactive ion etching (FIG. 3(g)).

The polycrystalline silicon oxide film 41 above the trench is removed using a hydrofluoric acid-based etching solution, and the polycrystalline silicon 28 for the gate electrode is removed.
0 surface (Figure 3 CI)).

The polycrystalline silicon 42 which becomes the word line is 3000 to 400
0A, and further silicon nitride film s8 at 500-1000A
(Fig. 3, tnl).

Resist 4 subjected to rubberization using a single lithography process
6 as an etching mask, the silicon nitride film 39 on the upper part of the trench bottom is removed (FIG. 3(,l)').

Next, thermal oxidation is performed in a mixture of hydrogen and oxygen to selectively oxidize the polycrystalline silicon 42 above the trench bottom to form a silicon oxide film 47 (FIG. 3(0)).

After removing the silicon nitride 11iK33 on the surface of the polycrystalline silicon 42, a thermal oxide film 43 is formed on this surface, and then patterning is performed on a resist (not shown) to form contacts with bit lines and word lines by lithography. This resist is then used as a mask to perform dry etching. Thereafter, thermal oxidation is performed again to form an oxide film 44 on the inner surface of the bit line contact portion, and silicon nitride film 22 and silicon oxide film 20 below the bit line contact are removed by reactive ion etching (FIG. 3@).

Aluminum 46 for bit lines is deposited, and bit lines in a predetermined pattern are formed through lithography and etching (FIG. 3(b)).

In the embodiments described above, a simple p-type silicon substrate 11 was used as the substrate, but a substrate in which a p layer is epitaxially grown on a p region may also be used.

The final process diagram is shown in Figure 4, but in this case, Figure 3 (
In trench cutting for forming a vertical transistor corresponding to step C), the first trench A is formed only in the p layer 102 on the p region 101, and a vertical transistor is manufactured in the same manner as described above. Then, in the groove etching for the groove capacitor corresponding to (in FIG. 3), a second groove B is formed so as to reach the p+ region 101. By doing so, the step of ion implantation for forming the p region 34 into the lower part of the groove capacitor shown in FIG. 3(j) becomes unnecessary. Furthermore, by using a shrimp substrate with a high concentration of p+, the separation between the capacitors is complete, and interference-free between cells can be realized.

In the embodiments described above, the electrode for the capacitor was formed after the gate electrode of the MOSFET was formed, but this order can also be reversed. Next, this will be explained in detail using FIG.

First, in the same way as described above, a first
After forming the thermal oxide film 20 of do. Next, a lattice-like resist pattern 2 with a width of about 1 μm is formed by one lithography process.
6 (Fig. 5(a)).

Using this resist pattern 2B as an etching mask, the multilayer film is removed by reactive ion etching to expose the surface of the silicon substrate 11 (see FIG. 5).

After removing the resist pattern 26, the silicon substrate 11 is etched again by reactive ion etching using the multilayer film as a mask.
A first groove A for forming a vertical transistor is formed by etching to a depth of about 1 μm (FIG. 5(C)).

After cleaning the inner surface of the trench in the same manner as described above, the upper silicon oxide film 25 and silicon nitride film 24, which are part of the multilayer film, are removed.
remove. Next, a thermal oxide film 27 is formed on the inner surface of the trench by thermal oxidation in the same manner as described above, and then an n-type intermediate layer 28 is formed at the bottom of the trench by ion implantation (FIG. 5(d)).

Next, a silicon oxide film 51 is deposited in the same manner as described above (
Figure 5(e)).

Only the oxide film 51 on the flat surface at the top and bottom of the trench is removed by reactive ion etching. In other words, there is an oxide film only on the groove sides! 1 is left (Figure 5(f))
. The opening between the oxidized JJHI at the bottom of the groove is etched by about 2 pm by reactive ion etching to form a second groove B which will become a capacitor part (FIG. 5(g)).

After cleaning the inner surface of the second groove, it is thermally oxidized to a
After forming the thermal oxide film 32 with a thickness of about ooX, a nitride film 33 with a thickness of 1000 to xaooX is deposited (FIG. 5(h)).

The silicon nitride film 33 on the top and bottom flat surfaces of the trench is removed by reactive ion etching, and a p+ region 34 is formed on the bottom flat surface of the multi-trench capacitor by ion implantation.

Next, thermal oxidation is performed in a mixture of hydrogen and oxygen to selectively form an isolation oxide film 35 only at the bottom of the groove (Fig. 5(i)).
).

After removing the nitride film 33 on the inner surface of the trench, a silicon oxide film 3B doped with phosphorus is buried inside the trench, and an n region 37 is formed on the silicon substrate on the side surface of the trench in the trench capacitor portion by thermal diffusion. Figure (j)).

After removing the phosphorus-doped silicon oxide film 36 inside the groove capacitor portion and the thermal oxide film 32 on the groove surface, a thermal oxide film 38 for the capacitor is formed again in a thickness of 50 to 100 mm, and polycrystalline silicon 4O is formed to form a cell plate. By the method of 3000
The polycrystalline silicon 40 on the upper flat surface of the multi-groove is removed by reactive ion etching (FIG. 5(k)).

Next, the oxide film 51.27 deposited on the side surfaces of the first trench and the oxide film 23 deposited on the top flat surface of the trench are removed by etching, and then the inner surface of the first trench and the cell plate are removed by thermal oxidation. A thermal oxide film 52, which will become a transfer gate insulating film, is formed on the surface of the polycrystalline silicon 40 (see FIG. 5 (1)).
)).

Polycrystalline silicon 42 for transfer gates and word lines is deposited by a known method to completely fill the first groove, and a thermal oxide film 43 is further formed on the surface (
)).

A resist (not shown) is patterned as bit line contacts and word lines by one lithography step, and processed by dry etching. Thereafter, thermal oxidation is performed again to form an oxide film 44 on the inner surface of the bit line contact portion, and the nitride film 22 and oxide film 20 below the bit line contact are removed by reactive ion etching (FIG. 5(n)).

Aluminum 45 for bit lines is deposited, and bit lines are formed through lithography and etching steps (fifth step).
Figure (0)).

In this method, the oxide film 51 is used as a dedicated etching mask to form the second groove.
There is an advantage that processing in these steps can be performed more reliably. It goes without saying that this method can also be applied to a shrimp substrate similar to that shown in FIG.

Note that each of the manufacturing methods described above is an example of the present invention, and the present invention is not limited thereto. For example, as mentioned above, ion implantation after forming the first groove for forming the transfer gate is not necessarily necessary, and ion implantation for forming the n+ layer 21 on the upper part of the groove also applies to the word line polycrystal. There is no problem even if the contact hole is used after processing the silicon 42. Further, the formation of the isolation oxide film 35 at the bottom of the trench capacitor and the formation of the n-region 37 of the trench capacitor may be performed in any order;
It is not necessarily necessary to provide this, and FIGS. 4 and 5 are examples in which this is omitted.

Further, in order to form the n region 37, a phosphorus-doped oxide film 36 is
However, the thin n layer may also be formed by, for example, a vapor phase diffusion method.

Furthermore, polycrystalline silicon is used for the transfer gate because it can be formed by CVD or the like and its surface can be oxidized, but it is not necessarily limited to this. For example, silicides such as molybdenum, tungsten, titanium, etc. may also be used.

Similarly, the bit line is not limited to aluminum, and these silicides and the like can also be used.

Further, although p-type silicon is used as the substrate, it goes without saying that if a substrate of opposite polarity is used, the polarity of each region will be reversed accordingly. For example, phosphorus diffusion n region 3T
Instead, a lap region is formed by, for example, boron diffusion.

〔Effect of the invention〕

As explained above, according to the semiconductor memory device of the present invention, the planar dimensions can be reduced by arranging the transistors and capacitors in series along the search direction on the side surfaces of the grooves formed on the main surface of the semiconductor substrate. It is possible to increase the capacitance of the capacitor without enlarging the capacitor and to increase the length of the transfer gate channel in order to reduce subthreshold leakage. In particular, according to the manufacturing method of the present invention, the transistor and the capacitor can be formed in a self-aligned manner, and the alignment margin between them can be increased. etc., making it possible to increase the density of memory cells.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a plane pattern diagram, and FIGS. 3, 4, and 5 are steps showing an example of the manufacturing method according to the present invention. Cross-sectional view FIG. 6 is a cross-sectional view showing an example of the configuration of a conventional semiconductor memory device. 11...P type silicon substrate, 12...Bit line, 12A...Bit line contact hole, 13...Transfer gate, 14-...Slotted capacitor, 16...轡Element isolation region, 18...Mochi cell plate, 17...#P+ region (channel cut region)
, 111A, 18B, 180@@@*insulating film, 1s person,
1sB... n+ region (source-drain region), I
8C...n region, 2!1.42--polycrystalline silicon constituting transfer gate and word line,
40- Polycrystalline silicon constituting the fist cell plate,
51・-ee Silicon acid (1[,1
01” IP+ area, 102 @ 畢e * p layer, A・
-・First groove of the fist, B 11 War・Second groove.

Claims (6)

[Claims] (1) In a semiconductor memory device consisting of a single transistor and a single capacitor, the transistor and the capacitor are arranged in series on the side surface of a groove formed on the main surface of a semiconductor substrate in the direction in which the groove is searched. A semiconductor memory device characterized by: (2) The semiconductor substrate includes a semiconductor region having a high impurity concentration and a semiconductor layer of the same conductivity type formed on the main surface thereof, and the groove has a first trench formed on the main surface of the semiconductor layer and a first trench formed on the main surface of the semiconductor layer. A second trench has an opening at the bottom of the first trench and a bottom reaches the semiconductor region, and a transistor is formed on the side surface of the first trench, and a capacitor is formed on the side surface of the second trench. A semiconductor memory device according to claim 1, characterized in that the semiconductor memory device is formed. (3) forming a first groove in the main surface of the semiconductor substrate; forming a highly impurity-concentrated semiconductor region in the semiconductor substrate at least near the opening of the first groove;
A step of forming a transistor by forming a conductor layer on the side surface of the trench with an insulating film interposed therebetween so that the trench is not completely buried; and a second step having an opening at the bottom of the first trench.
1. A method of manufacturing a semiconductor memory device, comprising: forming a groove; and forming a capacitor by forming a conductor layer on the side surface of the second groove via an insulating film. (4) Using a substrate including a semiconductor region having a high impurity concentration and a semiconductor layer of the same conductivity type formed on the main surface thereof as a semiconductor substrate, forming a first groove on the main surface of the semiconductor layer, and 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein the second trench is formed so that its bottom reaches the semiconductor region. (5) forming a first groove on the main surface of the semiconductor substrate; forming a masking material layer on the side surface of the first groove so that the groove is not completely buried; A step of forming a second groove having an opening at the bottom, a step of forming a capacitor by forming a conductor layer on the side surface of this second groove via an insulating film, and after removing the mask material layer. 1st
forming a highly impurity-concentrated semiconductor region in the semiconductor substrate at least near the opening of the first trench, and forming a conductor layer on the side surface of the first trench via an insulating film to form a transistor. A method for manufacturing a semiconductor memory device, characterized by: (6) Using a substrate including a semiconductor region having a high impurity concentration and a semiconductor layer of the same conductivity type formed on the main surface thereof as a semiconductor substrate, forming a first groove on the main surface of the semiconductor layer, and 6. The method of manufacturing a semiconductor memory device according to claim 5, wherein the second trench is formed so that its bottom reaches the semiconductor region.