KR900005355B1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The device includes a first conduction type well (62) formed on the first conduction type of substrate; a second conduction type IGFET having source and drain areas separated from each other on the surface well; a bit line connected to the source area; a first word line connected to the drain area; a first trench formed on the neighbourhood of the drain area of the substrate; a second trench formed deeper than the well depth; a first plate electrode having the same conduction type as the substrate; a storage node (78) formed on the inside of the trench wall and isolated from the first plate electode; a second plate electrode formed in the trench and on the connection area; and a second word line.

Description

Semiconductor memory device and manufacturing method

1 is a cross-sectional view of one embodiment of a DRAM cell having a conventional trench capacitor.

2 is a cross-sectional view of another embodiment of a DRAM cell having a conventional trench capacitor.

3 is a plan view of the DRAM cell according to the present invention.

4A-4 (i) are cross-sectional views of a manufacturing process of a DRAM cell according to the present invention.

5 is a cross-sectional view taken along the line a-a 'of FIG.

6 is a cross-sectional view taken along line b-b 'of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM), and more particularly, to an apparatus for a large capacity DRAM cell and a method of manufacturing the same.

In the semiconductor memory technology, efforts have been made to increase the number of memory cells on one chip in order to increase memory capacity. In order to achieve this purpose, it is important to minimize the area of a memory cell array in which a large number of memory cells are formed on the surface of a limited chip, and that a memory cell composed of one transistor and one capacitor is preferable in terms of the minimum area. It is a known fact. However, since the portion occupying most of the area of the memory cell of one transistor and one capacitor is the area occupied by the capacitor, while minimizing the area occupied by the capacitor, the capacity of the capacitor is increased to facilitate information detection and soft error caused by alpha particles. Reducing the problem is an important issue.

To solve the problem, various methods of forming a trench structure capacitor on the surface of a semiconductor substrate have been proposed to minimize the surface area occupied by the capacitor and maximize the capacity of the storage capacitor. It is true that you can not write.

One example of a conventional memory cell having a trench capacitor is a memory cell having a planar capacitor as shown in FIG. 1 having a recess in the trench.

1 is a cross-sectional view of a DRAM cell in which polycrystalline silicon inside a trench is plated with one electrode of a capacitor, and is formed on a P-type well 2 formed on a P-type semiconductor substrate 1 as shown, and having one electrode of a capacitor. And a cell plate of polycrystalline silicon (7) separated by the insulating film (4) which becomes the dielectric material of the well (2) and the capacitor, and formed on the well (2) below the insulating film (4) and becomes the other electrode of the capacitor. An N-type semiconductor region 5, a source region 10a of a transistor connected to the N-type semiconductor region, a drain region 10b of a transistor connected to a bit line described later, a polycrystalline gate that is a gate of a transistor and passes through a capacitor A polycrystalline silicon bit line 12 connected to the silicon word line 9 and the drain 10b of the transistor and separated into the word line 9 and the internal insulating layer 11, the bit line 12 and the insulating layer. Minutes into 13 And it consists of a metal line (Backing Metal) which is connected with the lower polysilicon word line (9) at a predetermined portion.

In the memory cell having the structure shown in FIG. 1, the planar area occupied by the capacitor can be greatly reduced. However, in order to prevent leakage current due to the punch-through phenomenon between the trench capacitors, as shown in FIG. Isolation) area 3 should be sufficiently secured.

On the other hand, the concentration of the well 2 may be increased to reduce the punch draw between trench capacitors, but the increase in the well concentration may be due to the characteristics of the transistor and the junction of the N-type semiconductor region 5 and the well 2 on the trench side. The concentration of the well is limited because it causes problems such as the reduction of the junction breakdown voltage, and the junction depth of the N-type semiconductor region on the side of the trench must be controlled to reduce the punch draw. Adjusting the concentration was problematic.

In addition, since the charge of the capacitor is stored along the outside of the trench, the memory cell has a high soft error rate (SER) due to alpha particles, similar to the planar capacitor.

FIG. 2 is a trench capacitor conventionally proposed to eliminate the punch draw between the trenches in the memory cell of FIG. 1 and to reduce the SER. Isolation of the trench side with an oxide film and the inside of the trench are shown in FIG. A memory cell in which capacitors are formed by forming double polycrystalline silicon layers separated from each other.

Referring to FIG. 2, a P-type well 22 formed on the P-type semiconductor substrate 21, a thick insulating layer 25 formed on the P-type well 22 and surrounding the inside of the trench, the thick An insulating layer which is separated from the well 22 by an insulating layer and becomes a dielectric material layer of the polycrystalline storage node 26 and the capacitor, which is formed over a predetermined region on the inside of the trench and the well surface. 27) a polysilicon cell plate 28 separated from the polysilicon cell plate 28, a source region 32a of a transistor formed on the well surface and connected to a bit line to be described later, and a well surface A drain region 32b of the transistor formed thereon, a gate oxide film 30 over the channel region between the source 32a and the drain 32b of the transistor, and an insulating material 29 over the cell plate 28. Split trench Polysilicon layer 31 serving as a gate and a word line of the gate, a polysilicon bit line 34 connected to the drain 32b of the transistor and separated into the word line 31 and the internal insulating layer 33, It is composed of a backing metal 36 separated from the bit line 34 and the insulating layer 35 and connected to the lower polycrystalline silicon word line 31 at a predetermined portion.

In the memory cell having the structure as shown in FIG. 2, the trench is separated into a thick insulating layer 25, and a device isolation oxide layer 23 connected to the thick insulating layer 25 is formed between each trench to form a capacitor in the trench and the inside. In this case, the soft error rate problem and the punch draw phenomenon in FIG. 1 can be reduced. However, the polysilicon storage node 26 reduces the actual area of the capacitor in the trench, so that the capacitor capacity required for operation of the DRAM cell is obtained. There is a problem in that the planar area of the trench is increased or the trench must be deeply drilled, and the topology of the device is increased due to the polycrystalline silicon cell plate 28 on the upper side, thereby making it difficult to manufacture a transistor formed after the formation of the capacitor.

Accordingly, an object of the present invention is to provide an apparatus for manufacturing a memory cell having a large capacity capacitor for a small memory cell area and at the same time having a low soft error rate for alpha particles.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

3 is a layout plan view of a memory cell array according to the present invention.

In the figure, region 40 is a trench region in which a capacitor is formed, and region 41 is a polysilicon storage node region surrounding the trench interior on the inside of the trench and on the substrate, and polycrystalline silicon sample rate in the remaining regions except region 42. The region 43 is formed of an impurity doped region of the same conductivity type as the substrate connected to the storage node region 41 and the region 50 and connected to the source region 48 of the transistor through the region 51. A region 44 is a polysilicon wordline region, region 45 is a polysilicon bitline region connected via a drain 47 and a contact 47 of the transistor, region 46 Is an aluminum line (Backing Metal) connected to the word line, and the region 52 is an element isolation oxide region that separates the trench from the trench. Substrate same as in contact with the isolating oxide film also has a field of type doped layer.

4A-4 (i) show a process diagram of a memory cell having a trench capacitor according to the present invention, showing a part of a cross section cut in the a-a 'direction in FIG.

Hereinafter, a manufacturing process of an embodiment of a memory cell having a trench capacitor according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 4A, first, a P-type well 62 is formed in a region where a memory cell is to be formed on a silicon substrate 61. Then, an oxide layer and a nitride layer of Si 3 N 4 are formed on the silicon substrate 61, and a field doping layer 63 having the same conductivity type as that of the substrate is formed in a predetermined region on the substrate to separate the memory cell and the cell. A device isolation oxide film 64 is formed on the field doping layer 63 with LOCOS (Local Oxidation of Silicon). Then, the oxide layer and the nitride layer used as the oxide mask are removed at the time of forming the device isolation oxide film, and a photoresist mask is formed by a normal photo process to form a high concentration N-type doping layer 65.

The N + doped layer 65 serves to connect the storage node of the capacitor and the source of the transistor in the memory cell of the present invention including one transistor and one capacitor.

4 (b) shows a CVD oxide film 68 formed on the substrate 61 by a 240A oxide layer 66, a 1500A nitride layer 67, and a 1000A CVD method in the process of forming a trench mask. ) In order to form the trenches (region 40 in FIG. 3). The CVD oxide film 68, the nitride film 67 and the oxide film 66 are formed by the reactive ion etching (RIE) method. Etching is performed to form trench window 69.

FIG. 4 (c) is a process of forming a first trench, and the silicon substrate is etched by a length of about 1-3 μm using a reactive ion etching method using the trench mask formed in the process of FIG. 4 (b) as an etching mask. One trench 71 is formed. In this process, the thickness of the CVD oxide film is lower than that shown in FIG. 4 (b), and the thickness of the CVD oxide film is determined by the selectivity and the trench depth of the silicon and the oxide film. Then, the thermal oxide film and the CVD oxide film are formed on the trench-formed substrate, and the formed oxide films are etched by the reactive ion etching method to form the side oxide film 72 of about 1000-2000A on the side of the first trench.

The thick side oxide film 72 suppresses depletion of a capacitor formed through a subsequent process. In FIG. 4D, the second trench 73 is formed by etching the silicon substrate using the trench mask formed in the process without a separate mask in the process of forming the second trench. At this time, the side oxide film 72 formed in the process of the fourth (c) is left as it is and as the trench deepens, the CVD oxide film 68b on the substrate becomes thin.

Then, the doping region 74 is formed by doping the trench side in which the second trench is formed, with a high concentration of N + or P + such that the surface concentration is about 10-10 / cm in the same conductivity type as the substrate. At this time, the doping method of the impurity may be ion implantation method, glass containing P + or N + may be applied to the trench to diffuse the impurities in a high-temperature furnace, and a conventional BN (Boron Nitrid) wafer may be used. Those skilled in the art will readily understand.

When doping the impurity, the dopant is doped over the entire portion of the lower end portion and the second trench on the first trench wall surface in which the side oxide film 72 is formed by the masking action of the side oxide film 72 thickly formed on the first trench wall surface 71 ′. Region 74 is formed.

In the above embodiment, the side oxide film 72 is formed of an oxide film, but may be formed by replacing it with a nitride film.

Then, in order to clean the trench surface, a method of growing and removing an oxide layer on the trench surface or etching the trench surface directly with a polysilicon etching material is used.

FIG. 4 (e) shows a process of forming a dielectric material layer of a trench capacitor. The CVD oxide film 68b, nitride film 67 and oxide film 66 used as the trench mask are removed without a mask, and an oxide film is formed on the entire surface of the substrate. As a result, the dielectric material layer 75 of the capacitor is formed and the polysilicon layer 76 is formed on the dielectric material layer 75.

At this time, the first trench wall surface where the side oxide film was formed is formed such that the thickness of the entire oxide layer is about 1000A-2000A. In addition, the dielectric material layer 75 may have a structure in which an oxide film and a nitride film are mixed in addition to the oxide film.

Then, a photoresist is formed on the entire surface of the substrate so that the inside of the trench is sufficiently coated, and then the entire surface of the substrate is exposed and developed to leave only the photoresist 77 inside the trench. Then, the polycrystalline silicon 76 and the dielectric material layer 75 on the substrate were etched to a level similar to that of the upper silicon surface as shown in FIG. 4 (f).

FIG. 4 (g) shows a process of forming the storage node of the trench capacitor. First, the photoresist 77 of FIG. 4 (f) is removed and the polycrystalline silicon 78 is deposited. Then, the polycrystalline silicon 76 and 78 is doped with an impurity of the same conductivity type as that of the N-type doping layer, and then a photoresist is applied to the polycrystalline silicon 78 which is overlapped with the silicon surface by a conventional photolithography process. A pattern is formed to complete the polysilicon storage node (hereinafter referred to as 78). The polysilicon storage node 78 is connected to the N + doped layer 65 through the region 79. Then, the photoresist used as a mask during the etching process is removed, and an oxide film 80, which is a capacitor dielectric material, is grown on the storage node polycrystalline silicon layer 78 recessed in the trench and on the upper silicon surface. The capacitor dielectric material may be the same material as the capacitor dielectric material 75 surrounding the trench instead of the oxide layer.

FIG. 4 (h) is a process of forming a cell plate of a trench capacitor. The polycrystalline silicon layer 81 is deposited on the fourth (g) diagram, doped with a predetermined impurity, and then etched again to form a polycrystal on the silicon surface. The thickness of the silicon layer 81 is about 3000A.

Then, the polysilicon layer 81 is doped with impurities and finally the polysilicon cell plate 81 is formed by a conventional etching method using a mask. An oxide film 82 is then grown on top of the polysilicon cell plate 81 to insulate the capacitor polysilicon cell plate and the polysilicon word line formed thereafter. At this time, since the capacitor plate 81 is doped polysilicon, the insulating oxide film 82 grows thicker on the surface of the polysilicon 81 than on the silicon surface.

After removing the oxide layer 82 in the region where the transistor is to be formed, a polysilicon word line 84 is formed on the gate oxide layer 83 of the transistor, and the transistor is formed using the polysilicon word line 84 as a mask. The drain region 85a and the source region 85b of the transistor are formed by doping N-type impurities in the region to be formed.

Next, an insulating layer 86 is formed on the polysilicon word line 84 to be insulated from the polysilicon bit line formed thereafter, and is connected to the drain region 85a of the transistor on the insulating layer 86. The polysilicon bit line 87 is formed.

Next, an insulating layer 88 is formed on the polysilicon bit line 87, and a metal line is formed of a metal such as aluminum on the insulating layer 88 and connected to the polysilicon word line 84 in a predetermined region. (Backing Metal) 89 is formed.

FIG. 5 is a cross-sectional view taken along line a-a 'of FIG. 3 as mentioned above as a completed cross-sectional view of the DRAM cell according to the present invention, which is formed through the process of FIGS. 4 (a) to 4 (i). 6 is a cross-sectional view taken along line b-b 'of FIG. 3, and the same reference numerals are used for the same portions as in FIG.

Referring to the drawings, the memory cell according to the present invention includes polycrystalline silicon in the trench with the first conductive semiconductor substrate 61 having the first conductive well 62 formed therebetween and the first dielectric material layer 75 interposed therebetween. A storage node 78 is formed, and a polysilicon cell plate 81 is formed over the substrate in the trench and over the trench, with the polysilicon storage node 78 and the second dielectric layer 80 interposed therebetween. An impurity semiconductor region 74 doped with an impurity of a first conductivity type, which is the same conductivity type as the substrate, is formed in the substrate and the well region in contact with the first dielectric material layer 75, and a predetermined region of the storage node 78 is formed. 79 is in contact with and is spaced apart from the impurity semiconductor region 74, the second conductive semiconductor region 65 is formed, the source region of the second conductive transistor in contact with the second conductive semiconductor region 65. 85b is formed and spaced apart from the source region. As a result, a drain region 85a of the second conductive transistor is formed, and a predetermined insulating film 83 is disposed on the separation region between the source and drain regions 85a and 85b of the transistor and on the polysilicon cell plate 81. A polysilicon word line 84 is formed, and is connected to the drain region 85a of the transistor on the word line 84 and separated into the word line 84 and the insulating film 86. A polysilicon bit line 87 is formed and an aluminum line 89 is formed on the bit line 87 by being separated by an insulating film 88.

In addition, the cell-to-cell, that is, the trench capacitor and the trench capacitor adjacent to each other, form a field doping layer 63 in the region of the lower substrate of the device isolation oxide 64 and the device isolation oxide 64 and the side oxide layer 72 is formed. The depth of the trench is sufficiently formed to separate the impurity doped region 74 formed around the field doped layer 63 and the second trench.

In addition, the polysilicon storage node 78 is a source region of the transistor through the silicon connection region 65 doped using polycrystalline silicon doped with impurities of the same conductivity type as the source of the transistor that is opposite to the well. 85b).

In addition, the present invention having the structure described above uses both the silicon substrate 61 and the polysilicon plate deposited on the trench as a cell plate. The ground plate or the same voltage as the second plate is applied to the first plate.

As described above, the present invention can maximize the effective area of a capacitor by using a trench of a constant size by forming a dielectric material by capturing the trench and the polysilicon storage node inside the trench.

In addition, the present invention selectively oxidizes the trench surface in two trench processes, thereby making the polycrystalline silicon recessed in the trench into the storage node of the capacitor, thereby eliminating the punch draw between adjacent trenches and reducing the charge destruction of the capacitor by the alpha particles. have.

Therefore, the present invention can secure the capacitance required for DRAM cell operation using a small planar area and can reduce the device isolation region between the trenches, and thus can be applied as a more highly integrated DRAM cell and a similar memory cell.

Claims (5)

A semiconductor memory device comprising: an insulated gate field effect transistor having a well of a first conductivity type on a semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type on the surface of the well, and a source and a drain; A gate electrode insulated over the semiconductor substrate between the regions, a bit line connected to the source region, a first word line connected to the gate region, a first trench formed in the semiconductor substrate adjacent to the drain region, and the first trench A second trench that is formed deeper than the depth of the well in succession, a first plate electrode region of the same conductivity type as the substrate formed on the semiconductor substrate inside the second trench wall, and a side surface which is coated on the first trench wall A storage node formed on the trench wall insulated from the first plate electrode by an oxide film and a first dielectric material applied on the first and second trench walls. And a trench separated by a second dielectric material applied on the storage node region wall and a connection region of the same conductivity type as that of the source which connects each other between the storage node region and the source region of the transistor. And a second word electrode formed on the connection area therein, and a second word line formed by separating the insulating material from the second plate electrode to provide the same voltage or different voltages to the first plate electrode and the second plate electrode. Supplying a semiconductor memory device. A method of manufacturing a semiconductor device, comprising: a device isolation oxide film for separating a memory cell and a memory cell on a surface of a first conductive type well formed on a silicon semiconductor substrate and a device isolation oxide film under a device isolation oxide film, the same conductivity type as the well A first process of forming a field doping layer of the second process, a second process of forming a doping layer of a second conductivity type opposite to the well in a region adjacent to the device isolation oxide film, and a mask for forming a trench in the entire surface of the substrate A third process of forming a pattern, a fourth process of forming a first trench by using the trench mask pattern as an etching mask, and forming a side oxide film on a wall of the first trench, and etching the trench mask pattern and the side oxide film Forming a second trench as a mask and forming an impurity doping layer of the same conductivity type as the substrate along the second trench wall; and the trench mask A sixth step of forming a dielectric material layer on the trench wall surface and the entire upper surface of the substrate to remove the pattern and forming the dielectric material of the capacitor on the trench wall surface; and a seventh process of forming a polycrystalline silicon layer in the trench on the dielectric material layer; An eight-step of forming a polycrystalline silicon layer on the polycrystalline silicon layer and the doped layer of the second conductive type on a substrate and doping the polycrystalline silicon layer to a second conductive type; and polycrystalline silicon of the second conductive type A ninth step of forming a dielectric material of a capacitor on the layer, a tenth step of forming a doped polycrystalline silicon layer on the dielectric material layer and forming a pattern of a cell plate, and oxidizing the polycrystalline silicon cell plate In step 11, the oxide film or the dielectric material layer is removed in an area except the upper part of the polycrystalline silicon cell plate, and the gate oxide film of the transistor is formed. A twelfth step of forming a polycrystalline silicon word line on the oxide film layer, and a thirteenth step of forming a source and a drain region of a transistor opposite to a well in a predetermined region except the cell plate; And a fourteenth step of forming an insulating film on the word line and forming a connection window in the drain region of the transistor, and a fifteenth step of forming a polysilicon bit line on the insulating film. A method of manufacturing a semiconductor memory device, comprising: The method of claim 2, wherein the dielectric material of the capacitor is an oxide film or a material composed of an oxide film and a nitride film. The method of claim 2, wherein the seventh step includes a process of applying a polycrystalline silicon layer on the entire surface of the dielectric material layer, a process of applying a photoresist on the polycrystalline silicon layer, and a photoresist to remove the photoresist outside the trench. And c process of etching the dielectric material layer and the polycrystalline silicon layer on the substrate, and e process of removing the photoresist in the trench. The side oxide film formed on the wall of the first trench is formed to have a thickness sufficient to prevent impurities on the wall of the first trench when the doping layer is formed on the wall of the second trench. Method of manufacturing a semiconductor device.

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