KR890008983A - Semiconductor memory device and manufacturing method - Google Patents

Abstract

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Description

Semiconductor memory device and manufacturing method

Since this is an open matter, no full text was included.

1 is a cross-sectional view of one embodiment of a DRAM cell having a conventional trench capacitor.

2 is a cross-sectional view of another embodiment of a DRAM cell having a conventional trench capacitor.

3 is a plan view of the DRAM cell according to the present invention.

4A-4 (i) are cross-sectional views of a manufacturing process of a DRAM cell according to the present invention.

5 is a cross-sectional view taken along the line a-a 'of FIG.

Claims (5)

A semiconductor memory device comprising: an insulated gate field effect transistor having a well of a first conductivity type on a semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type on the surface of the well, and a source and a drain; A gate electrode insulated over the semiconductor substrate between the regions, a bit line connected to the source region, a first word line connected to the gate region, a first trench formed in the semiconductor substrate adjacent to the drain region, and the first trench A second trench that is formed deeper than the depth of the well in succession, a first plate electrode region of the same conductivity type as the substrate formed on the semiconductor substrate inside the second trench wall, and a side surface which is coated on the first trench wall A storage node formed on the trench wall insulated from the first plate electrode by an oxide film and a first dielectric material applied on the first and second trench walls. And a trench separated by a second dielectric material applied on the storage node region wall and a connection region of the same conductivity type as that of the source which connects each other between the storage node region and the source region of the transistor. And a second word electrode formed on the connection area therein, and a second word line formed by separating the insulating material from the second plate electrode to provide the same voltage or different voltages to the first plate electrode and the second plate electrode. Supplying a semiconductor memory device. A method of manufacturing a semiconductor device, comprising: a device isolation oxide film for separating a memory cell and a memory cell on a surface of a first conductive type well formed on a silicon semiconductor substrate and a device isolation oxide film under a device isolation oxide film, the same conductivity type as the well A first process of forming a field doping layer of the second process, a second process of forming a doping layer of a second conductivity type opposite to the well in a region adjacent to the device isolation oxide film, and a mask for forming a trench in the entire surface of the substrate A third process of forming a pattern, a fourth process of forming a first trench by using the trench mask pattern as an etching mask, and forming a side oxide film on a wall of the first trench, and etching the trench mask pattern and the side oxide film Forming a second trench as a mask and forming an impurity doping layer of the same conductivity type as the substrate along the second trench wall; and the trench mask A sixth step of forming a dielectric material layer on the trench wall surface and the entire upper surface of the substrate to remove the pattern and forming the dielectric material of the capacitor on the trench wall surface; and a seventh process of forming a polycrystalline silicon layer in the trench on the dielectric material layer; An eight-step of forming a polycrystalline silicon layer on the polycrystalline silicon layer and the doped layer of the second conductive type on a substrate and doping the polycrystalline silicon layer to a second conductive type; and polycrystalline silicon of the second conductive type A ninth step of forming a dielectric material of a capacitor on the layer, a tenth step of forming a doped polycrystalline silicon layer on the dielectric material layer and a pattern of a cell plate, and an eleventh step of oxidizing the polycrystalline silicon cell plate And removing the oxide film or the dielectric material layer in an area except the upper part of the polysilicon cell plate and forming a gate oxide film of the transistor. A twelfth step of forming a polycrystalline silicon word line on the oxide layer, a thirteenth step of forming a source and a drain region of a transistor opposite to a well in a predetermined region except the cell plate; And a fifteenth step of forming an insulating film on the word line and forming a connection window in a drain region of the transistor, and a fifteenth step of forming a polysilicon bit line on the insulating film. A method of manufacturing a semiconductor memory device. The method of claim 2, wherein the dielectric material of the capacitor is an oxide film or a material composed of an oxide film and a nitride film. The method of claim 2, wherein the seventh step includes a process of applying a polycrystalline silicon layer on the entire surface of the dielectric material layer, a process of applying a photoresist on the polycrystalline silicon layer, and a photoresist to remove the photoresist outside the trench. And c process of etching the dielectric material layer and the polycrystalline silicon layer on the substrate, and e process of removing the photoresist in the trench. The side oxide film formed on the wall of the first trench is formed to have a thickness sufficient to prevent impurities on the wall of the first trench when the doping layer is formed on the wall of the second trench. Method of manufacturing a semiconductor device. ※ Note: The disclosure is based on the initial application.