JPS61269363A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the high velocity and the labor saving by reducing a word line load capacity by forming the first conductive layer to the depth in the middle of the groove formed on a main surface of the substrate of a semiconductor through an insulating film on the side plane of it and further forming the second conductor layer. CONSTITUTION:In the one-transistor type dynamic memory cell, a transfer transistor 2 and a groove capacitor 3 are arranged in series along the side plane of the groove formed almost vertically to a silicon substrate 1 and an isolation region 4 is arranged at the bottom of the groove. The first conductor 5 which functions as one electrode of a capacitor is formed through the insulating film 21 formed on the side plane of the groove. Also the second conductor layer 6 is formed in a predetermined region of the conductor 5, which functions as a gate electrode and a word line. On the region except this part, an insulating film is formed. Memory cells are located in the crossing region of bit lines 12 and the word lines 6 and a gate electrode 6 which is commonly used by two transfer transistors is limited to a region 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, a so-called one-transistor type dynamic memory cell, consisting of a single transistor and a single capacitor, and a method of manufacturing the same.

[Conventional technology]

Conventionally, as this type of memory cell, a memory cell structure has been proposed in which a transistor and a capacitor are arranged in series along the depth direction of the groove on the side surface of a groove formed in the main surface of a semiconductor substrate. This can be seen, for example, in the patent application filed in 1983.
No. 3230.

FIG. 9 is a cross-sectional view showing an example of the structure of this memory cell.
A transfer transistor 2 and a trench capacitor 3 are arranged in series along the side surfaces of a trench formed substantially perpendicularly to a silicon substrate 1, and an isolation region 4 is arranged at the bottom of the trench. Note that 5 is a self-plate forming one electrode of the capacitor, 6 is a gate electrode and word line of transfer transistor 2, 7 and 8 are highly impurity regions forming the source and drain, and 9 is a semiconductor having a conductivity type different from that of substrate 1. 1) is a semiconductor region having the same conductivity type as the channel cut substrate and has a high impurity concentration; and 12 is a bit line.

In the above configuration, since the transistor and the capacitor are arranged in series along the depth direction, the length of the transfer gate can be increased to increase the memory cell capacity and reduce subthreshold leakage without increasing the planar dimensions. It is possible to realize channelization. Furthermore, since the transistors and capacitors can be formed in a self-aligned manner, there is no need for alignment margin between them, and the structure is suitable for increasing the density of memory cells. FIG. 10 shows a plan view of the same structure, and the memory cell includes the bit line 12 and the gate electrode/word line 6 of the transfer transistor 2.
It is arranged like an island in the area of intersection with

[Problem that the invention seeks to solve]

However, in the structure described above, the gate electrode of the transfer transistor is located in the region 13 surrounding the island-shaped cell region.
Since the word line and the substrate are formed overlapping each other, the overlapping area with the substrate tends to become large, making it difficult to reduce the capacitance between the word line and the substrate. This not only prevents speed increase due to miniaturization, but also prevents miniaturization of the word line drive circuit and prevents power saving.

Means for Solving Problem c] In order to solve these problems, the present invention provides a groove formed on the main surface of a semiconductor substrate, and a groove formed in the middle of the groove via an insulating film on the side surface of the groove. A first conductor layer formed to a deep depth, a second conductor layer formed in a predetermined region on the first conductor layer, and an insulating film formed in a region other than the predetermined region are provided. This is what I did.

The manufacturing method also includes: forming a groove on the main surface of the semiconductor substrate; forming an insulating film on at least the side surfaces of the groove; and forming a first conductor to a predetermined depth within the groove; The method includes a step of forming an insulating film in a predetermined region above the first conductor, and a step of forming a second conductor in a region other than the predetermined region.

[Effect]

In the present invention, the capacitance between the gate electrode of the transfer transistor and the substrate, that is, the word line load capacitance can be reduced, and speeding up and power saving can be achieved.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, 1 is a p-type silicon substrate, 2 is a transfer transistor, 3 is a trench capacitor, 4 is an element isolation region, 7 is an n-44I region that is one of the source and drain, and 5 is one electrode of the capacitor. 6 is a gate electrode and word line of the transfer transistor 2 as a second conductor; 21. is a cell plate serving as a first conductor; 22. 23. 24. 25.
26. 27 is an insulating film. FIG. 2 shows a plan view of this semiconductor memory device, in which each memory cell is located at the intersection area of the bit line 12 and word line 6, and the gate electrode 6 shared by two transfer transistors is located at the intersection area of the bit line 12 and word line 6. It is limited to 13. As is clear from the figure, since the region where the gate electrode 6 is formed is limited to the region 13, the overlapping area between the gate electrode 6 and the substrate 1 can be reduced.

As a result, the word line capacitance can be easily reduced compared to the conventional technology, and speeding up and power saving can be achieved.

Note that in this semiconductor memory device, a thick insulating film 1 is provided at the bottom of the trench.
0 is provided, but this is for element isolation, and if element isolation can be achieved completely by other means, it does not necessarily need to be thick. Similarly, p”8 for channel cut near the bottom of the groove.
J [area 1) is provided, but this is not necessarily necessary either. Furthermore, there is no need to limit the channel cut region 1) to the vicinity of the groove bottom, and as shown in FIG.
The region 31 may be arranged over the entire wafer within a predetermined depth range including the vicinity of the groove bottom.

In FIG. 3, 32 is a p layer, and 3o is a silicon substrate consisting of at least two layers, 9 layers 32 and 93 layers 31.

In the semiconductor memory device described above, the cell plate 5 forming one electrode of the capacitor and the substrate 1 are insulated. This is because, in order to accumulate sufficient charge in the capacitor 3, it is necessary to apply a different potential to the cell plate 5 than that to the substrate 1. However, if at least the vicinity of the substrate surface on the side surface of the groove where the capacitor 3 is formed is made n-type, it becomes possible to accumulate sufficient charge in the capacitor 3 even if the cell plate 5 is at the same potential as the substrate 1. Plate 5
and the substrate 1 can be connected at the bottom of the groove.

By adopting such a structure, it is possible to omit the voltage generation circuit for supplying the potential to the cell plate 5 and the contact to the cell plate 5, which saves area, and since the cell plate 5 is at the substrate potential, noise is reduced. Furthermore, the reliability of the capacitor insulating film can be improved.

A semiconductor memory device having such a structure is shown in FIG. 4 as a second embodiment. In the figure, an n-shaded region 9 is provided near the substrate surface on the side surface of the groove where the capacitor 3 is formed, and a cell plate 60 is connected to the substrate 1 at the bottom of the groove. Here, 40 is an isolation p'' region 50, and 70 is an insulating film.

In FIG. 4, the same or corresponding parts as in FIG. 1 are given the same reference numerals. Note that in this illustrated semiconductor memory device, the cell plate 60 and the substrate 1 are connected at the bottom of the groove, but this is not always necessary. Further, the n-shaded area of the capacitor 3 is provided near the side surface of the groove, but as shown in FIG. It is also possible to have a structure in which it is provided across.

In addition, in FIGS. 4 and 5, there is a separation p in the vicinity of the bottom of the groove.
'' region 0 is provided, but this is not necessarily necessary. Also, similar to the p+ region 1) for channel cutting explained in the first embodiment shown in FIGS. 1 and 2, a p'' region for separation is provided. 0 is not limited to the vicinity of the groove bottom, but may be arranged over the entire surface of one of the 31 pJJI areas in a predetermined depth range including the vicinity of the groove bottom.

Next, an embodiment of a method for manufacturing a semiconductor memory device whose final shape is the structure shown in FIG. 1 will be described with reference to FIG. 6. First, a first thermal oxide film 81 is formed on the substrate 1, and an n0 layer 7 is formed on the surface of the substrate 1 by ion implantation. Next, a silicon nitride film 82 and a silicon oxide film 83 are sequentially deposited on the first thermal oxide film 81 by a known deposition method to form a multilayer film. Next, after a resist is applied to the entire surface, a lattice-shaped resist pattern 84 is formed in one lithography step. (FIG. 6(a)) Using this resist pattern 84 as an etching mask, the multilayer film is removed by reactive ion etching (RIE) to expose the surface of the substrate 1.

(Sixth Opening) After removing the resist pattern 84, the substrate 1 is etched by reactive ion etching using the multilayer film as a mask to form a groove. Afterwards, in order to remove contamination and damage caused by etching, the inside of the groove is cleaned with a fluoro-nitric acid solution, a thermal oxide film 85 is formed on the inner surface of the groove by a thermal oxidation method, and a p-oxide film 85 is formed near the flat surface of the bottom of the groove by an ion implantation method. "Region 1) is formed."

(FIG. 6(C)) Next, a silicon nitride film 86 is deposited in the trench using a known technique, and the silicon nitride film 86 deposited on the flat surface is removed by reactive ion etching, leaving only the substrate surface at the bottom of the trench. expose. (FIG. 6(d)) Thereafter, the isolation oxide film 10 is selectively formed only at the bottom of the trench by thermal oxidation in a mixed atmosphere of hydrogen and oxygen, and then the silicon nitride film 86
and remove the oxide film 85 (FIG. 6(e)). Next, after forming an oxide film 21 on the surface of the substrate in the trench by thermal oxidation, polycrystalline silicon 5, which will become a cell plate, is buried in the trench by a known technique. . (FIG. 6(f)) After that, the upper end of the polycrystalline silicon 5 is removed by reactive ion etching so that it is at a predetermined position within the groove, and then the multilayer film 83, 82, 81 on the main surface of the substrate is removed. . At this time, a portion of the oxide film 21 on the inner surface of the groove above the upper end of the polycrystalline silicon 5 is removed. (FIG. 6 (along)) Next, an oxide film 22 is formed on the exposed portion of the surface of the silicon substrate 1 by a thermal oxidation method, and then a silicon oxide film 23 is formed by a known method and buried in the trench.

Then, it is etched back by reactive ion etching.
Silicon oxide films 23 and 22 on the main surface of the substrate are removed to make the main surface of the substrate substantially flat. (Figure 6 (h
)) After forming the oxide film 24 on the main surface of the substrate, a resist is applied to the entire surface, and a resist pattern 87 is formed as a window for the transfer transistor by one lithography step. (6th
(FIG. (1)) Next, using the resist pattern 87 as a mask, the oxide film 23 in the opened area is removed. At this time, this window is oxidized in the area II! 24 and 22 are also removed. After removing the resist pattern 87, an oxide film 25 is formed by a thermal oxidation method or the like, and then polycrystalline silicon 6 is deposited on the main surface of the substrate including the window region by a known method. (FIG. 6 0)) Thereafter, a resist is applied and patterned as word lines by lithography, and processing is performed by dry etching using this resist pattern as a mask. Next, after removing the above resist pattern,
After forming the silicon oxide film 26 by a known method, a resist is applied again, a pattern 88 as a bit line contact hole is formed by lithography, and using this as a mask, the oxide film 26 is etched by reactive ion etching.
．． Polycrystalline silicon 6 and oxide film 24 are removed to expose the surface of substrate 1 at the contact portion. (Figure 6(k))
Next, after removing the resist pattern 8, an oxide film 27 is formed on the surface of the polycrystalline silicon 6 on the side surface of the bit line contact hole by thermal oxidation. At this time, since an oxide film is also formed on the surface of the substrate 1, which is the bit line contact part, the oxide film is removed by reactive ion etching to expose the surface of the substrate 1, and then the aluminum 12 for the bit line is etched.
is deposited and a bit line is formed through a lithography step and an etching step to obtain the final shape. (Figure 6 (1)
)) In the above example, the isolation oxide film 10 was formed by a thermal oxidation method (FIG. 6(e)), but the same oxide film may be formed by a CVD method or the like. In this case, channel cut) 8J
[Area 1] After ion implantation for formation (Fig. 6 (corresponding to C1),
After a silicon oxide film is buried in the trench by a known method, the silicon oxide film is removed by reactive ion etching to a predetermined thickness. Thereafter, polycrystalline silicon 5 is formed and the same steps as in the first embodiment described above (FIG. 6 (fl) onwards) are performed.

Note that, as previously described in the embodiment of the semiconductor memory device,
It is not necessarily necessary to make the isolation oxide film thick; in that case, the series of steps for forming the oxide film 10 (Fig. 6 (dl,
(corresponding to 81) can be omitted.

Furthermore, in the example, high concentration region for channel cut 1)
is formed near the bottom of the trench by ion implantation, but it is not necessary to limit the method to ion implantation. Furthermore, the formation position need not be limited to the vicinity of the groove bottom, and the high concentration region may be formed within a predetermined depth range including the groove bottom over the entire wafer surface. In this case, for example, a wafer on which a p-layer is laminated by a p-layer epitaxial method may be used as the substrate, and the groove may be formed so that the groove bottom reaches the underlying p-layer. Note that it is also possible to omit the above-mentioned high concentration region, and in this case, the ion implantation step for forming the high concentration region (FIG. 6(C)) may be omitted.

As described in the second embodiment of the semiconductor memory device, the n-shaded region 9 may be provided near the side surface of the trench where the capacitor 3 is formed. The manufacturing method of the embodiment using FIG. 4 as a final process diagram will be explained below using FIG. 7. As in the first embodiment of the semiconductor memory device shown in FIG. 1, after forming a thermal oxide film 81 on a substrate 1, forming an n layer 7, then depositing a silicon nitride film 82 and a silicon oxide film 83. After resist adhesion and one lithography process, a lattice resist pattern 84 is formed.
is formed, and using this as a mask, a multilayer film 83.82.81
is etched to expose the surface of the substrate 1. (Figure 7 (
a)) After removing the resist pattern 84, the multilayer film 83.82
．． A groove of a predetermined depth is formed using 81 as a mask, and after cleaning the groove with a fluoro-nitric acid solution, a silicon oxide film 91 is formed by a known method. (Seventh Opening) Next, the oxide film 91 deposited on the flat surface is removed by reactive ion etching to expose the substrate surface at the bottom of the groove.

At this time, an oxide film 91 remains on the side surfaces of the trench. (Figure 7 (C
)) Grooves are formed again by reactive ion etching using the oxide film 91 and the multilayer films 83, 82, and 81 as masks, and the insides of the grooves are cleaned with a fluoro-nitric acid solution.

(Fig. 7(d)) Next, polycrystalline silicon 92 doped with phosphorus is buried in the groove, and the substrate in the groove is heated by thermal diffusion using this as an impurity diffusion source.
An n-shade region 9 is formed near the exposed portion of the surface. At this time, the oxide film 91 functions as a diffusion mask, and prevents regions other than the capacitor portion of the side surfaces of the trench from becoming n-type. (FIG. 7(e)) Next, after removing the phosphorus-doped polycrystalline silicon 92, reactive ion etching is performed using the oxide film 91 and the multilayer film 83, 82, 81 as a mask, so that the bottom of the groove is etched into the n shadow region 9.
After forming the groove again so that it is in the lower predetermined position,
Clean the inside of the groove with a fluoro-nitric acid solution. (FIG. 7(f)) Next, after forming a thermal oxide film 50, a p'' region 40 is formed near the bottom of the trench by ion implantation, and the oxide film 50 on the flat surface of the bottom of the trench is removed by reactive ion etching. , the surface of the substrate 1 is exposed only at the bottom of the groove.

(FIG. 7 (Shu)) Next, after burying polycrystalline silicon 60 in the groove, remove it by reactive ion etching so that the upper end of polycrystalline silicon 60 is at a predetermined position, and then remove the silicon oxide film 8.
Remove 3. At this time, oxide film 91 is also removed. Next, after removing the silicon nitride film 82 and the oxide film 81,
An oxide film 70 is formed by thermal oxidation. (FIG. 7(h)) Thereafter, in accordance with the same process as in the first embodiment described above (FIG. 6 (corresponding to the following), the silicon oxide film 23 is embedded in the trench, and then etched by reactive ion etching. After etching back and removing the oxide films 23 and 70 on the main surface of the substrate 1 to make the main surface almost flat, a thermal oxide film 24 is formed on the main surface of the substrate, resist is attached, and a resist pattern is formed through one step of lithography. 93. (Figure 7 (1))
Using the resist pattern 93' as a mask, the silicon oxide film 23 and the thermal oxide film 70 in the opened area are removed, and at this time, the oxide film 24 in the same area is also removed. After removing resist pattern 93 and forming thermal oxide film 25, polycrystalline silicon 6 is formed on the main surface of substrate l including the window region. (FIG. 7: (j)) Next, after resist deposition and a lithography process, the polycrystalline silicon 6 is processed into a word line by dry etching, the resist is removed, and a silicon oxide film 26 is deposited. Another lithography process is performed to form a resist pattern 94 as a contact hole, and using this as a mask, the silicon oxide film 26. Polycrystalline silicon 6 and oxide film 24 are removed, and substrate 1 at the contact portion is removed.
expose the surface. (FIG. 7(k)) The resist pattern 94 is removed and a thermal oxide film 27 is formed on the surface of the polycrystalline silicon 6 on the side wall of the contact hole by thermal oxidation.
form. At this time, an oxide film is also formed on the surface of the substrate 1 in the contact area, so this oxide film is removed by reactive ion etching and the surface of the substrate 1 is exposed again, after which aluminum 12 for the bit line is attached and lithography is performed. A bit line is formed through one step and an etching step to obtain the final shape. (FIG. 7(1)) In the second embodiment of the above manufacturing method, the n
Although phosphorus-doped polycrystalline silicon 92 is used as an impurity diffusion source for forming the shadow region 9, other materials such as phosphorus-doped glass or a gas such as POCl3 may also be used. Other, n
The shadow region 9 may be formed by ion implantation. Changes in the process in this case will be explained using FIG. 8. First, as in the embodiment shown in FIG. 7, after forming a lattice-shaped trench, the side surfaces of the trench are covered with a silicon oxide film 91, and the surface of the substrate 1 at the flat part of the bottom of the trench is exposed (FIG. 7 (corresponding to C1). ).

(FIG. 8(a)) Next, after forming a thermal oxide film 95, using the multilayer films 81, 82, 83 and the oxide film 91 as a mask, an n-shade region 9 is formed near the bottom of the groove by ion implantation.

(8th opening)) Next, after removing the oxide film 95 by reactive ion etching, the bottom of the groove is located at a predetermined position below the n shadow area 9 using the oxide film 91 and the multilayer film 81°82.83 as a mask. After forming the groove again, the inside of the groove is cleaned with a nitric acid-based liquid. (FIG. 8(C)) Following the same steps as in the second embodiment shown in FIG. Proceed with the steps starting from the figure (corresponding to Shu) to obtain the final shape shown in Figure 8 (di).

In the second embodiment, the multilayer films 81, 82, 83 and the silicon oxide film 91 are used as masks to prevent regions other than the capacitor portion from becoming n-type when forming the n-shade region. However, for example, before forming the multilayer films 82, 83, etc., ions are implanted over the entire cell region.
As shown in FIG. 5, if an n shadow region 80 is formed within a predetermined depth range where the capacitor 3 is formed,
The above-mentioned mask is no longer necessary, and it becomes possible to use the same steps as in the first embodiment of the method for manufacturing a semiconductor memory device.

In addition, in this second embodiment, the cell plate 60 and the substrate 1 are connected at the groove bottom, but it is not necessary to connect them, and the reactivity is performed after forming the p'' region 40 near the groove bottom. The step of removing the oxide film 50 on the flat surface of the trench bottom by ion etching (FIG. 7 (phantom)) can also be omitted.

Furthermore, the formation of the p'' region 40 near the trench bottom is limited to the ion implantation method, just as in the case of forming the high concentration region for channel cut described in the first embodiment of the method for manufacturing a semiconductor memory device. It is not necessary. Also, of course, it is also possible to use an epitaxial wafer in which a p-layer is stacked on a p-layer as a silicon substrate, and to form a groove so that the bottom of the groove reaches the underlying p-layer. , p'' region 40 can be omitted; in this case, p''
It is better to omit the ion implantation step for forming the region 40 (FIG. 7(gl)).

Each of the manufacturing methods described above is an example of the present invention, and the present invention is not limited thereto. for example,
Polycrystalline silicon was used as the material for the cell plate and the gate electrode and word line of the transfer transistor, as it can be formed by CVD and the surface can be oxidized, but the material is not limited to this, and examples include molybdenum, tungsten, etc. metals or silicides thereof may also be used. Similarly, the bit lines are not limited to aluminum, but other metals, silicide, etc. can be used. Furthermore, various oxide films used as insulating films etc. are not limited to these, for example, PSG and BP.
Other insulating films such as SG or silicon nitride film may also be used.
Furthermore, the method of forming the same is not limited. others,
Although each embodiment uses a p-type silicon substrate as the substrate 1, it goes without saying that if a substrate of opposite polarity is used, the polarity of each region will be reversed accordingly.

〔Effect of the invention〕

As explained above, the present invention includes a groove formed on the main surface of a semiconductor substrate, a first conductive layer formed to a depth halfway into the groove via an insulating film on the side surface of the groove, and a first conductive layer formed on the main surface of a semiconductor substrate. By providing a second conductor layer formed in a predetermined region on the first conductor layer and an insulating film formed in a region other than the predetermined region,
Transfer transistor area can be limited,
The capacitance between the transfer transistor's gate electrode and the substrate, that is, the word line load capacitance, can be reduced, increasing speed.

This has the effect of reducing power consumption.

The manufacturing method also includes: forming a groove on the main surface of the semiconductor substrate; forming an insulating film on at least the side surfaces of the groove; and forming a first conductor to a predetermined depth within the groove; By including the step of forming an insulating film in a predetermined region above the first conductor and the step of forming a second conductor in a region other than the predetermined region, a capacitor can be formed in a self-aligned manner, and a groove and a In addition, since the alignment allowance for forming the transfer transistor region can be included in the alignment allowance for forming the bit line contact, it is possible to increase the density of memory cells.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a sectional view showing a modification of the first embodiment, and FIG. is a sectional view showing the second embodiment, FIG. 5 is a sectional view showing a modification thereof, FIG. 6 is a sectional view showing an example of the method for manufacturing the semiconductor memory device of FIG. 1, and FIG. FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device, FIG. 8 is a cross-sectional view showing a modification thereof, FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor memory device, and FIG. is its plan view. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Transfer transistor, 3...Capacitor, 4...Isolation region, 5.6
0...Cell plate, 6...Gate electrode/word line, 7...n'' region 9.80...n shadow area,
10...Isolation oxide film, 1). 40... p″ area 12... ・Bit line, 13... ・ ・ Area,
21.22゜23, 24. 25. 26. 27.
50. 70...Insulating film, 30...Silicon substrate, 31...P layer layer, 32...P layer.

Claims (2)

[Claims] (1) In a semiconductor memory device consisting of a single transistor and a single capacitor, a groove is formed on the main surface of the semiconductor substrate, and the groove is formed to a depth halfway through the groove through an insulating film on the side surface of the groove. a second conductor layer formed in a predetermined region on the first conductor layer;
an insulating film formed in a region other than the predetermined region, a capacitor is formed on the side surface of the groove in the region where the first conductor layer is formed, and a capacitor is formed on the side surface of the trench in the region where the second conductor layer is formed. A semiconductor memory device characterized in that a transistor is formed. (2) forming a groove on the main surface of the semiconductor substrate; forming an insulating film on at least the side surfaces of the groove; forming a first conductor to a predetermined depth within the groove; 1
forming an insulating film in a predetermined area on the conductor;
A method of manufacturing a semiconductor memory device, comprising the step of forming a second conductor in areas other than the predetermined area.