JPS61179571A - Memory cell and array thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to semiconductor devices, and particularly to dynamic random access memory, that is, dynamic RAM (hereinafter referred to as dRAM).

[Prior Art] The development of large-scale monolithic dRAMs poses a number of problems, one of the most important of which is that in order to increase the number of memory cells that can be integrated on a single chip, The problem is how to prevent the incidence of soft errors from increasing even if the dimensions of the software are reduced.

Large-scale dRAM uses silicon as the primary construction material, and each memory cell typically has a single MO8 field effect transistor with its source connected to a capacitor, its drain connected to a bit line, and its gate connected to a word line. It is. Such a memory cell operates so that when a charge is added to the capacitor, the logic becomes a logic 1, and when no charge is added, the logic becomes a logic 0. Conventionally, the cell capacitor in this case is formed by an inversion layer separated from the upper electrode layer by a thin oxide layer and separated from the substrate by a depletion layer.

However, in order to maintain stable circuit operation, it is necessary to set the capacitance of the capacitor to a large value that provides a sufficient S/N ratio. It has to be bigger. Furthermore, such MOS capacitors are susceptible to charges generated in the substrate by alpha particles (5HcV alpha particles can generate more than 200 hemtocoulombs ([C) of harmful electrons), and noise intruding from the substrate. It is easily affected by PN junction leakage over the entire area of the capacitor, subthreshold leakage (leakage below the threshold voltage) of the MOS FET in the cell, etc. The charge stored in one dRAM is normally 250 fC, so if the power supply voltage is 5 V, the capacitance of the capacitor needs to be 50 f[, and the thickness of the dioxide layer for charge storage is 150 fC]. In this case, approximately 20 microns square of capacitor area was required. In a memory cell using a conventional two-dimensional structure dRAM, this defines the minimum size of the cell.

One attempt to address these problems is Joly et al.'s
crystallizeclPolysilicon
J (41EEE Elec, Dev, Lett
, 8°1983), which attempted to form all of the basic elements of the cell, including the access transistor and charge storage capacitor, in a beam-recrystallized polysilicon layer deposited on an oxide layer on a silicon substrate. . In this case, the bit line is contained in a recrystallized polysilicon layer, and turning on the transistor causes charge to flow into the charge storage region. Highly doped recrystallized polysilicon surrounded by thermally grown oxide on the top, bottom and three sides is used as the charge storage region. The charge storage capacity obtained in this way is comparable to that of a normal capacitor with an equivalent storage area, because the electrodes above and below the region are separated from the charge storage gA region in the recrystallized polysilicon by a thin oxide layer. Approximately twice as much. Moreover, this charge storage region is isolated by the underlying oxide from charges injected into the substrate from circuitry around the region, and from charges penetrating into the substrate due to alpha particles and other radiation that cause soft errors. becomes. Furthermore, the capacitance of the bit line may be reduced due to the presence of a thick oxide layer below the bit line and complete sidewall oxide isolation. However, even if the capacity is twice the normal capacity, it is impossible to make the area occupied by the cell capacitor sufficiently small.

Another attempt to miniaturize dRAM is to extend the capacitor plates into the interior of the substrate. Such a capacitor is called a corrugated capacitor, and is described in “A Corrugated Capacitor” by H. Sunami et al.
Capacitor Ce1l (CCC) for H
egabit Dynamic 803 Hemori
esJ (IEEE IEDHTe, c, h, Di
gest 806.1982) and ``8 Corrugated Capacitor C'' by Sunami et al.
e1l (CCC) forHeaabit D'y
na1c HO3HemoriesJ (41E
EE Elec.

Dev, Lett, 90.1983 > and even 1. Ito et al.'s An Experimental
IMb DRA) 4 With On-ChipVo
ltage Limter j (1984[EE
El5SCC Digest of Tech, Pap
er 282) and others. This corrugated capacitor extends to a depth of 2.5 microns inside the silicon substrate, and is fabricated using a CVD dioxide silicon dioxide mask using a conventional CCj! A trench is formed by a reactive sputter etching method according to No. 4.
), wet etching is performed to remove scratches and dirt caused by dry etching. After forming the trench, a charge storage layer consisting of a silicon dioxide/silicon nitride/silicon dioxide triple layer is formed on the trench walls, and the trench is then filled with LPGVD polysilicon. This is because such a corrugated capacitor, in the case of a three-layer, 7-micron cell with a capacitance of 60 fF, has a capacitance more than seven times that of a normal cell.

A third attempt to reduce the area occupied by a cell capacitor is similar to the method of forming trenches as described above.
cron 803 VLSI ProcessTech
nolooiesJ (IEEE IEDHTech
, Digest 19° 1983) [A Submicron CHO3 Hegabi et al.
t Dynamic RAM Technology
UsingDoped Face Trench Ca
pacitor Ce1lJ (IEEEIEDHT
ech, Digest 319.1983) and ■
, r DeDletion Trench by Morie et al.
h Capacitor Technology for
Hevabit Level HO3dRAHJ
(41EEE Elec, Dew, Lett, 4
11.1983), etc., but all of these have the same structure as a normal cell except that the capacitor plate is formed on the trench wall of the substrate instead of being parallel to the substrate. This is a description of memory cells. Such a trench capacitor can have a large capacitance per unit area of the substrate simply by using a deep trench, and according to the three papers mentioned above, it is manufactured as follows.

That is, first, crystal orientation (100), p type, resistivity 4
A trench having a width of 0.4 to 1.0 microns is formed on a -5 ohm CRA silicon substrate by electron beam direct writing. Then reactive ion etching (RIE) with CBrF3 under a pressure of about 14 mTorr.
After engraving a 1-3 micron deep trench by
By performing an etching process in a mixed solution of nitric acid, acetic acid, and hydrofluoric acid, scratches caused by the RIE process are removed from the trench surface. Next, PSG (phosphorus silicate glass) is deposited by CVD using a P H/S i H/02 gas system to diffuse phosphorus into the trench surface layer.
Etch away the PSG with hydrofluoric acid. Subsequently, 150-500 layers of 5i02 are grown in dry oxygen on the trench surface, or Si3N4 is deposited by CVD to a thickness of 500 layers, and finally the trench is filled with LPGVD polysilicon. In this way, the capacitance per unit area of the trench sidewall is comparable to the capacitance per unit area of a normal capacitor, and therefore a capacitor with a large trench depth increases the charge storage area per unit area of the substrate. By this, it is possible to reduce the substrate area of the cell.

On the other hand, it is also a well-known technique to perform isolation using trenches, and its research has been widely conducted. For example, R. Lang's rDecp Trench
l5olated CHO3Devices j
(IEEEIEDCHTech, Di(rest 2
37.1982) and [A 5tu by K. Cham et al.
dy of the trench inversio
nProblem in the Trench CH
O3 Technology J (4IEEE El
ec, Dev, Lett, 303.1983) and R U-Groove l5o by A, A Yasari et al.
lation Technique for l1iah
5peed Bipolar VLSI's
J (IEEE IEDtHTech, Dlge
st 62.1982 > and [A
n l5O1atiOn TeChnOlooy fo
r High Performance Bipolar
Memories--10P-111 (IEEE I
ED814Tech, Dioest 58.1982
> Ya, T.

[tight-Speed Latc] by Yamaguchi et al.
hup-FreeO, 5-μm-Channel C
HO3Using Self-Aligned TiS
i2and Deep Trench l5olati
on TechnologiesJ (IEEE IED
I Tech, Digest 522.1983)
Ya, S.

“Directions in CH” by Koyama et al.
O3TechnoloayJ (IEEE IEDt
HTech, Digest 151゜1983) and
[Characterization and Mod
elling of the trench 5urfa
ce Problem for the Trench
Isolated CQO3TechnologyJ
(IEEE IEDtHTech.

Dioest 23.1983) etc. have a description thereof. The isolation trenches described in these
Trenched corrugated capacitors are formed in a manner similar to that described above. i.e. patterning (typically done using an oxide mask)
Ya, CBrF 5CC14, CI H, CCj! O,
, etc., etching, thermal oxidation of sidewalls (accompanied by nitride layer formation by LPCVD), and even embedding with polysilicon.

[Problems to be solved by the invention] However, using a trench capacitor reduces the dR
This does not completely solve the problem of miniaturizing AM cells, and in any case, such as a vertically arranged FET or a substantially vertically arranged trench capacitor,
At present, the area occupied by the cell on the substrate is still large.

[Means for Solving the Problems] The present invention forms a cell transistor on the side wall of a trench provided in a substrate in which a cell capacitor is formed, and a word line and a bit line intersect with each other above the trench. The present invention provides a one-transistor dRAM cell structure and an array of such cells, which stack the transistors on top of the capacitors to minimize the cell area on the substrate, thereby increasing the This is to increase the density of cell integration.

In one embodiment of the invention, one plate of the capacitor and the channel region of the transistor are formed in the bulk sidewall of the trench, and the other plate of the capacitor and the gate region of the transistor are formed in the trench. Formed by filling polysilicon and separated by an oxide layer inside the trench. Note that the signal charge is accumulated in the capacitor plate formed of the polysilicon.

Embodiment] FIG. 1A shows a one-transistor, one-capacitor cell connected to a bit line and a word line as an embodiment of the present invention, and its operation mode is as follows. That is, the capacitor 12 stores a charge representing one bit of information (for example, a state in which no charge is stored represents a logic O, and a state in which a charge corresponding to a potential of 5 volts between the plates of the capacitor is stored represents a logic 1). ).

This one bit of information is accessed (read or write a new bit) each time a voltage is applied to word line 14 connected to gate 16, thereby turning on transistor 18. By turning on, the capacitor 12 conducts with the bit line 20 to perform reading or writing.
In order to compensate for the disappearance of the accumulated charge in the second example, it is necessary to periodically refresh the charge, and this is the origin of the name dynamic RAM (dRAM).

FIG. 1B is a plan view showing a part of the dRAM array consisting of a word line 14 and a bit line 2o, in which the memory cells 30 of the above embodiment are arranged at the intersection of each line, and the bit line 20 is a word line. It is formed to pass below 14. These memory cells 3
o extends below these lines in the substrate to maximize memory density. As shown in the figure, if the minimum figure size is f and the minimum layer spacing allowable size (@small print alignment error allowance) is R, then the area of each cell is (2(f
+R)). Therefore, for example, the minimum figure size is 1.0
If the minimum interlayer tolerance is 0.25 microns, the area of each cell will be approximately 6.25 square microns.

FIG. 2 is a sectional view of the memory cell 30 according to an embodiment of the present invention. This memory cell 30 is formed on a P+ type silicon base 32 having a P type epitaxial layer 34, and includes a bit line 2o consisting of an N+ type buried layer, an oxide layer 42 for bit line insulation, and an N+ polysilicon layer 2o. the word line 14 and the channel 44 of the transistor 18; the gate oxide layer 46 of the transistor 18; the N+ diffusion region 48 forming the source region of the transistor 18; In other words, N+ forms the other electrode plate when it is used as the ground side electrode plate.
It includes a polysilicon region 50 and an oxide/nitride/oxide stack 52 forming an insulating layer between the plates of the capacitor 12. The cross-section of memory cell 3o in FIG. 2 corresponds to the arrow line 2--2 in FIG. 1B, and therefore the cross-sectional structure of trench-formed capacitor 12 and transistor 18 will be clear from FIG. 1B.

In the memory cell 30 configured as described above, one plate of the capacitor 12 is formed by the N+lJ region 48° 50, and the other plate is formed by the substrate 32 and the shrimp layer 34. However, in this case, by making the impurity concentration of the shrimp layer 34 much lower than that of the P+ type substrate 32, the N''/
The capacitance of the P junction and the capacitance of the N+ type polysilicon region 50/stack 52/P+ type layer 34 are both much smaller than the capacitance of the N+ polysilicon region 1450/stack 52/P+ substrate 32 and can be ignored. Make it so. Further, as will be explained next, the plate area of the shrimp layer 34 is smaller than that of the substrate 32, and for this reason as well, the capacity of the shrimp layer 34 itself is not a very important factor. In addition, when the cross section of the trench to be formed is 1×1 micron and the depth is 5 microns, this 1 micron depth shall be obtained by the shrimp layer 34 and the bit line 20 layer, and in this case, the pole of the capacitor 12 The plate area will be approximately 17 square microns. The illustrated P+ substrate 32 is also a ground layer common to all memory cells 30 in the array shown in FIG. 1B.

The transistor 18 of each memory cell 3o has a bulk silicon configuration with a polysilicon gate, the channel 44 is part of the 111 layer 34, and the source region 48
(which is also part of one plate of capacitor 12) and drain region 20 (which is also bit line 2o) are N+ diffused in P epi layer 34 and gate oxide layer 46.
is grown on the trench face of the 111 layer 34, and the gate is at the bottom of the polysilicon word line 14. Although the insulating oxide layer 42 is of considerable thickness, the word line 14 as a gate still
The structure overlaps the source and drain regions of the transistor.

Next, an embodiment of a method for manufacturing the memory cell 30 having the above structure will be described, and through this description, the dimensional and material characteristics of the memory cell 30 will be clarified. Third
Figures 8 to 3G show this production procedure.

1 Resistivity 1X10-2 when crystal orientation is (100)
A 111 layer 34 having a carrier concentration of 2×10 16 cells/cm ” and a thickness such that the final thickness after all heat treatments is 2.0 μm is formed on a P+ silicon substrate 32 of 1 ohm cm or less. After the field oxide layer 36 and P-type channel stop 38 are formed by conventional methods, a stress relief oxide layer is grown and LPGVD nitride is deposited on the oxide layer.The active region ( The nitride and oxide outside the active region are removed by patterning and plasma etching (the bit line 2o and the periphery of the cell array), and boron is implanted using the nitride layer as a mask, resulting in a carrier concentration of 1×. After forming channel stops 38 of 1017/3 to a depth of 400, the field oxide layer 36 is grown to a thickness of 8000.Then, after removing the nitride layer, the active A portion of the region where the bit lines 2o are to be formed is defined, and arsenic is implanted so that the carrier concentration becomes 1×1020 pieces/car.
0 to a depth of 2000 people. Thereafter, the photoresist was removed and a protective film of oxide was formed, and the resulting structure is shown in FIGS. 3A and 3B. 3rd A here
The figure is a cross-sectional view along the bit line 20, and the third B
The figure is a cross-sectional view taken in a plane perpendicular to the bit line 20. Note that the line width of the bit line 20 is approximately 1.5 microns as described with reference to FIG. 1B.

2. To form a trench with a cross section of 1 micron,
Micron plasma enhanced CVDII? Chemical layer 6
4 is deposited and patterned. This patterned oxide layer 6
The trench is etched to a depth of 1.25 μm by performing RIE treatment with HCl using No. 4 as a mask. R from the wall of the trench thus formed
After removing scratches and dirt from the IE process by wet etching with acid, a protective oxide layer 65 is thermally grown on the walls and bottom of the trench, and nitride 66 is deposited by LPGVD to roughly treat the sidewalls of the trench. , to protect the oxide layer on the sidewalls to limit diffusion during subsequent processing steps. The oxide layer 6
The thickness of the nitride layer 66 is approximately 200, for example.
The thickness of the network is, for example, 1000 people. The structure thus obtained is shown in Figure 3C. Note that this Figure 3C is the following Figure 3D.
The same applies to FIGS. 3A to 3G, but all of them are views showing a cross section along the bit line 2o.

3. Next, the RIE process using HCI is performed again to roughly lower the trench. In this case, the oxide layer 64 is also slightly eroded, but this layer does not cause any particular problem because the initial deposition thickness of this layer is sufficiently large.

When the trench is now approximately 5.0 microns deep, the trench is cleaned as described above;
After the oxide is thermally grown to form the insulating layer stack 52 of the capacitor 12 100 thick, a 75 thick nitride is deposited by LPGVD. The nitride layer is then thermally oxidized to complete the dielectric properties, resulting in an initial oxide/nitride/Ride layer stack 52. The trench thus formed is filled with N+ doped polysilicon (region 50) as shown in FIG. 3D.

4. Planarize the polysilicon region 50 by, for example, spin coating on photoresist, and then planarize the polysilicon region 50 on its surface and inside the trench 30.
00 people will be completely plasma etched. In this case, the plasma etch inside the trench is performed from the top of the insulating stack 52 down and over the substrate 32. As will be described later, the polysilicon region 11!50 is the stack 5.
In the case where the polysilicon region 1450 extends slightly below the upper end of the polysilicon region 1450 and above the substrate 32, the upper end position of the polysilicon region 1450 does not have to be particularly strict. See Figure 3E.

5. Remove exposed portions of stack 52 (in this case, nitride layer 66 is much thicker than stack 52;
In removing exposed portions of stack 52, nitride layer 66 is removed.
are not significantly removed). Vapor phase diffusion of phosphorus then forms a diffusion region 48 having a thickness of at least 2,000 people (FIG. 3F). In addition, in FIG. 3F, the diffusion region 48
appear to be formed in two places, but these regions are part of a single annular region surrounding the trench,
It forms the source of the transistor 18.

However, at this time, the gate oxide layer of this transistor 18 has not yet been formed.

6. Deposit N+ type polysilicon by LPCVD, planarize it, and perform plasma etching completely to the plane and directly below the oxide layer 65 and oxide layer 66 in the trench. This N+ polysilicon layer becomes a part of the polysilicon region 50 and increases its thickness, and is indicated by the same reference numeral as the polysilicon region 50 in the drawing (FIG. 3G). In this case as well, the polysilicon region 50 sufficiently overlaps the diffusion region 48 to provide good electrical contact therebetween, and the oxide layer 66
The nitride layer 65 is completely exposed and the transistor 1
If the gate 8 reliably covers the channel region, the position of the upper end of the polysilicon region 50 does not have to be very strict, but this will also be described later.

7. Grow a thermal oxide layer 56 on the exposed portions of polysilicon region 50 and diffusion region 48 to a thickness of approximately 1000 nm. In this case, the oxide layer 65 generates a bird's beak at its lower edge, but growth is inhibited by the nitride layer 66 at other locations.

This thermal oxide layer 56 is formed to reduce the source/gate parasitic capacitance of the transistor 18, and may be omitted depending on the case. Next, after etching the nitride layer 66, a wet etch is performed to remove the oxide layer 65 (and a portion of the much thicker thermal oxide layer 56), thereby removing the channels 44 and the diffusion. A portion of region 48 is exposed. This exposed channel 44
gate oxide layer 46 to a thickness of 250 nm (which increases the thickness of thermal oxide layer 56) and then N+
Deposition and patterning of a polysilicon layer 14 to form the word line 14 results in a cell having the cross-sectional structure described in connection with FIG.

Next, a second embodiment of the dRAM according to the present invention (shown as a memory cell 130 in FIG. 4C) and a second embodiment of the manufacturing method according to the present invention will be described below with reference to FIGS. 48 to 4D. Refer to and explain. These Figures 4A-4D are
Both the figure and FIGS. 3A to 3G are sectional views of the same type.

1. After growing a thermal oxide layer 135 with a thickness of 1000 nm on a P+ substrate 132 with a crystal orientation of (100), a plasma enhanced CVD II9 oxide layer 137 with a thickness of 1 micron is deposited. This oxide layer 137 is then patterned to form trenches of 1 square micron in cross section, and then, using this layer as a mask, an RIE process with HCl is performed to etch the trenches to a depth of 5 microns.

The trench sidewalls are then cleaned and a capacitor oxide layer 152 is thermally grown on the sidewalls and the trench bottom, followed by a 4 micron arsenic implanted polysilicon region 150.
is deposited by sputtering (FIG. 4A).

2. Perform wet etching on each of the above oxide layers.

This removes the exposed portion of capacitor oxide layer 152 and lifts off the portion of polysilicon region 150 above oxide layer 137. Next, thickness 2
000 1-2 ohm crtr silicon epi layer 144
N+ bit line 2o and the transistor 18 by evaporating and implanting ions into the layer.
A layer 120 to become the drain of the transistor 18 and a region 148 to become the source of the transistor 18 are formed (FIG. 4B).
. In this case, since the region 148 is formed on the upper surface of the polysilicon region 150, it is naturally expected that the region 148 will have various defects. Since it is an implanted part, such defects do not pose much of a problem.

By performing the 3 and 7 anneal treatments, the region 148 is slightly bulged by promoting diffusion of the implanted impurity. Gate oxide layer 146 is then thermally grown to 250 layers, followed by N+ polysilicon deposition and patterning to form word lines 14. The structure of the dRAM cell 130 thus obtained is shown in FIG. 4C.

Next, a third embodiment of the dRAM according to the present invention will be described. This third embodiment, designated by the reference numeral 160, is a variant of the dRAM cell 130 described above, and is produced by a third method embodiment, which is a variation of the second embodiment of the method according to the invention, as described above. It is something that will be done. In the following description, the same reference numerals as above indicate corresponding items in the above embodiment.

1. After performing step (1) of the second embodiment, the oxide layer is etched in step (2).

2. 2000mm thick LPGVD polysilicon layer 14
N+ layers 120 and 148 are formed by depositing 4 and implanting impurities therein.

The resulting structure is similar to that of FIG. 4B, except that in this case regions 120, 144 and 150 are polysilicon layers rather than shrimp layers as in the second embodiment.

3. The regions 120, 144 are converted into a shrimp layer on the substrate 132 by annealing and solid-phase epitaxy, and as a result, part of the regions 148, 150 becomes single crystal.

The broken waveform line in FIG. 4D conceptually shows such partial single crystallization. However, among such crystallized regions, it is only the region 144 (channel region of the transistor 18) that affects the operating characteristics. Note that the high temperature used in this process causes diffusion of impurity ions, causing the region 148 to bulge as shown in FIG. 4D.

The N+ type layer 120 is then patterned and etched to form the bit line 20.

4. The gate oxide layer 146 is then grown to a thickness of 250 nm, followed by the deposition, patterning and etching of the N+ polysilicon layer 14 to form the word line 14.
form. The cross-sectional f1 structure of the dRAM cell 160 thus obtained is shown in FIG. 4E.

cl RAM t/lz 130, 1600)
The operation Lt difference also depends on the cell memory cell 30 described earlier.
The behavior is equivalent to . That is, the transistor 18 has its drain 201 channel region 144, source 148
, the gates 14 are all vertically arranged, and one plate of the capacitor 12 is placed in the N+ region [14
According to 8/150, the other bridge plate is formed using the P+ substrate 132, and the oxide layer 152 and the region 1 are formed.
48 and the reverse bias junction between substrate 132 to form a dielectric layer.

Note that the above step (3) of the manufacturing method of the cell 160 has been changed 4
However, the N+ layer 120 may be patterned and etched after a solid phase epitaxy process is performed to define and implant channel stops att between the plurality of bit lines 20. The method of forming the channel stop region in this case is similar to the method of forming the channel stop 38 between the bit lines 20 in the first embodiment of the method according to the invention.

Various embodiments of the dRAM and its manufacturing method according to the present invention have been described above, but these embodiments may be modified by changing the above-mentioned dimensions, shape of the trench, depth of impurity implantation, type of substitute material, etc. as appropriate. , using ion diffusion instead of ion implantation, using wet etching instead of dry etching, using a halogen carbon compound instead of HCl in RIE,
Omitting the protective nitride layer 66 and making various other changes will be readily apparent from the foregoing description.

[Brief explanation of the drawing]

FIG. 1A and FIG. 1B each show a dRA according to the present invention.
FIG. 2 is a cross-sectional view of a first embodiment of a dRAM cell according to the present invention taken along line 2-2 in FIG. 1B. The cross-sectional views shown in FIGS. 38 to 3G are diagrams showing a series of steps in manufacturing the dRAM cell according to the first embodiment according to the first embodiment of the cell manufacturing method according to the present invention. Figures 4 to 4E are diagrams showing a series of steps when manufacturing dRAM cells according to the second and third embodiments of the cell manufacturing method according to the present invention. 12... Capacitor, 14... Word line, 16... Gate, 18... Transistor, 20... Bit line, 30.130, 160... Memory cell, 32.132
...substrate, 34.144... shrimp layer, 42... oxide layer, 44... channel, 46.146... gate oxide layer, 48... diffusion region, 50.150...・Polysilicon area, 52.152・
...Oxide/Nitride/Oxide stack.

Claims (1)

[Claims] (1) In a memory cell array provided on a substrate, (a
) a plurality of mutually parallel first conductor lines provided on the substrate; (b) a plurality of mutually parallel second conductor lines intersecting with and insulated from the first conductor lines; (c) a plurality of memory cells provided at each intersection of the first and second conductor lines, each of the memory cells having an electric field provided in a trench formed in the substrate below the intersection; an effect transistor and a capacitor, the drain region of the transistor connecting it to one of the first conductor lines, and the gate region connecting it to one of the second conductor lines; The memory cell array further comprises a source region connected to a first electrode plate of the capacitor. (2) (a) The memory cell array according to claim 1, wherein a second electrode plate of the electrode plates of the capacitor is connected to the substrate. (3) In a memory cell provided on a semiconductor substrate, (a)
A memory cell array comprising: a capacitor formed in a trench provided in the substrate; and (b) a transistor formed in the trench and connected to the capacitor. (4) In the memory cell array provided on the substrate, (a
) a plurality of mutually parallel first conductor lines provided on the substrate; (b) a plurality of mutually parallel second conductor lines intersecting with and insulated from the first conductor lines; (c) a plurality of memory cells provided at each intersection of the first and second conductor lines, each of the memory cells being connected to one of the first conductor lines and the second conductor line; a field effect transistor and a capacitor formed in a trench formed in the substrate at a point of intersection with one of the lines, the gate of the transistor being formed by a material inserted into the trench; a source region, a channel region and a drain region are formed in the substrate, the drain region connecting it to one of the first conductor lines;
The gate region connects this to one of the second conductor lines.
A memory cell array characterized in that the source region is connected to the capacitor and the source region is connected to the capacitor. (5) (a) The substrate is made of silicon, and (b)
5. The memory cell array according to claim 4, wherein said first conductor line is formed by an impurity implanted region formed in said substrate. (6) The memory cell array according to claim 5, wherein (a) the source region, channel region, and drain region are formed by a solid phase epitaxial growth method. (7) The memory cell array according to claim 5, wherein (a) the source region, channel region, and drain region are formed by an epitaxial deposition method. (8) In a memory cell provided on a semiconductor substrate, (a)
(b) a charge storage capacitor formed at the bottom of a sidewall of a substantially vertical trench provided in the substrate; and (b) a field effect transistor provided on the sidewall of the trench between the capacitor and the surface of the substrate. the transistor's source connects it to one plate of the capacitor, its drain connects it to a bit line provided substantially on the surface of the substrate, and its gate connects it to a bit line provided substantially on the surface of the substrate. A memory cell array characterized in that the memory cell array is connected to word lines provided substantially on the surface of the memory cell array. (9) (a) The charge storage capacitor includes (i) a first region formed within the sidewall of the trench, and a second region formed within the substrate and adjacent to the first region. (ii) an insulating layer formed on the sidewall in the first region; (iii)
It consists of two parts: a first layer formed on the insulating layer in the trench, and a third region formed in the substrate near the second region and adjacent to the first layer. (b) said transistor comprises a source region thereof, and said second and third regions are of opposite conductivity types to form a junction therebetween; , a channel region and a drain region are all formed in the sidewalls of the trench, a source region is adjacent to the third region, and a gate insulating layer is formed on the sidewalls in the channel region. Claim No. 8
The memory cell array described in . (10) (a) The substrate is made of silicon, and (
9. The memory cell array according to claim 8, wherein: b) a reverse bias is applied to the junction when charge is stored in the capacitor. (11) (a) The carrier concentration in the vicinity of the second region of the first region is much lower than the carrier concentration in a portion separated from the second region. 9. The memory cell array according to item 9. (12) The memory cell array according to claim 9, wherein (a) the first layer has a polycrystalline structure or an amorphous crystalline structure. (13) (a) A patent characterized in that the first layer, at least in the vicinity of the third region, is made of a single crystal formed by solid phase epitaxial growth using the third region as a seed. The memory cell array according to claim 9. (14) The memory cell array according to claim 9, wherein (a) the first layer is formed by an epitaxial vapor deposition method. (15) 1 constructed in a trench formed in a substrate with word lines and bit lines substantially on the surface thereof;
In a transistor/one capacitor memory cell, (2) a gate of the transistor is formed in a layer of a portion of the trench adjacent to the substrate surface and the gate is connected to the word line; a channel region and a drain region are formed on a portion of a sidewall of the trench near the surface of the substrate, and the drain region is formed adjacent to the substrate surface and one of the bit lines. (c) a first plate of the capacitor is disposed within the trench to insulate the first plate from the layer and connect to the source region; and (d) a first plate of the capacitor is connected to the source region. 1. A transistor characterized in that a second electrode plate is formed substantially in one area of the substrate and adjacent to a side wall of the trench, and the second electrode plate is installed through the substrate. /1 capacitor memory cell. (16) In manufacturing a one-transistor/one-capacitor memory cell in a memory cell having a trench formed in a semiconductor substrate, (a) a trench is formed in the substrate, and (b) insulation is provided on the sidewall of the trench. (c) filling the bottom of the trench with a semiconductor material; and (d) forming a field effect transistor in the unfilled portion of the trench and on the sidewalls of the trench, the top of the trench adjacent to the semiconductor material. 1-transistor/1-capacitor, characterized in that the source region of the transistor is formed by partially filling the semiconductor material, and both the semiconductor material and the source region form one plate of the capacitor. A method for manufacturing memory cells.