JPH06236972A - Formation of layer insulating film - Google Patents

Abstract

PURPOSE:To increase an yield by forming a flat layer insulating film and by preventing the breaking of voids in the following high-temperature treatment. CONSTITUTION:After a bit line is formed with a tungsten polycide film 51, an SiO2 film 52 is deposited and then a polycrystalline silicon film 75 is deposited by vacuum CVD. After that, the polycrystalline silicon film 75 is isotropically etched back to fill a recessed section 55 with the polycrystalline silicon film 75. Under this condition, a BPSG film 56 is deposited. Since the polycrystalline silicon film 75 formed by vacuum CVD has an excellent step coverage, the generation of voids can be prevented. Furthermore, when the polycrystalline silicon film 75 is etched back, the SiO2 film 52 serves as a stopper.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film on a wiring when there is a recess having a high aspect ratio on the wiring.

[0002]

2. Description of the Related Art FIG. 4 shows a stacked capacitor DRAM manufactured by using a conventional example of the present invention.
In order to manufacture this stacked capacitor DRAM, as shown in FIG. 5, a thick SiO ₂ film (not shown) is formed on the surface of only the memory cell portion 12 of the Si substrate 11 by the same method as the normal LOCOS method. Is formed first, and this SiO ₂
By removing the film by etching, the Si substrate 11 at the boundary between the memory cell section 12 and the peripheral circuit section 13 is removed.
A step 14 is provided on the surface of the.

Providing the step 14 prevents the memory cell portion 12 from becoming higher than the peripheral circuit portion 13 in a later step if the surface of the Si substrate 11 remains flat, and the focus margin is reduced during lithography exposure. This is because After that, the P well 15 and the like are formed on the Si substrate 11,
The LOCOS method is performed again to form the SiO ₂ film 16 on the surface of the element isolation region of the Si substrate 11, and further form the SiO ₂ film 17 as a gate insulating film on the surface of the element active region.

[0004] Then, a gate electrode made of tungsten polycide film 21 or the like is formed on the SiO ₂ film 17 and 16, the Si substrate 11 by a tungsten polycide film 21 and the SiO ₂ film 16 as a mask N ^- type of The diffusion layer 22 is formed. Then, sidewalls made of the SiO ₂ film 23 are formed on the side surfaces of the tungsten polycide film 21, and the tungsten polycide film 21 and the SiO ₂ films 16 and 23 are used as masks to form N ^{+ on} the Si substrate 11 of only the peripheral circuit section 13. A mold diffusion layer 24 is formed.

Through the steps so far, the access transistor 25 constituting the memory cell is completed in the memory cell section 12, and the LDD structure transistor 26 is formed in the peripheral circuit section 13.
Is completed. After that, the SiO ₂ film, the PSG film, and the reduced pressure CV
The inter-layer insulation film 27 is a composite film with the SiN film deposited by the D method.
To form. Then, a polycrystalline Si film 31 is deposited on the entire surface, and an opening 32 is formed in a portion of the polycrystalline Si film 31 on one diffusion layer 22 of the transistor 25.

After that, a SiO ₂ film 33 is deposited on the entire surface, the entire surface of the SiO ₂ film 33 and the interlayer insulating film 27, etc. are etched back, and the side wall made of the SiO ₂ film 33 is formed on the inner peripheral surface of the opening 32. While being formed, the contact hole 34 reaching the diffusion layer 22 while being surrounded by the side wall is opened in the interlayer insulating film 27 and the like. Therefore, if the size of the opening 32 is set to the limit of lithography, the size of the contact hole 34 can be made smaller than the limit of lithography.

After that, a polycrystalline Si film 35 is deposited on the entire surface so as to contact the diffusion layer 22 through the contact hole 34, and the polycrystalline Si films 31 and 35 are formed on the polycrystalline Si films 31 and 35 by ion implantation or a predeposition method using POCl _3. Introduce N-type impurities. Then, these polycrystalline Si films 31 and 35 are processed into a pattern of the storage node electrode which is the lower electrode of the capacitor.

After that, a dielectric film 36 is formed on the entire surface, and a polycrystalline Si film 37 is deposited on the dielectric film 36. Then, an N-type impurity is introduced into the polycrystalline Si film 37 by a predeposition method using POCl ₃ or the like, and the memory cell portion 12 is removed from the polycrystalline Si film 37 and the dielectric film 36.
The contact portion between the bit line and the diffusion layer 22 and its vicinity are removed.

Thereafter, low pressure CVD using TEOS as a raw material
A SiO ₂ film 41 or the like is deposited to a film thickness of about several tens to 100 nm by a method or the like, and a low melting point glass film such as a BPSG film 42 is further deposited to a film thickness of a few hundred nm by the CVD method. Then, a resist (not shown) is applied, and this resist and B
The PSG film 42 is etched back. At this time, BPS
Since G film 42 is about twice the etch rate as compared to the SiO ₂ film 41, SiO ₂ film 41 is a stopper when etching back the BPSG film 42.

Then, in an N ₂ atmosphere at 800 ° C. or higher, B
By flowing the PSG film 42, the BPS
The G film 42 is embedded in the step portion to perform smoothing. And
The interlayer insulating film 43 is formed of a SiO ₂ film or a PSG film having a film thickness of several hundreds nm.

Thereafter, only the memory cell portion 12 is covered with a resist (not shown), the resist is used as a mask, and the polycrystalline Si film 37 left in the peripheral circuit portion 13 is used as a stopper to contain hydrofluoric acid. The interlayer insulating film 43, the BPSG film 42, and the SiO ₂ film 41 of the peripheral circuit portion 13 are removed by wet etching with a liquid. Then, using the above-mentioned resist or the BPSG film 42 as a mask, polycrystalline Si
The film 37 is also etched. Through the steps up to this point, the capacitor 44 forming the memory cell is completed.

After that, a PSG film, a SiO ₂ film, and a reduced pressure CV
The SiN film deposited by the D method or a combination thereof is used to form the interlayer insulating film 45 having a film thickness of several tens to several hundreds nm. Then, the contact hole 46 reaching the other diffusion layer 22 of the transistor 25, the contact hole 47 reaching the one diffusion layer 24 of the transistor 26, and the like are formed in the interlayer insulating film 4.
Open a hole in 5th grade. Further, a bit line is formed with the tungsten polycide film 51 having a film thickness of about 200 nm.

Next, as shown in FIG. 6, a low pressure CVD method or a high temperature CVD method using TEOS as a raw material is used to deposit a SiO ₂ film 52 having a good step coverage with a thickness of several tens nm. Then, the BPSG film 53 is deposited to a thickness of about 300 nm by the CVD method, and the resist 54 is processed into a pattern that covers only the memory cell portion 12.

Next, the resist 54 is placed in an O ₂ plasma atmosphere.
Anisotropically etch back only. And the resist 5
4 when the BPSG film 53 is exposed, the resist 54
And the BPSG film 53 are switched to the same etching rate, and the resist 54 and the BPSG film 53 are etched back to form a recess 55 on the tungsten polycide film 51 as shown in FIG. The BPSG film 53 is left only in the recess having a high aspect ratio.

Next, after removing the remaining resist 54, as shown in FIG. 8, a low melting point glass film such as a BPSG film 56 is deposited by CVD to a film thickness of several hundred nm, and the transistor 26 is formed. Contact hole 5 reaching the other diffusion layer 24 of
7 etc. are opened in the BPSG film 56 etc. And 850
Smoothing is performed by causing the BPSG film 56 to flow in an N ₂ atmosphere at about 950 ° C.

Next, as shown in FIG. 4, Ti and TiON
The barrier metal film 61 and the Si and Si, the first layer Al wiring composite film of Al film 62 containing Cu or the like is formed consisting of the like, SiO ₂ by a plasma CVD method using TEOS as a raw material
The film 63 is deposited. Then, the SOG film 64 is applied and etched back, and the SiO ₂ film 65 is further deposited by the plasma CVD method using TEOS as a raw material.
Perform the above smoothing.

After that, the PSG film 66 as an interlayer insulating film is formed.
Are deposited by the CVD method, and contact holes 67 and the like reaching the Al film 62 and the like are opened in the PSG film 66 and the like. And Ti
Barrier metal film 71 made of Si, TiON or the like and Si or S
The composite film with the Al film 72 containing i, Cu, etc.
l wiring is formed, and a SiN film 73 as a surface protection film is deposited by a plasma CVD method to a film thickness of about 750 nm,
This stacked capacitor DRAM was completed.

[0018]

By the way, in the above-mentioned conventional example, the tungsten polycide film 5 which is a bit line is used.
The recess 55 on 1 is filled with BPSG films 53 and 56 for smoothing. At present, the BPSG film is made of SiH ₄
It is formed by an atmospheric pressure CVD method using a system gas as a raw material.

However, the BPSG film thus formed does not have good step coverage, and voids 74 may occur in the BPSG films 53 and 56 in the recess 55, as shown in an enlarged view in FIG. The void 74 ruptured during the subsequent high temperature heat treatment, hindering the processing of the upper wiring of the Al film 62 and the like, and reduced the yield of the stacked capacitor DRAM.

[0020]

According to a first aspect of the present invention, there is provided a method of forming an interlayer insulating film, which comprises a step of forming a wiring 51 on a semiconductor substrate 11, and a step of forming the wiring 51 and then a first insulating film 52.
On the entire surface, a step of forming a semiconductor film 75 having a different etching characteristic from that of the first insulating film 52 on the first insulating film 52 by a low pressure CVD method, and the semiconductor film 75 being isotropic. The process further includes a step of physically etching back to fill the recess 55 on the wiring 51 with the semiconductor film 75, and a step of forming the second insulating film 56 on the entire surface after the etch back.

According to a second aspect of the present invention, in the method of forming an interlayer insulating film, the step of forming the wiring 51 on the semiconductor substrate 11 and the wiring 5 are performed.
1 is formed and then the first insulating film 52 is formed on the entire surface, and a semiconductor film 75 having etching characteristics different from that of the first insulating film 52 is formed on the first insulating film 5 by a low pressure CVD method.
2 and the step of forming the mask layer 54 flat on the semiconductor film 75, and the mask layer 54 and the semiconductor film 75 under the condition that the etching rates of the mask layer 54 and the semiconductor film 75 are equal. 75 isotropically etched back to form the recess 55 on the wiring 51 in the semiconductor film 75.
And a step of forming the second insulating film 56 on the entire surface after the etching back.

The method of forming an interlayer insulating film according to claim 3 is the same as the method of forming an interlayer insulating film according to claim 1 or 2, wherein the first insulating film 52 is a SiO ₂ film, and the semiconductor film 75.
Is a polycrystalline Si film or an amorphous Si film.

[0023]

According to the method of forming an interlayer insulating film of claim 1, the reduced pressure C
The semiconductor film 75 formed by the VD method is used to form the recess 55 on the wiring 51.
Since the semiconductor film 75 formed by the low pressure CVD method has good step coverage, it is possible to reliably fill the recess 55 on the wiring 51 with this semiconductor film 75 and prevent the occurrence of the void 74. Further, since the first insulating film 52 serves as an etching stopper when the semiconductor film 75 is etched back, it is possible to prevent the already formed wiring 51 from being simultaneously etched.

In the method for forming an interlayer insulating film according to claim 2, since the mask layer 54 is flattened on the semiconductor film 75 and then the mask layer 54 and the semiconductor film 75 are simultaneously etched back, the number of steps is large. The semiconductor film 75 can more surely fill the recess 55 on the wiring 51 to prevent the generation of the void 74.

In the method for forming an interlayer insulating film according to claim 3, a polycrystalline Si film or an amorphous Si film is used as the semiconductor film 75, and the polycrystalline Si film or the amorphous Si film formed by the low pressure CVD method is used. Has good step coverage. Further, the SiO ₂ film is used as the first insulating film 52, and the etching selection ratio between the SiO ₂ film and the polycrystalline Si film or the amorphous Si film is large.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to manufacture of a stacked capacitor DRAM will be described below with reference to FIGS. The components corresponding to those of the conventional example shown in FIGS.

FIG. 1 shows a stacked capacitor DRAM manufactured in this embodiment. Also in this embodiment, SiO
Until the _2nd film 52 is deposited, the substantially same process as one prior art example shown in FIGS. However, in this embodiment, as shown in FIG. 2, thereafter, a polycrystalline Si film 75 having a film thickness of several hundreds nm is deposited on the entire surface by a low pressure CVD method. It is not necessary to add impurities to this polycrystalline Si film 75. Further, the temperature at which the low pressure CVD method is performed is set to 60
An amorphous Si film may be deposited instead of the polycrystalline Si film 75 at about 0 ° C. or lower.

Next, the entire surface of the polycrystalline Si film 75 is isotropically etched back by using a gas such as SF ₆ and O ₂ to form a recess 55 on the tungsten polycide film 51 as shown in FIG. Polycrystalline Si only in recesses with a high aspect ratio such as
Leave the membrane 75. At this time, since the SiO ₂ film 52 serves as an etching stopper, the tungsten polycide film 51 which is the bit line is not etched. After that, the steps similar to those of the conventional example shown in FIGS. 4 to 9 are executed again to complete the stacked capacitor DRAM shown in FIG.

Comparing the above-described embodiment with the conventional example shown in FIGS. 4 to 9, CVD of the BPSG film 53 in this conventional example, lithography for patterning the resist 54, and etching of only the resist 54 are performed. In this embodiment, as a process corresponding to the five processes of backing, etching back of the resist 54 and the BPSG film 53, and peeling off the remaining resist 54, CVD of the polycrystalline Si film 75 and this polycrystalline Si film 75 are performed. Only two steps of etch back are required, and three steps are reduced. Further, even if only lithography is considered, the number of processes is reduced by one.

In the above-mentioned embodiment, the polycrystalline S
At the time of etching back the i film 75, the resist 54 may be used as in the conventional example shown in FIGS. By doing so, although the number of steps increases, the recess 55 can be more surely filled with the polycrystalline Si film 75.

[0031]

According to the method of forming an interlayer insulating film of claim 1,
Since the recesses on the wiring can be surely filled with the semiconductor film to prevent the generation of voids, a smooth interlayer insulating film can be formed with the second insulating film, and the voids are ruptured by the subsequent high temperature heat treatment. Can be prevented and the yield can be increased.

In the method of forming the interlayer insulating film according to the second aspect, since the recesses on the wiring can be more surely filled with the semiconductor film to prevent the generation of voids, the second insulating film can provide a smoother interlayer insulating film. It is possible to form a film, and it is possible to more reliably prevent the rupture of voids due to the subsequent high-temperature heat treatment and improve the yield.

In the method of forming an interlayer insulating film according to claim 3, the polycrystalline Si film or the amorphous Si film formed by the low pressure CVD method has good step coverage, and the SiO ₂ film and the polycrystalline Si film or Since the etching selection ratio with respect to the crystalline Si film is large, the method for forming an interlayer insulating film according to claim 1 or 2 can be reliably implemented.

[Brief description of drawings]

FIG. 1 is a side sectional view of a stacked capacitor DRAM manufactured by using an embodiment of the present invention.

FIG. 2 is a side sectional view showing a first half process of one embodiment.

FIG. 3 is a side sectional view showing a step that follows FIG.

FIG. 4 is a side sectional view of a stacked capacitor DRAM manufactured by using a conventional example of the present invention.

FIG. 5 is a side sectional view showing an initial process for manufacturing the stacked capacitor DRAM shown in FIG.

FIG. 6 is a side sectional view showing a step that follows FIG.

7 is a side sectional view showing a step that follows FIG.

8 is a side sectional view showing a step that follows FIG. 7. FIG.

FIG. 9 is a side sectional view showing a problem in a conventional example.

[Explanation of symbols]

11 Si substrate 51 Tungsten polycide film 52 SiO ₂ film 54 Resist 55 Recessed portion 56 BPSG film 74 Void 75 Polycrystalline Si film

Claims (3)

[Claims] 1. A step of forming a wiring on a semiconductor substrate, a step of forming a first insulating film on the entire surface after forming the wiring, and a semiconductor film having etching characteristics different from those of the first insulating film. On the first insulating film by a low pressure CVD method, isotropically etching back the semiconductor film to fill the recesses on the wiring with the semiconductor film, and after the etching back. And a step of forming a second insulating film on the entire surface, the method of forming an interlayer insulating film. 2. A step of forming a wiring on a semiconductor substrate, a step of forming a first insulating film on the entire surface after forming the wiring, and a semiconductor film having etching characteristics different from those of the first insulating film. Are formed on the first insulating film by a low pressure CVD method, a step of forming a mask layer flat on the semiconductor film, and a step of forming the mask layer and the semiconductor film under the same etching rate. And a step of isotropically etching back the mask layer and the semiconductor film to fill the recesses on the wiring with the semiconductor film, and a step of forming a second insulating film over the entire surface after the etching back. A method for forming an interlayer insulating film, comprising: 3. The first insulating film is a SiO ₂ film,
3. The method for forming an interlayer insulating film according to claim 1, wherein the semiconductor film is a polycrystalline Si film or an amorphous Si film.