JP3065395B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3065395B2 JP3065395B2 JP3257328A JP25732891A JP3065395B2 JP 3065395 B2 JP3065395 B2 JP 3065395B2 JP 3257328 A JP3257328 A JP 3257328A JP 25732891 A JP25732891 A JP 25732891A JP 3065395 B2 JP3065395 B2 JP 3065395B2
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- film
- semiconductor device
- insulating film
- shallow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子の製造方法
に係り、特に半導体素子におけるコンタクト孔埋め込み
配線に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wiring having a contact hole embedded in a semiconductor device.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
以下に示すようなものがあった。図２はかかる従来の半
導体素子の断面図である。まず、ＩＣ基板１上に素子分
離のための絶縁膜２（例えばＳｉＯ2 ）、拡散層３を形
成した後、絶縁膜４（例えばＢＰＳＧ）をＣＶＤ法にて
形成する。その後、コンタクトとなる開孔部５を形成
し、その後、配線となるＡｌ−Ｓｉ系合金膜６をスパッ
タ法で形成し、配線パターンをホトリソエッチングで得
る。これによって半導体素子が完成する。2. Description of the Related Art Conventionally, techniques in such a field include:
There were the following. FIG. 2 is a sectional view of such a conventional semiconductor device. First, after an insulating film 2 (for example, SiO 2 ) for element isolation and a diffusion layer 3 are formed on an IC substrate 1, an insulating film 4 (for example, BPSG) is formed by a CVD method. Thereafter, an opening 5 serving as a contact is formed, and thereafter, an Al-Si alloy film 6 serving as a wiring is formed by a sputtering method, and a wiring pattern is obtained by photolithography. Thereby, the semiconductor element is completed.
【０００３】しかしながら、集積度が増加するにつれて
コンタクト開孔部５の径は小さくなり、アスペクト比
（径と深さの比）が大きくなる。従来の方法ではＡｌ−
Ｓｉ系合金膜６のステップカバレージが悪くなり、断線
となる。そのためコンタクト孔内部を金属で埋め込む技
術が開発されてきている。その１つの方法である選択Ｗ
（タングステン）ＣＶＤ法を図３を用いて説明する。However, as the degree of integration increases, the diameter of the contact opening 5 decreases, and the aspect ratio (the ratio of diameter to depth) increases. In the conventional method, Al-
The step coverage of the Si-based alloy film 6 deteriorates, resulting in disconnection. Therefore, a technique for embedding the inside of the contact hole with a metal has been developed. One method, selection W
The (tungsten) CVD method will be described with reference to FIG.
【０００４】図３において、ＩＣ基板１１に先程と同様
に素子分離絶縁膜１２、拡散層１３を形成した後、絶縁
膜１４を形成しコンタクトとなる開孔部１５を形成す
る。そして、選択ＷＣＶＤ法により、Ｗ（タングステ
ン）膜１６を開孔部１５と絶縁膜１４の段差が生じない
程度に形成する。その後、Ａｌ−Ｓｉ系合金膜１７をス
パッタ法で形成し、ホトリソエッチングによりパターニ
ングする。In FIG. 3, an element isolation insulating film 12 and a diffusion layer 13 are formed on an IC substrate 11 in the same manner as described above, and then an insulating film 14 is formed to form a hole 15 serving as a contact. Then, a W (tungsten) film 16 is formed by a selective WCVD method to such an extent that a step between the opening 15 and the insulating film 14 does not occur. Thereafter, an Al-Si based alloy film 17 is formed by a sputtering method, and is patterned by photolithography.
【０００５】この方法によれば、コンタクト孔内を金属
で埋め込むため、ステップカバレージの悪化による断線
を防ぐことができ、信頼性の高い配線構造を得ることが
できる。According to this method, since the inside of the contact hole is buried with metal, disconnection due to deterioration of step coverage can be prevented, and a highly reliable wiring structure can be obtained.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、実際に
用いられる半導体素子コンタクト孔は、図４に示すよう
に、拡散層２３上だけではなく電極層２５上にも存在す
る。そのため各層上のコンタクト孔２６、コンタクト孔
２７を同時に選択ＷＣＶＤ法でＷ膜２８、Ｗ膜２９を形
成することになる。この２種類のコンタクト孔２６、コ
ンタクト孔２７はコンタクト孔２７の方が浅いため、埋
め込まれるＷ膜２９の厚さはコンタクト孔２７における
絶縁膜２４と段差が生じない程度に抑えなければならな
い。それにより深い方のコンタクト孔２６内のＷ膜２８
の厚さはＷ膜２９と同じであるため、コンタクト孔２６
は完全に埋め込まれておらず、配線層となるＡＬ−Ｓｉ
系合金膜３０をスパッタ法で形成する際、ステップカバ
レージの悪化により、コンタクト孔２６内では断線する
可能性がある。However, as shown in FIG. 4, the semiconductor element contact holes actually used exist not only on the diffusion layer 23 but also on the electrode layer 25. Therefore, the contact holes 26 and contact holes 27 on each layer are simultaneously selected, and the W film 28 and the W film 29 are formed by the WCVD method. Since the two types of contact holes 26 and 27 are shallower in the contact hole 27, the thickness of the W film 29 to be buried must be suppressed to such an extent that no step is formed between the contact hole 27 and the insulating film 24. Thereby, the W film 28 in the deeper contact hole 26 is formed.
Since the thickness of the contact hole 26 is the same as that of the W film 29,
Is not completely buried, and AL-Si becomes a wiring layer
When the system alloy film 30 is formed by the sputtering method, there is a possibility that the contact hole 26 may be disconnected due to deterioration of step coverage.
【０００７】また、前記ステップカバレージを良くする
ためにコンタクト孔２６のＷ膜２８の膜厚を厚くする
と、コンタクト孔２７でのＷ膜２９が絶縁膜２４よりあ
ふれ、上方及び左右へＷ膜が成長するため、平坦性及び
層内ショートという問題が発生する。このため、深さの
異なるコンタクト孔への選択ＷＣＶＤ法は技術的に満足
できるものは得られなかった。If the thickness of the W film 28 in the contact hole 26 is increased in order to improve the step coverage, the W film 29 in the contact hole 27 overflows the insulating film 24, and the W film grows upward and left and right. Therefore, problems such as flatness and short-circuit in the layer occur. Therefore, the selective WCVD method for contact holes having different depths could not be technically satisfactory.
【０００８】本発明は、深さの異なるコンタクト孔に選
択ＷＣＶＤ法を用いる際、浅いコンタクト孔を埋め込ん
でも、深いコンタクト孔は完全に埋め込むことができな
いために配線層となるＡｌ−Ｓｉ系合金膜をスパッタす
る際、ステップカバレージ悪化による断線が生じるとい
う問題点を除去するため、深いコンタクト孔、浅いコン
タクト孔両方とも断線のない良好な半導体素子の製造方
法を提供することを目的とする。According to the present invention, when a selective WCVD method is used for contact holes having different depths, even if a shallow contact hole is buried, a deep contact hole cannot be completely buried. It is an object of the present invention to provide a good method for manufacturing a semiconductor device in which both deep and shallow contact holes have no disconnection in order to eliminate the problem that disconnection occurs due to deterioration of step coverage when sputtering is performed.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するために、基板上に層間絶縁膜を形成し、前記層間
絶縁膜に浅いコンタクト孔と深いコンタクト孔の深さの
異なるコンタクト孔を有する半導体素子の製造方法にお
いて、前記浅いコンタクト孔の径は深いコンタクト孔の
径よりも小さく形成する工程と、これらのコンタクト孔
を選択ＷＣＶＤ法にて同時にＷ膜で埋め込んだ後に、配
線層を形成する工程とを施すようにしたものである。According to the present invention, in order to achieve the above object, an interlayer insulating film is formed on a substrate, and a contact hole having a different depth from a shallow contact hole and a deep contact hole is formed in the interlayer insulating film. The step of forming the diameter of the shallow contact hole smaller than the diameter of the deep contact hole, and disposing these contact holes simultaneously with a W film by a selective WCVD method.
And a step of forming a line layer .
【００１０】[0010]
【作用】本発明によれば、上記したように、深さの異な
るコンタクト孔を有する半導体素子において、浅いコン
タクトの径を深いコンタクト孔に比べて小さく形成し、
同じ時間で深いコンタクト孔と浅いコンタクト孔を同時
に選択ＷＣＶＤ法にて同時にＷ膜で埋め込んだ後に、配
線となるＡｌ−Ｓｉ系合金膜を形成して深いコンタクト
孔、浅いコンタクト孔それぞれの導通をとるようにした
ものである。According to the present invention, as described above, in a semiconductor device having contact holes having different depths, the diameter of a shallow contact is formed smaller than that of a deep contact hole.
At the same time, a deep contact hole and a shallow contact hole are simultaneously buried with a W film by a selective WCVD method. Then , an Al-Si alloy film to be a wiring is formed to conduct the deep contact hole and the shallow contact hole. It is like that.
【００１１】[0011]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の実施例を示す半
導体素子の製造工程断面図である。まず、図１（ａ）に
示すように、Ｓｉ基板３１に素子分離のための絶縁膜３
２（例えば、ＳｉＯ2 ）を形成し、拡散層３３を形成し
た後、第１の層間絶縁膜３４（例えば、ＢＰＳＧ）をＣ
ＶＤ法にて５０００Å形成する。その後平坦化させる熱
処理を行なう。熱処理はＮ2 雰囲気で９５０℃で１５分
行なう。平坦になった後、電極となるＷポリサイド膜３
５を形成する。作成方法は次に示す様である。まず、ポ
リシリコン膜をＣＶＤ法にて１０００〜１５００Å形成
する。その後ドーパントとなる不純物をポリシリコンに
含ませる。ここではリンのイオン注入を行なう。条件は
４０ｋｅｖ，１×１０16ｉｏｎｓ／ｃｍ2 である。そし
て、ＷＳｉｘ膜をスパッタにて１５００Å形成し、前述
のポリシリコン層／ＷＳｉ層をホトリソ、エッチングで
パターニングする。そして、第２の層間絶縁膜３６（例
えば、ＢＰＳＧ）をＣＶＤ法にて５０００Å形成し、平
坦にさせるフロー熱処理を行なう。熱処理条件は、Ｎ2
雰囲気で９５０℃で１５分行なう。この熱処理によって
前述のポリシリコン層／ＷＳｉ層はＷポリサイド膜３５
となる。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1A, an insulating film 3 for element isolation is formed on a Si substrate 31.
2 (eg, SiO 2 ) and the diffusion layer 33 are formed, and then the first interlayer insulating film 34 (eg, BPSG) is
It is formed at 5000 ° by the VD method. Thereafter, heat treatment for planarization is performed. The heat treatment is performed at 950 ° C. for 15 minutes in an N 2 atmosphere. After flattening, W polycide film 3 to be an electrode
5 is formed. The creation method is as follows. First, a polysilicon film is formed at 1000 to 1500 ° by a CVD method. After that, an impurity serving as a dopant is included in the polysilicon. Here, phosphorus ion implantation is performed. The conditions are 40 keV, 1 × 10 16 ions / cm 2 . Then, a WSix film is formed at 1500 ° by sputtering, and the aforementioned polysilicon layer / WSi layer is patterned by photolithography and etching. Then, a second interlayer insulating film 36 (for example, BPSG) is formed at 5000.degree. The heat treatment condition is N 2
Perform at 950 ° C. for 15 minutes in an atmosphere. By this heat treatment, the aforementioned polysilicon layer / WSi layer becomes the W polycide film 35.
Becomes
【００１２】その後、図１（ｂ）に示すように、ホトリ
ソ、エッチングにより拡散層３３上及びＷポリサイド膜
３５上にコンタクト孔３７（例えば、直径１μｍ〜２μ
ｍ）、コンタクト孔３８（例えば、コンタクト孔３７の
直径の１／２〜１／４以下）を形成する。コンタクト孔
のエッチングは、ＣＦ4 ／ＣＨＦ3 、流量比を１．０、
圧力１Ｔｏｒｒ、ＲＦパワー７５０Ｗで行なう。この時
に、Ｗポリサイド層３５上の浅いコンタクト孔３８の径
は、深いコンタクト孔３７に比べてかなり小さくする。
つまり、１／２〜１／４以下にする。更に、コンタクト
抵抗の低減を図るために、Ｗポリサイド膜３５上に形成
されるコンタクト孔３７は複数個形成するのが望まし
い。Thereafter, as shown in FIG. 1B, contact holes 37 (for example, having a diameter of 1 μm to 2 μm) are formed on the diffusion layer 33 and the W polycide film 35 by photolithography and etching.
m), a contact hole 38 (for example, 1/2 to 1/4 or less of the diameter of the contact hole 37) is formed. Etching of the contact hole is performed using CF 4 / CHF 3 , a flow ratio of 1.0,
The operation is performed at a pressure of 1 Torr and an RF power of 750 W. At this time, the diameter of the shallow contact hole 38 on the W polycide layer 35 is considerably smaller than that of the deep contact hole 37.
That is, it is set to 1/2 to 1/4 or less. Further, it is desirable to form a plurality of contact holes 37 formed on the W polycide film 35 in order to reduce the contact resistance.
【００１３】その後、選択ＷＣＶＤ法により、Ｗ膜３９
を深いコンタクト孔３７内に第２の層間絶縁膜３６と段
差が生じない程度に形成する。この時、浅い複数個のコ
ンタクト孔３８は、コンタクト径がかなり小さいため、
反応ガス交換がスムーズに行なわれず、Ｗ膜の成長速度
が遅く、深いコンタクト孔３７が埋め込まれる時間でＷ
膜４０が埋め込まれることになる。Thereafter, a W film 39 is formed by a selective WCVD method.
Is formed in the deep contact hole 37 to such an extent that a step does not occur with respect to the second interlayer insulating film 36. At this time, the plurality of shallow contact holes 38 have a considerably small contact diameter.
The reaction gas exchange is not performed smoothly, the growth rate of the W film is low, and the W
The film 40 will be embedded.
【００１４】その後、図１（ｃ）に示すように、配線層
となるＡｌ−Ｓｉ系合金膜４１をスパッタ法にて６００
０Å形成する。そして、ホトリソエッチングを行ない、
配線パターンを得る。また、浅いコンタクト孔３８での
コンタクト抵抗は、コンタクト孔を複数個設置してある
ので、通常の大きさのものと変わらない。なお、本発明
は上記実施例に限定されるものではなく、本発明の趣旨
に基づいて種々の変形が可能であり、これらを本発明の
範囲から排除するものではない。Thereafter, as shown in FIG. 1C, an Al—Si alloy film 41 serving as a wiring layer is
0 ° is formed. Then, perform photolithography etching,
Obtain a wiring pattern. In addition, the contact resistance in the shallow contact hole 38 is not different from that of a normal size because a plurality of contact holes are provided. It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.
【００１５】[0015]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、浅いコンタクトの径を深いコンタクト孔に比べ
てかなり小さくし、選択ＷＣＶＤにおけるＷの堆積レー
トが遅くなるようにして形成するようにしたので、深い
コンタクト孔が埋められる時間で浅いコンタクト孔が埋
められるようになり、従来のプロセスを変えることな
く、深いコンタクト孔と浅いコンタクト孔を同時にＷ膜
で埋め込むことができる。As described in detail above, according to the present invention, the diameter of a shallow contact is made considerably smaller than that of a deep contact hole, and the deposition rate of W in selective WCVD is reduced. As a result, the shallow contact hole can be filled with the time required for filling the deep contact hole, and the deep contact hole and the shallow contact hole can be simultaneously filled with the W film without changing the conventional process.
【００１６】したがって、深いコンタクト孔でのスパッ
タＡｌ−Ｓｉ系合金膜のステップカバレージの悪化はな
くなる。また、コンタクト孔形成時のエッチング工程に
おいても、浅いコンタクト孔では径が小さくなっている
ために、マイクロローディング効果によりエッチングレ
ートが遅くなり、深いコンタクト孔が開孔するまでの時
間での下地Ｗポリサイド層のオーバーエッチング時間が
抑えられ、損傷も抑えられる。これにより断線のない良
好な半導体素子の実現が可能となる。Therefore, deterioration of the step coverage of the sputtered Al-Si alloy film in the deep contact hole is eliminated. Also, in the etching process at the time of forming the contact hole, since the diameter is small in the shallow contact hole, the etching rate is slowed down by the microloading effect, and the base W polycide in the time until the deep contact hole is opened. Over-etching time of the layer is reduced and damage is also reduced. As a result, a good semiconductor element without disconnection can be realized.
【図１】本発明の実施例を示す半導体素子の製造工程断
面図である。FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体素子の断面図である。FIG. 2 is a sectional view of a conventional semiconductor device.
【図３】従来の他の半導体素子の断面図である。FIG. 3 is a cross-sectional view of another conventional semiconductor device.
【図４】従来技術の問題点説明図である。FIG. 4 is an explanatory diagram of a problem in the related art.
３１ Ｓｉ基板 ３２ 絶縁膜 ３３ 拡散層 ３４ 第１の層間絶縁膜 ３５ Ｗポリサイド膜 ３６ 第２の層間絶縁膜 ３７、３８ コンタクト孔 ３９，４０ Ｗ膜 ４１ Ａｌ−Ｓｉ系合金膜 31 Si substrate 32 Insulating film 33 Diffusion layer 34 First interlayer insulating film 35 W polycide film 36 Second interlayer insulating film 37, 38 Contact hole 39, 40 W film 41 Al-Si based alloy film
Claims (1)
絶縁膜に浅いコンタクト孔と深いコンタクト孔の深さの
異なるコンタクト孔を有する半導体素子の製造方法にお
いて、 （ａ）前記浅いコンタクト孔の径は深いコンタクト孔の
径よりも小さく形成する工程と、 （ｂ）これらのコンタクト孔を選択ＷＣＶＤ法にて同時
にＷ膜で埋め込んだ後に、配線層を形成する工程とを施
すことを特徴とする半導体素子の製造方法。1. A method of manufacturing a semiconductor device having an interlayer insulating film formed on a substrate and having a shallow contact hole and a deep contact hole having different depths in the interlayer insulating film, wherein: (a) the shallow contact hole; (B) forming these contact holes at the same time by selective WCVD.
Forming a wiring layer after the semiconductor device is embedded with a W film .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3257328A JP3065395B2 (en) | 1991-10-04 | 1991-10-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3257328A JP3065395B2 (en) | 1991-10-04 | 1991-10-04 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05251569A JPH05251569A (en) | 1993-09-28 |
| JP3065395B2 true JP3065395B2 (en) | 2000-07-17 |
Family
ID=17304839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3257328A Expired - Fee Related JP3065395B2 (en) | 1991-10-04 | 1991-10-04 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3065395B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998035308A1 (en) * | 1997-02-11 | 1998-08-13 | Lsi Logic Corporation | Modular cell placement system |
| KR100463594B1 (en) * | 2002-11-09 | 2004-12-29 | 엘지.필립스 엘시디 주식회사 | A X-ray detector and a method for fabricating thereof |
| JP7069605B2 (en) * | 2017-08-29 | 2022-05-18 | 富士電機株式会社 | Manufacturing method of semiconductor device |
-
1991
- 1991-10-04 JP JP3257328A patent/JP3065395B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05251569A (en) | 1993-09-28 |
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