JPH07147321A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07147321A JPH07147321A JP29649393A JP29649393A JPH07147321A JP H07147321 A JPH07147321 A JP H07147321A JP 29649393 A JP29649393 A JP 29649393A JP 29649393 A JP29649393 A JP 29649393A JP H07147321 A JPH07147321 A JP H07147321A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact holes
- conductor film
- conductor
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にコンタクト孔を充填する導電体膜の形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a conductor film filling a contact hole.
【0002】[0002]
【従来の技術】半導体装置の微細化が進むにつれて、配
線層が多層化されている。これに伴ない、異なる配線層
を接続するためのコンタクト孔の種類も増え、かつ、こ
れらのコンタクト孔の口径もそれぞれ小さくなってい
る。これらのコンタクト孔内にスパッタリングのみによ
り導電体膜を充填することは、困難である。この傾向に
対する製造工程の短縮,製造原価の低減の1つとして、
上層の配線層(例えば第3層)から異なる種類の下層の
配線層(例えば第1,および第2層の配線層)への深さ
の異なる(例えば2種類の)コンタクト孔を形成し、こ
れらのコンタクト孔に同時に導電体膜を充填する種々の
方法が提案されている。これらの方法の1つが、特開平
2−308524号公報に開示されている。2. Description of the Related Art As semiconductor devices have been miniaturized, wiring layers have become multi-layered. Along with this, the types of contact holes for connecting different wiring layers are increasing, and the diameters of these contact holes are decreasing. It is difficult to fill the conductive film in these contact holes only by sputtering. As one of the shortening of the manufacturing process and the reduction of manufacturing cost against this tendency,
Forming contact holes having different depths (for example, two types) from upper wiring layers (for example, third layer) to different types of lower wiring layers (for example, first and second wiring layers), and Various methods have been proposed for simultaneously filling the contact holes with the conductor film. One of these methods is disclosed in JP-A-2-308524.
【0003】半導体装置の製造工程の断面図である図3
を参照すると、上記公開公報記載の製造方法は、以下の
ようになっている。まず、半導体基板1表面にゲート酸
化膜2を形成し、ゲート酸化膜2上にゲート電極15を
形成した後、ゲート電極15の側壁に絶縁膜スペーサ3
を形成する。半導体基板1表面に拡散層4を形成した
後、全面に層間絶縁膜6を形成する。次に、公知のフォ
トリソグラフィ技術により、拡散層4に達する深さの深
いコンタクト孔17を層間絶縁膜6に形成する〔図3
(a)〕。次に、減圧CVD法により、全面に多結晶シ
リコン膜を形成する。この多結晶シリコン膜を異方性エ
ッチングすることにより、上記コンタクト孔17の側壁
に多結晶シリコン膜スペーサ12を形成する〔図3
(b)〕。続いて、ゲート電極15に達する深さの浅い
コンタクト孔18を形成する〔図3(c)〕。次に、タ
ングステンの選択CVD法により、コンタクト孔17,
18をそれぞれタングステン膜20により充填する〔図
3(d)〕。FIG. 3 is a sectional view of a manufacturing process of a semiconductor device.
With reference to, the manufacturing method described in the above publication is as follows. First, the gate oxide film 2 is formed on the surface of the semiconductor substrate 1, the gate electrode 15 is formed on the gate oxide film 2, and then the insulating film spacer 3 is formed on the sidewall of the gate electrode 15.
To form. After forming the diffusion layer 4 on the surface of the semiconductor substrate 1, the interlayer insulating film 6 is formed on the entire surface. Next, a contact hole 17 having a depth reaching the diffusion layer 4 is formed in the interlayer insulating film 6 by a known photolithography technique [FIG.
(A)]. Next, a polycrystalline silicon film is formed on the entire surface by the low pressure CVD method. By anisotropically etching this polycrystalline silicon film, a polycrystalline silicon film spacer 12 is formed on the side wall of the contact hole 17 [FIG.
(B)]. Then, a contact hole 18 having a depth reaching the gate electrode 15 is formed [FIG. 3 (c)]. Next, the contact hole 17,
Each 18 is filled with a tungsten film 20 [FIG. 3 (d)].
【0004】[0004]
【発明が解決しようとする課題】上記公開公報記載の半
導体装置の製造方法は、深さの深いコンタクト孔の側壁
にのみ第1の導電体膜からなるスペーサを形成しておく
ことにより、このコンタクト孔への第2の導電体膜の選
択成長の時間を短縮する。その結果として、深さの異な
るコンタクト孔に、同時に第2の導電体膜を充填するこ
とが可能であるとしている。しかしながら、現実の半導
体装置では、さまざまな深さのコンタクト孔が存在する
ため、深さの異なる全てのコンタクト孔を同時に第2の
導電体膜で充填することは、極めて困難である。そのた
め、これらのコンタクト孔に接続する上層の配線が、こ
れらのコンタクト孔の上端近傍で断線しやすくなる。ま
たこの方法では、コンタクト孔の開口を2度に分けて行
なうため、フォトリソグラフィ工程の回数が増大し、製
造工期が長くなるという問題もある。In the method of manufacturing a semiconductor device described in the above-mentioned publication, the spacer made of the first conductor film is formed only on the side wall of the deep contact hole to form the contact. The time for selective growth of the second conductor film in the holes is shortened. As a result, it is possible to simultaneously fill the contact holes having different depths with the second conductor film. However, in an actual semiconductor device, since contact holes having various depths exist, it is extremely difficult to simultaneously fill all the contact holes having different depths with the second conductor film. Therefore, the upper layer wirings connected to these contact holes are easily broken near the upper ends of these contact holes. Further, in this method, since the contact holes are opened twice, there is a problem that the number of photolithography steps is increased and the manufacturing period is prolonged.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法の第1の態様は、半導体基板の表面からの上面の
高さがそれぞれ異なる複数の種類の配線層を形成し、全
面に層間絶縁膜を形成し、口径が同じでこれらの配線層
の上面に達する深さの異なる複数の種類のコンタクト孔
をこの層間絶縁膜に形成する工程と、全面に第1導電体
膜を形成し、この第1導電体膜を異方性エッチングして
上記層間絶縁膜の上面から所定の深さより下方のそれぞ
れの上記コンタクト孔の側壁にこの第1導電体膜からな
るスペーサを形成する工程と、第2導電体膜の選択成長
を行ない、それぞれの上記コンタクト孔をこの第2導電
体膜で充填する工程とを有する。According to a first aspect of a method for manufacturing a semiconductor device of the present invention, a plurality of types of wiring layers having different heights from the surface of a semiconductor substrate are formed, and an interlayer is formed over the entire surface. A step of forming an insulating film, forming a plurality of types of contact holes having the same diameter and different depths reaching the upper surfaces of these wiring layers in this interlayer insulating film, and forming a first conductor film on the entire surface, Anisotropically etching the first conductor film to form spacers made of the first conductor film on the sidewalls of the contact holes below a predetermined depth from the upper surface of the interlayer insulating film; And a step of selectively growing the two conductor films and filling each of the contact holes with the second conductor film.
【0006】本発明の半導体装置の製造方法の第2の態
様は、半導体基板の表面からの上面の高さがそれぞれ異
なる複数の種類の配線層を形成し、全面に層間絶縁膜を
形成し、口径が同じでこれらの配線層の上面に達する深
さの異なる複数の種類のコンタクト孔をこの層間絶縁膜
に形成する工程と、全面に第1導電体膜を形成し、それ
ぞれの上記コンタクト孔が充填されるまで全面に第2導
電体膜を成長する工程と、上記第2導電体膜および上記
第1導電体膜を異方性エッチングによりエッチバックし
て、それぞれの上記コンタクト孔における上記層間絶縁
膜の上面から所定の深さまでのこの第1導電体膜を除去
する工程と、第3導電体膜の選択成長を行ない、それぞ
れの上記コンタクト孔をこの第3導電体膜と上記第2導
電体膜とで充填する工程とを有する。好ましくは、上記
第1導電体膜がチタン膜と窒化チタン膜との積層膜から
なり、上記第2,および第3導電体膜がタングステン膜
からなる。According to a second aspect of the method for manufacturing a semiconductor device of the present invention, a plurality of types of wiring layers having different heights from the surface of the semiconductor substrate are formed, and an interlayer insulating film is formed on the entire surface. A step of forming a plurality of types of contact holes having the same diameter and different depths reaching the upper surfaces of these wiring layers in the interlayer insulating film; and forming a first conductor film on the entire surface, A step of growing a second conductor film on the entire surface until it is filled, and etching back the second conductor film and the first conductor film by anisotropic etching to obtain the interlayer insulation in each of the contact holes. The step of removing the first conductor film from the upper surface of the film to a predetermined depth and the selective growth of the third conductor film are performed, and the contact holes are formed in the third conductor film and the second conductor, respectively. Fill with membrane And a step. Preferably, the first conductor film is a laminated film of a titanium film and a titanium nitride film, and the second and third conductor films are a tungsten film.
【0007】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0008】半導体装置の製造工程の断面図である図1
を参照すると、本発明の第1の実施例は、以下のように
なっている。FIG. 1 is a sectional view of a manufacturing process of a semiconductor device.
Referring to, the first embodiment of the present invention is as follows.
【0009】まず、P型の半導体基板1表面にゲート酸
化膜2を形成し、ゲート酸化膜2上にポリサイドゲート
電極5を形成した後、ポリサイドゲート電極5の側壁に
絶縁膜スペーサ3を形成する。半導体基板1表面にN型
の拡散層4を形成した後、全面に層間絶縁膜6を形成す
る。次に、公知のフォトリソグラフィ技術により、拡散
層4に達する深さの深いコンタクト孔7と、ポリサイド
ゲート電極5に達する深さの浅いコンタクト孔8とを層
間絶縁膜6に同時に形成する。コンタクト孔7の口径
は、コンタクト孔8の口径と同じである〔図1
(a)〕。First, a gate oxide film 2 is formed on the surface of a P-type semiconductor substrate 1, a polycide gate electrode 5 is formed on the gate oxide film 2, and then an insulating film spacer 3 is formed on a sidewall of the polycide gate electrode 5. Form. After the N type diffusion layer 4 is formed on the surface of the semiconductor substrate 1, the interlayer insulating film 6 is formed on the entire surface. Next, a well-known photolithography technique is used to simultaneously form a deep contact hole 7 reaching the diffusion layer 4 and a shallow contact hole 8 reaching the polycide gate electrode 5 in the interlayer insulating film 6. The diameter of the contact hole 7 is the same as the diameter of the contact hole 8 [Fig.
(A)].
【0010】次に、PH3 ,SiH4 ガスを用いた温度
500〜600℃,圧力60〜100Paの減圧CVD
法により、全面に第1導電膜であるリンドープド多結晶
シリコン膜9を堆積する。このリンドープド多結晶シリ
コン膜9の膜厚は、コンタクト孔7,8の口径に比べて
薄く、所望の薄さになっている〔図1(b)〕。Next, low pressure CVD using PH 3 and SiH 4 gas at a temperature of 500 to 600 ° C. and a pressure of 60 to 100 Pa.
By the method, the phosphorus-doped polycrystalline silicon film 9 which is the first conductive film is deposited on the entire surface. The film thickness of the phosphorus-doped polycrystalline silicon film 9 is smaller than the diameters of the contact holes 7 and 8 and has a desired thickness [FIG. 1 (b)].
【0011】続いて、流量比0.3〜0.4のHBr/
Cl2 ガスを用いた圧力50〜70Pa,パワー200
〜300Wでのプラズマ異方性エッチングを行ない、コ
ンタクト孔7,8の側壁にのみに、それぞれリンドープ
ド多結晶シリコン膜スペーサ9aを残置させる。これら
リンドープド多結晶シリコン膜スペーサ9aの上端は層
間絶縁膜6の上面(コンタクト孔7,8の上端)より低
い。この間隔は所定の値であり、この値はコンタクト孔
7,8の口径の1/2であることが好ましい。上記エッ
チングにおいて、層間絶縁膜6上面のリンドープド多結
晶シリコン膜9が除去された後、さらに所定の時間この
エッチングを続行するすることにより、上記形状のリン
ドープド多結晶シリコン膜スペーサ9aが得られる〔図
1(c)〕。Subsequently, HBr / with a flow rate ratio of 0.3 to 0.4
Pressure of 50 to 70 Pa using Cl 2 gas, power of 200
Plasma anisotropic etching is performed at .about.300 W to leave the phosphorus-doped polycrystalline silicon film spacers 9a only on the sidewalls of the contact holes 7 and 8, respectively. The upper ends of the phosphorus-doped polycrystalline silicon film spacers 9a are lower than the upper surface of the interlayer insulating film 6 (upper ends of the contact holes 7 and 8). This interval is a predetermined value, and this value is preferably 1/2 of the diameter of the contact holes 7 and 8. In the above etching, after the phosphorus-doped polycrystalline silicon film 9 on the upper surface of the interlayer insulating film 6 is removed, the etching is continued for a further predetermined time to obtain the phosphorus-doped polycrystalline silicon film spacer 9a having the above-described shape [Fig. 1 (c)].
【0012】次に、流量比1〜2のWF6 /SiH4 ガ
スを用いた温度200〜300℃,圧力0.1〜0.3
Paのタングステンの選択CVD法により、コンタクト
孔7,8内をそれぞれ第2導電体膜であるタングステン
膜10Aにより充填する。このタングステン膜10A
は、それぞれのコンタクト孔7,8の底面とリンドープ
ド多結晶シリコン膜スペーサ9aの表面とからほぼ同じ
成長速度で成長する。コンタクト孔7,8の口径が等し
く,リンドープド多結晶シリコン膜スペーサ9aの上端
が上述のようになっている場合には、タングステン膜1
0Aが成長してそれぞれのコンタクト孔7,8の上端に
到達するのは、ほぼ同時である。このとき、タングステ
ン膜10Aの上面は、それぞれ概ね平坦になっている
〔図1(d)〕。なお、リンドープド多結晶シリコン膜
スペーサ9aの上端とコンタクト孔7,8の上端とが一
致している場合には、これらの上端においても、タング
ステン膜10Aは成長初期の段階から成長するため、最
終的なタングステン膜10Aの上面が層間絶縁膜6の上
面より突出した形状になり、後工程での上層の配線の形
成に支障をきたすことになる。Next, using WF 6 / SiH 4 gas with a flow rate ratio of 1 to 2, the temperature is 200 to 300 ° C., and the pressure is 0.1 to 0.3.
The contact holes 7 and 8 are filled with the tungsten film 10A that is the second conductor film by the selective CVD method of tungsten of Pa. This tungsten film 10A
Grow at substantially the same growth rate from the bottom surfaces of the contact holes 7 and 8 and the surface of the phosphorus-doped polycrystalline silicon film spacer 9a. If the diameters of the contact holes 7 and 8 are equal and the upper end of the phosphorus-doped polycrystalline silicon film spacer 9a is as described above, the tungsten film 1
It is almost the same time that 0A grows and reaches the upper ends of the respective contact holes 7 and 8. At this time, the upper surfaces of the tungsten films 10A are substantially flat [FIG. 1 (d)]. When the upper end of the phosphorus-doped polycrystalline silicon film spacer 9a and the upper ends of the contact holes 7 and 8 are aligned with each other, the tungsten film 10A also grows from these initial stages even at these upper ends. The upper surface of the tungsten film 10A has a shape protruding from the upper surface of the interlayer insulating film 6, which hinders the formation of an upper wiring in a later step.
【0013】その後、それぞれのタングステン膜10A
(およびコンタクト孔7,8)を介して、それぞれ拡散
層4およびポリサイドゲート電極3に接続される上層の
配線層(図示せず)を層間絶縁膜6上面に形成する。Then, each tungsten film 10A is formed.
An upper wiring layer (not shown) connected to the diffusion layer 4 and the polycide gate electrode 3 respectively (and via the contact holes 7 and 8) is formed on the upper surface of the interlayer insulating film 6.
【0014】なお、上記第1の実施例はN型の拡散層の
みを有する場合の半導体装置の製造方法であるが、N型
の拡散層とP型の拡散層とを有する半導体装置の場合に
は、第1導電体膜として減圧CVD法による低濃度のド
ープド多結晶シリコン膜あるいはノンドープド多結晶シ
リコン膜,もしくはスパッタリング等による所望の膜厚
(コンタクト孔を充填するのでなければ問題はない)の
金属膜等を用いてもよい。The first embodiment is a method of manufacturing a semiconductor device having only an N type diffusion layer. However, in the case of a semiconductor device having an N type diffusion layer and a P type diffusion layer. Is a low-concentration doped polycrystalline silicon film or a non-doped polycrystalline silicon film formed by the low pressure CVD method as the first conductor film, or a metal having a desired film thickness (there is no problem unless the contact hole is filled) by sputtering or the like. A film or the like may be used.
【0015】上記第1の実施例は、1度のフォトリソグ
ラフィ工程により2種類の深さのコンタクト孔を開口し
ても、これら2種類のコンタクト孔内に同時に導電体膜
を充填できる。充填された導電体膜の上面も概ねコンタ
クト孔の上端と一致し、かつ、概ね平坦の面となる。そ
の結果、製造工程が短縮される。さらに、これらのコン
タクト孔に接続される上層の配線のこれらコンタクト孔
の上端近傍での断線は、起りにくくなる。深さが異なる
3種類以上のコンタクト孔がある場合でも、本実施例を
適用することは可能である。In the first embodiment, even if the contact holes having two kinds of depths are opened by one photolithography process, the conductor film can be simultaneously filled in these two kinds of contact holes. The upper surface of the filled conductor film also substantially coincides with the upper end of the contact hole and is a substantially flat surface. As a result, the manufacturing process is shortened. Further, disconnection of upper layer wirings connected to these contact holes near the upper ends of these contact holes is less likely to occur. Even if there are three or more types of contact holes having different depths, this embodiment can be applied.
【0016】半導体装置の製造工程の断面図である図2
の参照すると、本発明の第2の実施例は、以下のように
なっている。FIG. 2 is a sectional view of the manufacturing process of the semiconductor device.
The second embodiment of the present invention is as follows.
【0017】まず、上記第1の実施例と同様に、P型の
半導体基板1表面にゲート酸化膜2を形成し、ゲート酸
化膜2上にポリサイドゲート電極5を形成した後、ポリ
サイドゲート電極5の側壁に絶縁膜スペーサ3を形成す
る。半導体基板1表面にN型の拡散層4を形成した後、
全面に層間絶縁膜6を形成する。次に、拡散層4に達す
る深さの深いコンタクト孔7と、ポリサイドゲート電極
5に達する深さの浅いコンタクト孔8とを層間絶縁膜6
に同時に形成する。コンタクト孔7の口径は、コンタク
ト孔8の口径と同じである〔図2(a)〕。First, similarly to the first embodiment, the gate oxide film 2 is formed on the surface of the P type semiconductor substrate 1, the polycide gate electrode 5 is formed on the gate oxide film 2, and then the polycide gate is formed. The insulating film spacer 3 is formed on the side wall of the electrode 5. After forming the N type diffusion layer 4 on the surface of the semiconductor substrate 1,
An interlayer insulating film 6 is formed on the entire surface. Next, the contact hole 7 having a deep depth reaching the diffusion layer 4 and the contact hole 8 having a shallow depth reaching the polycide gate electrode 5 are formed.
To form at the same time. The diameter of the contact hole 7 is the same as the diameter of the contact hole 8 [FIG. 2 (a)].
【0018】次に、温度300〜400℃,圧力350
〜800Pa,パワー2〜3kWでのスパッタリングに
より、全面にチタン膜と窒化チタン膜とが積層されてな
る第1導電体膜であるところのチタン−窒化チタン膜1
1を形成する。このチタン−窒化チタン膜11の膜厚
も、コンタクト孔7,8の口径に比べて薄く、所望の薄
さになっている〔図2(b)〕。Next, the temperature is 300 to 400 ° C. and the pressure is 350.
-Titanium-titanium nitride film 1 which is a first conductor film formed by laminating a titanium film and a titanium nitride film on the entire surface by sputtering at 800 Pa and a power of 2 to 3 kW.
1 is formed. The film thickness of the titanium-titanium nitride film 11 is smaller than the diameters of the contact holes 7 and 8 and has a desired thickness [FIG. 2 (b)].
【0019】続いて、SiH4 還元,もしくはH2 還元
を用いたCVD法(いわゆるブランケットCVD法)に
より、全面に第2導電体膜であるところの膜厚が少なく
ともコンタクト孔7,8の口径の1/2のタングステン
膜を形成する。本実施例では、全面に上記チタン−窒化
チタン膜11が形成されているため、このタングステン
膜はコンタクト孔7,8の側壁にも十分に成長し,空洞
(キャビティ)の形成がなされることなくこれらコンタ
クト孔7,8を充填することができる。次に、流量比2
〜3のCF4 /O2 ガスを用いた圧力130〜270P
a,パワー200〜300Wのプラズマ異方性エッチン
グによるエッチバックにより、タングステン膜10Bと
チタン−窒化チタン膜11aとをそれぞれのコンタクト
孔7,8内に残置させる。このエッチングではチタン膜
および窒化チタン膜に比べてタングステン膜のエッチン
グ速度が高いため、タングステン膜10Bの上面はチタ
ン−窒化チタン膜11aの上端より低くなっている。チ
タン−窒化チタン膜11aの上端は層間絶縁膜6の上面
(コンタクト孔7,8の上端)より低く、この間隔は所
定の値であり、この値はコンタクト孔7,8の口径の1
/2であることが好ましい〔図2(c)〕。Then, by a CVD method using SiH 4 reduction or H 2 reduction (so-called blanket CVD method), the film thickness of the second conductor film is at least equal to the diameter of the contact holes 7 and 8. A half tungsten film is formed. In the present embodiment, since the titanium-titanium nitride film 11 is formed on the entire surface, this tungsten film also grows sufficiently on the sidewalls of the contact holes 7 and 8 without forming a cavity. These contact holes 7 and 8 can be filled. Next, the flow rate ratio 2
˜3, CF 4 / O 2 gas pressure 130-270P
a, the tungsten film 10B and the titanium-titanium nitride film 11a are left in the respective contact holes 7 and 8 by etching back by plasma anisotropic etching with power of 200 to 300 W. Since the etching rate of the tungsten film is higher than that of the titanium film and the titanium nitride film in this etching, the upper surface of the tungsten film 10B is lower than the upper end of the titanium-titanium nitride film 11a. The upper end of the titanium-titanium nitride film 11a is lower than the upper surface of the interlayer insulating film 6 (upper ends of the contact holes 7 and 8), and this distance is a predetermined value, which is 1 of the diameters of the contact holes 7 and 8.
It is preferably / 2 [Fig. 2 (c)].
【0020】次に、上記第1の実施例と同様に、流量比
1〜2のWF6 /SiH4 ガスを用いた温度200〜3
00℃,圧力0.1〜0.3Paのタングステンの選択
CVD法により、コンタクト孔7,8内にそれぞれ第3
導電体膜であるタングステン膜10Cを形成する。この
結果、コンタクト孔7,8内はそれぞれタングステン膜
10Bとタングステン膜10Cとにより充填される〔図
2(d)〕。Next, as in the first embodiment, temperatures of 200 to 3 using WF 6 / SiH 4 gas with a flow rate ratio of 1 to 2 are used.
By the selective CVD method of tungsten at a temperature of 00 ° C. and a pressure of 0.1 to 0.3 Pa, third contact holes are formed in the contact holes 7 and 8, respectively.
A tungsten film 10C which is a conductor film is formed. As a result, the contact holes 7 and 8 are filled with the tungsten film 10B and the tungsten film 10C, respectively (FIG. 2 (d)).
【0021】なお、第1導電体膜(例えば、チタン膜,
窒化チタン膜等)と第2導電体膜(例えば、タングステ
ン膜)とのエッチング速度がほぼ等しくなる異方性エッ
チングが存在するならば、第1導電体膜の上端および第
2導電体膜の上面が層間絶縁膜の上面と一致するまでエ
ッチバックすればよいことになり、図2(d)に示した
ような第3導電体膜の形成は必要が無くなる。The first conductor film (for example, titanium film,
If there is anisotropic etching in which the etching rates of the titanium nitride film or the like) and the second conductor film (for example, a tungsten film) are substantially equal, the upper end of the first conductor film and the upper surface of the second conductor film are present. Is to be etched back until it coincides with the upper surface of the interlayer insulating film, and the formation of the third conductor film as shown in FIG. 2D is not necessary.
【0022】上記第2の実施例は、上記第1の実施例と
同じ効果を有する。さらに本実施例は、コンタクト孔底
部にバリアメタルとして機能するチタン−窒化チタン膜
が残留形成されているため、上記第1の実施例よりコン
タクト孔でのリーク電流が低減される。The second embodiment has the same effect as the first embodiment. Further, in this embodiment, since the titanium-titanium nitride film functioning as a barrier metal remains formed at the bottom of the contact hole, the leak current in the contact hole is reduced as compared with the first embodiment.
【0023】[0023]
【発明の効果】以上説明したように本発明の半導体装置
の製造方法によると、1度のフォトリソグラフィ工程に
より2種類以上の深さのコンタクト孔を開口しても、こ
れらのコンタクト孔内に同時に導電体膜を充填できる。
充填された導電体膜の上面も概ねコンタクト孔の上端と
一致し、かつ、概ね平坦の面となる。その結果、製造工
程が短縮される。さらに、これらのコンタクト孔に接続
される上層の配線のこれらコンタクト孔の上端近傍での
断線は、起りにくくなる。As described above, according to the method of manufacturing a semiconductor device of the present invention, even if contact holes having two or more kinds of depths are formed by one photolithography process, the contact holes are simultaneously formed in these contact holes. A conductor film can be filled.
The upper surface of the filled conductor film also substantially coincides with the upper end of the contact hole and is a substantially flat surface. As a result, the manufacturing process is shortened. Further, disconnection of upper layer wirings connected to these contact holes near the upper ends of these contact holes is less likely to occur.
【図1】本発明の第1の実施例の製造工程の断面図であ
る。FIG. 1 is a sectional view of a manufacturing process according to a first embodiment of the present invention.
【図2】本発明の第2の実施例の製造工程の断面図であ
る。FIG. 2 is a cross-sectional view of the manufacturing process of the second embodiment of the present invention.
【図3】従来の半導体装置の製造工程の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device manufacturing process.
1 半導体基板 2 ゲート酸化膜 3 ポリサイドゲート電極 4 拡散層 5 絶縁膜スペーサ 6 層間絶縁膜 7,8,17,18 コンタクト孔 9 リンドープド多結晶シリコン膜 9a リンドープド多結晶シリコン膜スペーサ 10A,10B,10C,20 タングステン膜 11,11a チタン−窒化チタン膜 12 多結晶シリコン膜 12a 多結晶シリコン膜スペーサ 15 ゲート電極 1 Semiconductor Substrate 2 Gate Oxide Film 3 Polycide Gate Electrode 4 Diffusion Layer 5 Insulating Film Spacer 6 Interlayer Insulating Film 7, 8, 17, 18 Contact Hole 9 Phosphorus Doped Polycrystalline Silicon Film 9a Phosphorus Doped Polycrystalline Silicon Film Spacer 10A, 10B, 10C , 20 Tungsten film 11, 11a Titanium-titanium nitride film 12 Polycrystalline silicon film 12a Polycrystalline silicon film spacer 15 Gate electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/285 301 R 7376−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 21/285 301 R 7376-4M
Claims (3)
ぞれ異なる複数の種類の配線層を形成し、全面に層間絶
縁膜を形成し、同じ口径を有し,該配線層の上面に達す
る深さの異なる複数の種類のコンタクト孔を該層間絶縁
膜に形成する工程と、 全面に第1導電体膜を形成し、該第1導電体膜を異方性
エッチングして前記層間絶縁膜の上面から所定の深さよ
り下方のそれぞれの前記コンタクト孔の側壁に該第1導
電体膜からなるスペーサを形成する工程と、 第2導電体膜の選択成長を行ない、それぞれの前記コン
タクト孔を該第2導電体膜で充填する工程とを有するこ
とを特徴とする半導体装置の製造方法。1. A plurality of types of wiring layers each having a different height from the surface of the semiconductor substrate are formed, an interlayer insulating film is formed on the entire surface, and the depth is the same as that of the wiring layer. A plurality of types of contact holes having different thicknesses are formed in the interlayer insulating film, and a first conductor film is formed on the entire surface, and the first conductor film is anisotropically etched to form an upper surface of the interlayer insulator film. Forming a spacer made of the first conductor film on the side wall of each of the contact holes below a predetermined depth from, and selectively growing the second conductor film to form each of the contact holes in the second hole. And a step of filling with a conductor film.
ぞれ異なる複数の種類の配線層を形成し、全面に層間絶
縁膜を形成し、同じ口径を有し,該配線層の上面に達す
る深さの異なる複数の種類のコンタクト孔を該層間絶縁
膜に形成する工程と、 全面に第1導電体膜を形成し、それぞれの前記コンタク
ト孔が充填されるまで全面に第2導電体膜を成長する工
程と、 前記第2導電体膜および前記第1導電体膜を異方性エッ
チングによりエッチバックして、それぞれの前記コンタ
クト孔における前記層間絶縁膜の上面から所定の深さま
での該第1導電体膜を除去する工程と、 第3導電体膜の選択成長を行ない、それぞれの前記コン
タクト孔を該第3導電体膜と前記第2導電体膜とで充填
する工程とを有することを特徴とする半導体装置の製造
方法。2. A plurality of types of wiring layers each having a different height from the surface of the semiconductor substrate are formed, an interlayer insulating film is formed on the entire surface, and the depth is the same as that of the wiring layer. Forming a plurality of different kinds of contact holes in the interlayer insulating film, and forming a first conductive film on the entire surface and growing a second conductive film on the entire surface until the contact holes are filled. And a step of etching back the second conductor film and the first conductor film by anisotropic etching to obtain a first depth from the upper surface of the interlayer insulating film in each of the contact holes to a predetermined depth. And a step of selectively growing the third conductor film and filling each of the contact holes with the third conductor film and the second conductor film. Method for manufacturing semiconductor device .
ン膜との積層膜であり、前記第2導電体膜および前記第
3導電体膜がタングステン膜であることを特徴とする請
求項2記載の半導体装置の製造方法。3. The first conductor film is a laminated film of a titanium film and a titanium nitride film, and the second conductor film and the third conductor film are tungsten films. 2. The method for manufacturing a semiconductor device according to 2.
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Cited By (22)
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