KR100284283B1 - Method of forming interconnection for semiconductor device - Google Patents
Method of forming interconnection for semiconductor device Download PDFInfo
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- KR100284283B1 KR100284283B1 KR1019980035701A KR19980035701A KR100284283B1 KR 100284283 B1 KR100284283 B1 KR 100284283B1 KR 1019980035701 A KR1019980035701 A KR 1019980035701A KR 19980035701 A KR19980035701 A KR 19980035701A KR 100284283 B1 KR100284283 B1 KR 100284283B1
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- metal layer
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 87
- 230000004888 barrier function Effects 0.000 claims abstract description 50
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 27
- 239000011737 fluorine Substances 0.000 claims abstract description 27
- 239000007789 gas Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 9
- 238000009832 plasma treatment Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 97
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 16
- 229910052721 tungsten Inorganic materials 0.000 description 16
- 239000010937 tungsten Substances 0.000 description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 배선 형성 방법에 관한 것으로, 이와같은 배선 형성 방법은 기판상에 장벽금속층을 형성하는 공정과; 화학기상증착방법에 의해 불소(f)를 포함하는 소오스가스(source gas)를 사용하여 상기 장벽금속층상에 금속층을 형성하는 공정과; 상기 금속층을 식각하여 금속층패턴을 형성하는 공정과; 수소 플라즈마 처리를 실시하여 상기 장벽금속층에 잔류하는 불소를 제거하는 공정을 포함한다.The present invention relates to a method for forming a wiring of a semiconductor device, the method of forming a wiring comprises the steps of forming a barrier metal layer on a substrate; Forming a metal layer on the barrier metal layer by using a source gas containing fluorine (f) by a chemical vapor deposition method; Etching the metal layer to form a metal layer pattern; Performing a hydrogen plasma treatment to remove fluorine remaining in the barrier metal layer.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로,특히 신뢰성과 양산성이 향상된(개선된) 반도체 소자의 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming wiring of a semiconductor device having improved (improved) reliability and mass productivity.
배선은 소자의 각 단위 파트에 그 기능이 적절한 시기에 작동되도록 하기 위하여 외부(또는 파트간)에서 인가되는 신호(전류)가 흐르는 통로를 말하며, 오늘날 반도체 소자가 고집적화 되어감에 따라, 배선간 선폭이 점점 좁아져 양산성(공정성향상, 쓰루풋(throughput)향상, 공정의 단순화, 그리고 저렴한 공정비용)과 신뢰성 있는 배선형성기술의 개발이 요구된다.Wiring refers to a passage through which a signal (current) applied from the outside (or between parts) flows in each unit part of an element so that its function is operated at an appropriate time, and as the semiconductor devices become more integrated today, the line width between wirings Increasingly, mass production (process improvement, throughput, process simplification, and low process cost) and reliable wiring forming technology are required.
특히, 디램(DRAM)에 있어서, 워드라인, 비트라인, 콘택, 플러그를 포함한 배선이 그것이다. 워드라인은 트랜지스터가 작동할 수 있도록 게이트에 시그널을 주는 기능으로 주로 도프된 폴리실리콘을 사용하며, 플러그는 배선과 배선을 연결하는 기능으로 주로 텅스텐(W)을 사용한다. 텅스텐등은 기존의 WSi2에 비하여 비저항이 1/5이하로 작기 때문에 동일한 디자인룰하에서 비트라인의 두께를 1/5로 낮출수 있고, 동일한 두께를 고수할 경우에는 그 폭을 1/5로 감소시킬 수 있으므로 평탄화와 고집적화에 아주 유리한 장점이 있다. 또한, 글루층(접착제층)으로는 스텝커버리지가 우수한 화학기상증착(CVD) TiN이 주로 사용되고 있다.In DRAM, in particular, the wiring including word lines, bit lines, contacts, and plugs is the same. The word line uses a doped polysilicon mainly to signal the gate for the transistor to operate, and the plug uses tungsten (W) mainly to connect the wiring to the wiring. Tungsten lamps can reduce the thickness of the bit line to 1/5 under the same design rule because the specific resistance is less than 1/5 compared to the conventional WSi 2 , and the width is reduced to 1/5 if the same thickness is adhered to. Since it can be made, it is very advantageous for flattening and high integration. As the glue layer (adhesive layer), chemical vapor deposition (CVD) TiN having excellent step coverage is mainly used.
콘택(contact)은 배선과 실리콘기판이 연결되는 부분을 의미하며, 배선(금속)과 실리콘의 전기적 성질이 상이하여 콘택저항이 발생한다. 이러한 콘택저항은 소자특성을 평가하는 한 항목으로서 중요한 의미를 가지며. 양산성있는 소자제조를 위해서는 우선 콘택이 오믹(ohmic)특성을 보여야 하고, 콘택저항이 낮아야하며, 그리고 안정해야한다.Contact refers to a portion where the wiring and the silicon substrate are connected, and the contact resistance is generated because the electrical properties of the wiring (metal) and silicon are different. Such contact resistance has an important meaning as an item for evaluating device characteristics. In order to manufacture mass-produced devices, the contact must first show ohmic characteristics, low contact resistance, and stable.
낮은 콘택저항을 얻기 위해서는 일함수 차이가 작은 금속을 배선재료로 선정해야하고 실리콘에서의 도핑농도가 높아야 한다. 그런데 배선재료로 사용하는 거의 모든 금속의 일함수는 대동소이하므로, 실질적으로 실리콘에서의 도핑농도가 콘택저항을 결정하는 중요한 요인으로 작용한다. 이러한 오믹콘택을 얻기 위한 방법으로는 실리사이드(살리사이드포함)기술이 보편화. 오믹콘택공정시 열처리조건이 중요하다.In order to obtain low contact resistance, a metal having a small work function difference should be selected as a wiring material and a high doping concentration in silicon should be obtained. However, since almost all metals used as wiring materials have similar work functions, the doping concentration in silicon serves as an important factor in determining contact resistance. As a method for obtaining such an ohmic contact, silicide (including salicide) technology is widely used. Heat treatment condition is important in ohmic contact process.
또한,집적도가 증가하면서 제기되는 가장 큰 문제는 콘택과 비아홀의 가로세로의비(aspect ratio rate)가 증가한다는 것이며, 기존공정의 가장 큰 한계는 쿨리메이티드 스퍼터링기술로는 스텝커버리지가 우수한 박막을 증착할 수 없기 때문에 가로세로비가 큰 홀을 채울수 없다는 것이다.In addition, the biggest problem that arises from the increase in density is that the aspect ratio ratio of the contact and the via hole increases, and the biggest limitation of the existing process is that the cooled sputtering technology provides a thin film having excellent step coverage. Because it cannot be deposited, the aspect ratio cannot fill a large hole.
도 1a 내지 도 1c 는 종래 반도체 소자의 배선 형성 방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a wiring forming method of a conventional semiconductor device.
먼저, 도 1a 에 도시된 바와 같이, 불순물영역(2)을 가지는 반도체 기판(1)상에 상기 불순물영역(2)이 노출되도록 콘택홀(3a)을 가진 절연층(3)을 형성한다. 상기 절연층(3)은 주로 비피에스지(BPSG) 등이 도포되어 형성된다.First, as shown in FIG. 1A, an insulating layer 3 having a contact hole 3a is formed on a semiconductor substrate 1 having an impurity region 2 so as to expose the impurity region 2. The insulating layer 3 is mainly formed by coating BPSG or the like.
이후 도 1b 에 도시된 바와 같이, 상기 콘택홀(3a)을 포함한 상기 절연층(3)상에 장벽금속층(4)을 형성한다. 상기 장벽금속층(4)은 Ti/TiN 또는 TiN 등으로 형성된다.Thereafter, as shown in FIG. 1B, the barrier metal layer 4 is formed on the insulating layer 3 including the contact hole 3a. The barrier metal layer 4 is formed of Ti / TiN or TiN.
이후 도 1c 에 도시된 바와 같이, 상기 장벽금속층(4)상에 상기 콘택홀(3a)이 충분히 채워지도록 텅스텐층(5)을 형성한 다음, 상기 텅스텐층(5)을 상기 장벽금속층(4)의 상면이 노출될 때 까지 에치백하여 텅스텐층 플러그(5a)를 형성한다. 상기 텅스텐층(5)은 불소를 포함하는 소오스가스를, 예를 들면 WF6등과 같은 가스를 사용하여 화학기상증착방법에 의해 형성되고, 상기 에치백공정은 불소를 포함하는 식각가스를, 예를 들면 SF6등과 같은 가스를 사용하여 수행된다.Thereafter, as shown in FIG. 1C, a tungsten layer 5 is formed on the barrier metal layer 4 so that the contact hole 3a is sufficiently filled, and then the tungsten layer 5 is replaced with the barrier metal layer 4. The tungsten layer plug 5a is formed by etching back until the top surface of the film is exposed. The tungsten layer 5 is formed by a chemical vapor deposition method using a source gas containing fluorine, for example, WF 6 or the like, and the etch back process is an etching gas containing fluorine, for example. For example, using a gas such as SF 6 .
상기 텅스텐층 플러그(5a)의 형성 후, 도 2 에 도시된 바와 같이, 노출된 장벽금속층(4)에 불소성분이 잔류하게 된다. 상기 잔류 불소는 텅스텐층을 형성하고 이를 식각하여 텅스텐층 플러그를 형성할 때, 소오스가스 및 식각가스로 각각 사용하는 WF6와 SF6에 의해 발생된다.After the formation of the tungsten layer plug 5a, as shown in FIG. 2, the fluorine component remains in the exposed barrier metal layer 4. The residual fluorine is generated by WF 6 and SF 6 used as source gas and etching gas, respectively, when forming a tungsten layer and etching the tungsten layer plug.
상기한 바와 같은 종래 반도체 소자의 배선 형성 방법은 장벽금속층에 잔류하는 불소로 인해 이후 증착될 배선층에 보이드를 유발시켜 배선에 대한 신뢰성과 양선성을 저하시키는 문제점이 있었다.The wiring formation method of the conventional semiconductor device as described above has a problem of lowering the reliability and goodness of the wiring by causing voids in the wiring layer to be subsequently deposited due to fluorine remaining in the barrier metal layer.
또한, 배선층과 장벽금속층간의 계면접착력을 약화시켜 막의 필링(peeling)현상을 야기하는 문제점이 있었다.In addition, there is a problem in that the interfacial adhesion between the wiring layer and the barrier metal layer is weakened to cause peeling of the film.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 텅스텐플러그의 형성 후 수소 및 질소 플라즈마 처리를 연속적으로 실시하여 노출된 장벽금속층에 잔류하는 불소를 제거하여 신뢰성과 양산성이 향상된 반도체 소자의 배선 형성 방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention is to form a wire of a semiconductor device having improved reliability and mass productivity by removing fluorine remaining in the exposed barrier metal layer by continuously performing hydrogen and nitrogen plasma treatment after the formation of the tungsten plug. The purpose is to provide a method.
상기와 같은 목적을 달성하기 위한 본 발명의 일실시예에 따른 반도체 소자의 배선 형성 방법은 기판상에 장벽금속층을 형성하는 공정과; 화학기상증착방법에 의해 불소를 포함하는 소오스가스를 사용하여 상기 장벽금속층상에 금속층을 형성하는 공정과; 상기 금속층을 식각하여 금속층패턴을 형성하는 공정과; 수소 플라즈마 처리를 실시하여 상기 장벽금속층에 잔류하는 불소를 제거하는 공정을 포함하는 것을 특징으로 한다.According to one or more exemplary embodiments, a wire forming method of a semiconductor device includes: forming a barrier metal layer on a substrate; Forming a metal layer on the barrier metal layer using a source gas containing fluorine by a chemical vapor deposition method; Etching the metal layer to form a metal layer pattern; And performing a hydrogen plasma treatment to remove fluorine remaining in the barrier metal layer.
또한, 본 발명의 다른 일실시예에 따른 반도체 소자의 배선 형성 방법은 기판상에 제 1 콘택홀을 가진 제 1 절연막을 형성하는 공정과; 상기 제 1 콘택홀 및 상기 제 1 절연막상에 제 1 장벽금속층을 형성하는 공정과; 상기 제 1 장벽금속층상에 제 1 금속층을 형성하는 공정과; 상기 제 1 금속층상에 제 2 콘택홀을 가지는 제 2 절연막을 형성하는 공정과; 상기 제 2 콘택홀 및 제 2 절연막상에 제 2 장벽금속층을 형성하는 공정과; 상기 제 2 장벽금속층상에 제 2 금속층을 형성하는 공정과; 불소를 포함하는 식각가스로 상기 제 2 금속층을 식각하여 제 2 콘택홀에 플러그를 형성하는 공정과; 수소 플라즈마 처리를 실시하여 상기 제 2 장벽금속층에 잔류하는 불소를 제거하는 공정을 포함하는 것을 특징으로 한다.In addition, a method for forming a wiring of a semiconductor device according to another embodiment of the present invention includes the steps of forming a first insulating film having a first contact hole on the substrate; Forming a first barrier metal layer on the first contact hole and the first insulating film; Forming a first metal layer on the first barrier metal layer; Forming a second insulating film having a second contact hole on the first metal layer; Forming a second barrier metal layer on the second contact hole and the second insulating film; Forming a second metal layer on the second barrier metal layer; Forming a plug in a second contact hole by etching the second metal layer with an etching gas containing fluorine; And performing a hydrogen plasma treatment to remove fluorine remaining in the second barrier metal layer.
도 1a 내지 도 1c 는 종래 반도체 소자의 배선 형성 방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views for explaining a wiring formation method of a conventional semiconductor device.
도 2 는 도 1c 의 'A' 부분의 확대단면로서, 금속층플러그의 형성 후 노출된 장벽금속층에 잔류하는 불소를 보여주기 위한 설명도.FIG. 2 is an enlarged cross-sectional view of a portion 'A' of FIG. 1C and illustrates an example of fluorine remaining in the exposed barrier metal layer after formation of the metal layer plug; FIG.
도 3a 및 3b 는 본 발명의 일실시예에 따른 반도체 소자의 배선 형성 방법을 설명하기 위한 단면도.3A and 3B are cross-sectional views illustrating a wire forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 4a 내지 4c 는 본 발명의 다른 실시예에 따른 반도체 소자의 배선 형성 방법을 설명하기 위한 단면도.4A to 4C are cross-sectional views illustrating a wiring forming method of a semiconductor device in accordance with another embodiment of the present invention.
도 5 는 도 3b 및 도 4c 의 'B' 부분의 확대단면도로서, 금속층플러그의 형성 후 장벽금속층에 잔류하는 불소가 수소 플라즈마 처리에 의해 상기 장벽금속층으로부터 제거되는 것을 설명하기 위한 것이다.FIG. 5 is an enlarged cross-sectional view of the portion 'B' of FIGS. 3B and 4C to explain that fluorine remaining in the barrier metal layer after formation of the metal layer plug is removed from the barrier metal layer by hydrogen plasma treatment.
**도면의주요부분에대한부호설명**** description of the main parts of the drawings **
10 : 반도체 기판 11 : 불순물영역10 semiconductor substrate 11 impurity region
20 : 제 1 절연층 21 : 제 1 콘택홀20: first insulating layer 21: first contact hole
30 : 제 1 장벽금속층 40 : 제 1 금속층30: first barrier metal layer 40: first metal layer
41 : 제 1 금속층 플러그 (제 1 플러그)41: first metal layer plug (first plug)
50 : 제 2 절연층 51 : 제 2 콘택홀50: second insulating layer 51: second contact hole
60 : 제 2 장벽금속층 70 : 제 2 금속층60: second barrier metal layer 70: second metal layer
71 : 제 2 금속층 플러그 (제 2 플러그)71: second metal layer plug (second plug)
이하, 본 발명에 따른 반도체 소자의 배선 형성 방법에 대해 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the wiring formation method of the semiconductor element which concerns on this invention is demonstrated.
도 3a 및 도 3b 는 본 발명의 일실시예에 따른 반도체 소자의 배선 형성 방법을 설명하기 위한 반도체 소자의 단면들을 도시한 것이다.3A and 3B illustrate cross-sectional views of a semiconductor device for describing a method of forming wirings in the semiconductor device according to an embodiment of the present invention.
도 3a 에 도시된 바와 같이, 불순물영역(11)을 가지는 반도체 기판(10)상에 제 1 절연층(20)을 형성하고, 상기 불순물영역(11)에 대응하는 상기 반도체 기판(10)의 상면 일부가 노출되도록 상기 제 1 절연층(20)을 포토에칭하여 제 1 콘택홀(21)을 형성한다.As shown in FIG. 3A, a first insulating layer 20 is formed on a semiconductor substrate 10 having an impurity region 11, and an upper surface of the semiconductor substrate 10 corresponding to the impurity region 11 is formed. The first insulating layer 20 is photoetched to expose a part of the first contact hole 21.
상기 제 1 절연층(20)은 붕소나 인이 도프된 비피에스(BSPG:Boron Phosphorous Silicate Glass), 에스오지(SOG:Spin On Glass), 피이티이오에스(PE-TEOS :Pe-TetraEthylOrthoSilcate) 등으로 형성된다.The first insulating layer 20 may be formed of boron or phosphorus-doped BPSG (Boron Phosphorous Silicate Glass), SG: Spin On Glass (PEG), PE-TEOS (Pe-TetraEthylOrthoSilcate), or the like. Is formed.
이후 도 3b 에 도시된 바와 같이, 상기 제 1 콘택홀(21)을 포함하는 상기 제 1 절연층(20)상에 제 1 장벽금속층(30)을 형성하고, 상기 제 1 장벽금속층(30)상에 제 1 금속층(40)을 증착한 후, 상기 제 1 절연층(20)상의 제 1 장벽금속층(30)이 노출되도록 상기 제 1 금속층(40)을 에치백 또는 화학적 기계적 연마하여 금속층플러그(제 1 플러그)(41)를 형성한다. 상기 제 1 장벽금속층(30)은 TiN, Ti/TiN, TiW 등으로 형성되고, 상기 제 1 금속층(40)은 텅스텐으로 형성된다. 상기 텅스텐은 주로 불소성분을 포함하는 소오스가스를 사용하는 화학기상증착방법을 통해 형성되며, 상기 에치백공정은 불소를 포함하는 식각가스를 사용하여 수행된다. 상기 소오스가스로는 WF6가, 상기 식각가스로는 SF6가 주로 사용된다.3B, a first barrier metal layer 30 is formed on the first insulating layer 20 including the first contact hole 21, and then on the first barrier metal layer 30. After depositing the first metal layer 40 on the metal layer plug, the first metal layer 40 is etched back or chemically mechanically polished to expose the first barrier metal layer 30 on the first insulating layer 20. 1 plug) 41 is formed. The first barrier metal layer 30 is formed of TiN, Ti / TiN, TiW, or the like, and the first metal layer 40 is formed of tungsten. The tungsten is formed through a chemical vapor deposition method using a source gas mainly containing a fluorine component, and the etch back process is performed using an etching gas containing fluorine. The source gas, a WF 6, wherein the etching gas is SF 6 are commonly used.
상기 금속층 플러그(41)의 형성 후, 도 5 에 도시된 바와 같이, 노출된 상기 제 1 장벽금속층(30)에 불소가 잔류한다. 상기 잔류불소는 불소를 포함하는 상기 소오스가스(WF6) 및 식각가스(SF6)를 사용하여 상기 텅스텐층을 증착 및 식각할 때 발생하며, 노출된 상기 장벽금속층(30)의 표면이나 결정입계에 잔류하게 된다.After formation of the metal layer plug 41, fluorine remains in the exposed first barrier metal layer 30, as shown in FIG. The residual fluorine is generated when the tungsten layer is deposited and etched using the source gas (WF 6 ) and the etching gas (SF 6 ) containing fluorine, and the exposed surface or grain boundary of the barrier metal layer 30 is exposed. Will remain.
이러한 잔류 불소를 제거하기 위해, 배선층을 증착하기 전, 수소 플라즈마 처리를 행한다. 그 결과, 잔류 불소는 수소와의 화학반응에 의해 기체인 불산으로 제거된다. 또한, 잔류불소를 제거한 상태에서, 질소 플라즈마 처리를 행한다. 그 결과, 장벽금속층(30)의 결정입계에 질소가 스터핑되어 막의 조직이 치밀하게 된다.In order to remove such residual fluorine, a hydrogen plasma treatment is performed before the wiring layer is deposited. As a result, residual fluorine is removed by gaseous hydrofluoric acid by a chemical reaction with hydrogen. In addition, nitrogen plasma treatment is performed while residual fluorine is removed. As a result, nitrogen is stuffed at the grain boundaries of the barrier metal layer 30, resulting in a dense structure of the film.
도 4a 및 도 4c 는 본 발명의 다른 실시예에 따른 반도체 소자의 배선 형성 방법을 설명하기 위한 반도체 소자의 단면들을 도시한 것이다.4A and 4C illustrate cross-sectional views of a semiconductor device for describing a method of forming wirings in the semiconductor device, according to another embodiment of the present invention.
단, 장벽금속층이 형성되기 전의 공정은 도 3a 에서 설명한 바와 동일하여 도 4a 에 대한 설명은 생략한다.However, the process before the barrier metal layer is formed is the same as described in Figure 3a, and the description of Figure 4a will be omitted.
도 4b 에 도시된 바와 같이, 상기 제 1 콘택홀(21)을 포함하는 상기 제 1 절연층(20)상에 제 1 장벽금속층(30)을 형성하고, 상기 제 1 장벽금속층(30)상에 제 1 금속층(40)을 증착한다. 상기 제 1 금속층(40)은 텅스텐으로, 주로 WF6를 소오스가스로 사용하는 화학기상증착방법에 의해 형성된다.As shown in FIG. 4B, a first barrier metal layer 30 is formed on the first insulating layer 20 including the first contact hole 21, and on the first barrier metal layer 30. The first metal layer 40 is deposited. The first metal layer 40 is made of tungsten, and is formed by a chemical vapor deposition method using mainly WF 6 as a source gas.
이후 도 4c 에 도시된 바와 같이, 상기 제 1 금속층(40)상에 제 2 콘택홀(51)을 가지는 제 2 절연층(50)을 형성하고, 상기 제 2 콘택홀(51)을 포함하는 상기 제 2 절연층(50)상에 제 2 장벽금속층(60)을 형성하고, 상기 제 2 장벽금속층(60)상에 제 2 금속층(70)을 형성한 다음, 상기 제 2 절연층(50)상의 제 2 장벽금속층(60)이 노출되도록 상기 제 2 금속층(70)을 에치백 또는 화학적 기계적 연마하여 상기 제 2 콘택홀(51)에 금속층플러그(제 2 플러그)(71)를 형성한다. 상기 제 2 장벽금속층(60)은 TiN, Ti/TiN, TiN 등으로 형성되고, 상기 제 2 금속층(70)은 텅스텐으로 형성된다. 상기 텅스텐은 주로 WF6를 기체원료로 하는 화학기상증착을 통해 형성되며, 상기 에치백공정시 불소를 포함하는 SF6를 에천트가스로 하는 식각공정에 의해 패터닝된다.4C, the second insulating layer 50 having the second contact hole 51 is formed on the first metal layer 40, and the second contact hole 51 is formed. A second barrier metal layer 60 is formed on the second insulating layer 50, a second metal layer 70 is formed on the second barrier metal layer 60, and then the second barrier metal layer 60 is formed on the second insulating layer 50. The second metal layer 70 is etched back or chemically mechanically polished to expose the second barrier metal layer 60 to form a metal layer plug (second plug) 71 in the second contact hole 51. The second barrier metal layer 60 is formed of TiN, Ti / TiN, TiN, and the like, and the second metal layer 70 is formed of tungsten. The tungsten is mainly formed through chemical vapor deposition using WF 6 as a gas raw material, and is patterned by an etching process using SF 6 containing fluorine as an etchant gas during the etch back process.
상기 금속층 플러그(71)의 형성 후, 노출된 상기 제 2 장벽금속층(60)에 불소가 잔류하게 되는데, 이를 제거하는 방법은 앞서 설명한 바와 동일하여 이에 대한 설명은 생략한다.After the formation of the metal layer plug 71, fluorine remains in the exposed second barrier metal layer 60. The method for removing the same is the same as described above, and thus description thereof will be omitted.
상기한 바와 같은 본 발명에 따른 반도체 소자의 배선 형성 방법은 금속층플러그를 형성한 후 장벽금속층 및 상기 플러그상에 배선층을 증착하기 전에 수소 및 질소 플라즈마 처리를 연속적으로 실시하여 장벽금속층에 잔류하는 불소를 제거함으로써, 배선층과 장벽금속층의 계면에서 보이드가 형성되는 것을 억제하고, 배선층과 장벽금속층간의 접착력도 향상시켜 신뢰성과 양산성이 우수한 배선을 형성할 수 있는 효과가 있다.As described above, in the method of forming a wiring of a semiconductor device according to the present invention, after forming a metal layer plug, hydrogen and nitrogen plasma treatments are successively performed before depositing a wiring layer on the barrier metal layer and the plug to remove fluorine remaining in the barrier metal layer. This eliminates the formation of voids at the interface between the wiring layer and the barrier metal layer, and also improves the adhesive force between the wiring layer and the barrier metal layer, thereby providing a wire having excellent reliability and mass productivity.
Claims (1)
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| JP24537299A JP3160811B2 (en) | 1998-08-31 | 1999-08-31 | Semiconductor element wiring forming method |
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| JPH08306781A (en) * | 1995-04-27 | 1996-11-22 | Nec Corp | Fabrication of semiconductor device |
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| JPH08306781A (en) * | 1995-04-27 | 1996-11-22 | Nec Corp | Fabrication of semiconductor device |
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| KR101315880B1 (en) | 2008-07-23 | 2013-10-08 | 삼성전자주식회사 | Metal wiring structure and method of manufacturing the same |
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