KR100265828B1 - A method for fabricating semiconductor device - Google Patents

A method for fabricating semiconductor device Download PDF

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KR100265828B1
KR100265828B1 KR1019970029081A KR19970029081A KR100265828B1 KR 100265828 B1 KR100265828 B1 KR 100265828B1 KR 1019970029081 A KR1019970029081 A KR 1019970029081A KR 19970029081 A KR19970029081 A KR 19970029081A KR 100265828 B1 KR100265828 B1 KR 100265828B1
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South Korea
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contact hole
oxide film
undoped
film
undoped oxide
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KR1019970029081A
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Korean (ko)
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KR19990004921A (en
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양종열
마숙락
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is to prevent a step difference of a metallic interconnection contact hole from being produced due to an etching velocity of an oxide film which is a part of an interlayer dielectric. CONSTITUTION: The first undoped oxide film(201), the first doped oxide film(202), and the second undoped oxide film(203) are formed on a substrate with a desired lower layer formed. The second undoped oxide film, the first doped oxide film, and the first undoped oxide film are selectively etched to form a conductive contact hole in such a way that an assistant contact hole is further formed on an edge of a region formed with a following metallic interconnection contact hole. A conductive contact hole is formed to be contacted with the lower layer through the conductive contact hole. The third undoped oxide film(204) and the second doped oxide film(205) are formed on the entire surface of the substrate, and the first and second doped oxide films and the first to third undoped oxide films are selectively etched to form the metallic interconnection contact hole.

Description

반도체 소자 제조방법{A method for fabricating semiconductor device}A method for fabricating semiconductor device

본 발명은 반도체 제조 기술에 관한 것으로, 특히 층간절연막 및 콘택홀 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to an interlayer insulating film and a contact hole forming process.

일반적으로, 반도체 소자의 고집적화에 따라 반도체 소자의 다층화는 일반화되어 있으며, 따라서 각 층간의 전기적 절연을 위한 층간절연막을 구성하는 산화막의 종류도 다양해지고 있다.In general, multilayering of semiconductor devices has become common due to high integration of semiconductor devices, and thus, the types of oxide films constituting interlayer insulating films for electrical insulation between layers have also been diversified.

이하, 첨부된 도면 도 1을 참조하여 종래기술을 살펴본다.Hereinafter, with reference to the accompanying drawings Figure 1 looks at the prior art.

도시된 바와 같이 종래의 콘택홀 형성 공정은 실리콘 기판(100)에 대해 소자 분리막(101), 워드라인(102) 등의 소정의 하부층 공정을 마치고, 전체 구조 상부에 층간절연막인 MTO(Medium Temperature Oxide, 103), BPSG(BoroPhospho Silicate Glass)막(104) 및 MTO막(105)을 차례로 증착하고, 비트라인(106)을 형성한다(비트라인 콘택홀 형성 공정 포함). 계속하여, 전체 구조 상부에 층간절연막인 MTO막(107), BPSG막(108), MTO막(109) 및 BPSG막(110)을 차례로 증착하고, 금속배선 콘택홀 형성을 위한 마스크를 사용하여 습식 및 건식 식각을 수행하여 콘택홀을 형성한다.As shown in the drawing, the conventional contact hole forming process finishes a predetermined lower layer process such as the device isolation film 101 and the word line 102 with respect to the silicon substrate 100, and is an MTO (Medium Temperature Oxide), which is an interlayer insulating film on the entire structure. 103, a BPSG (BoroPhospho Silicate Glass) film 104 and an MTO film 105 are sequentially deposited to form a bit line 106 (including a bit line contact hole forming process). Subsequently, an MTO film 107, a BPSG film 108, an MTO film 109, and a BPSG film 110, which are interlayer insulating films, are sequentially deposited on the entire structure, and wetted using a mask for forming a metal wiring contact hole. And dry etching to form a contact hole.

이후, 콘택홀 식각 후 외기에 노출되어 실리콘 기판(100) 상에 형성된 자연 산화막(도시되지 않음)을 제거하기 위하여 세정 공정을 수행한다. 이때, 세정 용액은 희석된 BOE(Buffered Oxide Etchant)인데, 서로 다른 산화막 간의 식각 속도의 차이로 인하여 MTO막(103,105,107,109)의 일부가 콘택홀 내부로 돌출하게 된다. 즉, 불순물이 도핑되지 않은 산화막인 MTO막(103,105,107,109)에 비하여 불순물이 도핑된 BPSG막(104,108,110)의 식각 속도가 빠르기 때문에 상대적으로 식각 속도가 느린 MTO막(103,105,107,109)이 콘택홀 내로 돌출하게 되는 것이다.Thereafter, after the contact hole etching, a cleaning process is performed to remove a natural oxide film (not shown) formed on the silicon substrate 100 by being exposed to the outside air. At this time, the cleaning solution is diluted BOE (Buffered Oxide Etchant). Due to the difference in etching rates between different oxide films, a part of the MTO films 103, 105, 107 and 109 protrude into the contact hole. That is, since the etching rate of the BPSG films 104, 108, 110 doped with impurities is faster than that of the MTO films 103, 105, 107, and 109, which are oxide films that are not doped with impurities, the MTO films 103, 105, 107, and 109 having relatively low etching rates protrude into the contact holes. .

이러한, 콘택홀 측벽의 단차는 이후의 금속막 증착시 단차 피복성을 나쁘게 하는 원인이 되어 콘택의 저항을 증가시키는 요인으로 작용하게 된다.Such a step difference in the sidewalls of the contact hole causes a step coverage worsening in the subsequent deposition of the metal film, thereby acting as a factor of increasing the resistance of the contact.

본 발명은 콘택홀 식각 후 자연 산화막의 습식 제거시 층간절연막을 이루는 산화막 간의 식각 속도차에 의한 금속배선 콘택홀 측벽의 단차를 방지할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a step difference between sidewalls of a metal wiring contact hole due to an etching rate difference between oxide layers forming an interlayer insulating layer when the natural oxide film is wet removed after contact hole etching.

도 1은 종래기술에 따라 형성된 반도체 소자의 콘택홀 단면도.1 is a cross-sectional view of a contact hole of a semiconductor device formed according to the prior art.

도 2a 및 도 2b는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정도.2A and 2B illustrate a semiconductor device manufacturing process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

200 : 실리콘 기판 201,203,204 : MTO막200: silicon substrate 201,203,204: MTO film

202,205 : BPSG막 206 : 포토레지스트 패턴202, 205: BPSG film 206: photoresist pattern

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자 제조방법은,소정의 하부층이 형성된 반도체 기판 상에 제1 비도핑 산화막, 제1 도핑 산화막 및 제2 비도핑 산화막을 차례로 형성하는 제1 단계; 상기 제2 비도핑 산화막, 제1 도핑 산화막 및 상기 제1 비도핑 산화막을 선택 식각하여 도전층 콘택홀을 형성하되, 후속 금속배선 콘택홀 형성 영역의 가장자리에 소정 폭을 가지는 링 형태의 보조 콘택홀이 더 형성되도록 하는 제2 단계; 상기 도전층 콘택홀을 통해 상기 하부층과 콘택되는 도전층을 형성하는 제3 단계; 상기 제3 단계를 마친 전체 구조 상부에 제3 비도핑 산화막 및 제2 도핑 산화막을 형성하되, 상기 제3 비도핑 산화막이 상기 보조 콘택홀에 매립되도록 하는 제4 단계; 상기 제1 및 제2 도핑 산화막과 상기 제1 내지 제3 비도핑 산화막을 선택 식각하여 상기 금속배선 콘택홀을 형성하되, 상기 금속배선 콘택홀이 상기 보조 콘택홀의 일부에 오버랩되도록 하는 제5 단계; 및 상기 금속배선 콘택홀에 대해 자연 산화막 세정 공정을 실시하는 제6 단계를 포함하여 이루어진다.A characteristic semiconductor device manufacturing method of the present invention for achieving the above technical problem, a first undoped oxide film, a first undoped oxide film and a second undoped oxide film sequentially formed on a semiconductor substrate formed with a predetermined lower layer step; The second undoped oxide layer, the first dope oxide layer, and the first undoped oxide layer are selectively etched to form a conductive layer contact hole, and a ring-shaped auxiliary contact hole having a predetermined width at an edge of a subsequent metal wiring contact hole forming region. A second step of further forming; Forming a conductive layer in contact with the lower layer through the conductive layer contact hole; A fourth step of forming a third undoped oxide film and a second doped oxide film on the entire structure after the third step, wherein the third undoped oxide film is buried in the auxiliary contact hole; A fifth step of selectively etching the first and second doped oxide films and the first to third undoped oxide films to form the metal wire contact hole, wherein the metal wire contact hole overlaps a part of the auxiliary contact hole; And a sixth step of performing a natural oxide film cleaning process on the metallization contact hole.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 및 도 2b는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정도로서, 이하 이를 참조하여 설명한다.2A and 2B are diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described below with reference to the drawings.

도 2a를 참조하면, 우선 소자 분리막(도시되지 않음), 워드라인(도시되지 않음)을 포함한 소정의 하부층 공정을 마친 실리콘 기판(200) 상에 MTO막(201), BPSG막(202) 및 MTO막(203)으로 구성된 층간절연막을 형성한다. 이어서, 전도층 콘택(예컨대, 비트라인 콘택) 공정을 진행하는데, 이때 전도층 콘택홀의 디파인과 함께 후속 금속배선 콘택 영역에 보조 콘택홀이 디파인되도록 한다. 즉, MTO막(203) 및 BPSG막(202)을 차례로 선택 식각하여 전도층 콘택홀을 형성할 때 금속배선 콘택 영역을 링 형태로 둘러싸는 보조 콘택홀을 형성한다. 계속하여 전도층 증착 및 마스크 공정을 통해 전도층(도시되지 않음)을 형성한다. 이때 금속배선 콘택 영역의 보조 콘택홀에도 전도층이 매립되나 전도층 식각 공정시 다시 제거된다. 이어서, 전체 구조 상부에 후속 층간절연막으로 MTO막(204) 및 BPSG막(205)을 형성하는데, MTO막(204) 증착시 보조 콘택홀에 MTO막(204)이 매립된다. 다음으로, 전체 구조 상부에 금속배선 콘택홀 형성을 위한 포토레지스트 패턴(206)을 형성한다. 도면에 도시된 바와 같이 금속배선 콘택홀은 보조 콘택홀의 일부 영역에 오버랩되게 된다.Referring to FIG. 2A, first, an MTO film 201, a BPSG film 202, and an MTO are formed on a silicon substrate 200 after a predetermined underlayer process including an isolation layer (not shown) and a word line (not shown). An interlayer insulating film composed of a film 203 is formed. Subsequently, a conductive layer contact (eg, bit line contact) process is performed, wherein the auxiliary contact hole is defined in the subsequent metallization contact region together with the fineness of the conductive layer contact hole. In other words, when the MTO film 203 and the BPSG film 202 are selectively etched to form the conductive layer contact hole, an auxiliary contact hole is formed to surround the metal wiring contact region in a ring shape. Subsequently, a conductive layer (not shown) is formed through the conductive layer deposition and mask process. At this time, the conductive layer is also buried in the auxiliary contact hole of the metal wiring contact region, but is removed again during the conductive layer etching process. Subsequently, an MTO film 204 and a BPSG film 205 are formed as a subsequent interlayer insulating film over the entire structure. The MTO film 204 is embedded in the auxiliary contact hole when the MTO film 204 is deposited. Next, a photoresist pattern 206 for forming a metal wiring contact hole is formed on the entire structure. As shown in the drawing, the metallization contact hole overlaps a part of the auxiliary contact hole.

다음으로 도 2b를 참조하면, 포토레지스트 패턴(206)을 식각 장벽으로 하여 BPSG막(205)의 일부를 등방성(습식) 식각하고, 계속하여 하부의 층간절연막들(205,204,203,202,201)을 비등방성(건식) 식각함으로써 와인 글래스 형태의 금속배선 콘택홀을 형성한다.Next, referring to FIG. 2B, a portion of the BPSG film 205 is isotropically (wet) etched using the photoresist pattern 206 as an etch barrier, and then the lower interlayer insulating films 205, 204, 203, 202, and 201 are anisotropic (dry). By etching, a metal glass contact hole in the form of a wine glass is formed.

이후 자연 산화막(도시되지 않음) 제거를 위한 세정을 실시한다.Thereafter, cleaning is performed to remove the native oxide film (not shown).

전술한 바와 같이 콘택홀을 형성하면 후속 자연 산화막 세정 공정시에 단일막(예컨대, MTO막)이 콘택홀 측벽의 대부분을 구성하고 있기 때문에 세정액에 대한 층간절연막의 식각 속도가 동일하게 나타나며, 이로 인하여 종래와 같이 금속배선 콘택홀 측벽에 단차가 유발되는 것을 방지할 수 있다. 한편, BPSG막(205)이 세정 공정에서 MTO막(201,203,204) 보다 더 빨리 식각되기는 하지만 콘택홀 상부가 조금 넓어질 뿐이므로 문제가 되지 않는다.As described above, when the contact hole is formed, the etching rate of the interlayer insulating film with respect to the cleaning liquid is the same since a single film (for example, an MTO film) forms most of the contact hole sidewalls in the subsequent natural oxide film cleaning process. As in the related art, it is possible to prevent a step from occurring in the sidewall of the metal wiring contact hole. On the other hand, although the BPSG film 205 is etched faster than the MTO films 201, 203, and 204 in the cleaning process, the upper part of the contact hole is slightly widened, which is not a problem.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 층간절연막으로 BPSG막과 MTO를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 금속배선 콘택홀 저부의 자연 산화막 제거를 위한 세정 공정시 다른 식각 특성을 보이는 층간절연막을 다층으로 구성하는 모든 경우에 적용될 수 있다.For example, in the above-described embodiment, the case where the BPSG film and the MTO are used as the interlayer insulating film has been described as an example. However, the present invention provides an interlayer insulating film having different etching characteristics during a cleaning process for removing a natural oxide film at the bottom of the metal wiring contact hole. It can be applied to all the cases configured in a multilayer.

상기와 같이 본 발명은 자연 산화막 제거를 위한 세정 공정에서 층간절연막의 일부가 돌출하여 턱이 지는 현상을 방지하며, 이로 인하여 이후의 콘택홀 매립 공정에서 보이드 발생을 감소시킴으로서 반도체 소자의 신뢰도를 향상시키고 수율을 개선하는 효과가 있다.As described above, the present invention prevents a part of the interlayer insulating film from protruding from the jaw in the cleaning process for removing the natural oxide film, thereby improving the reliability of the semiconductor device by reducing the generation of voids in the subsequent contact hole filling process. It has the effect of improving the yield.

Claims (3)

소정의 하부층이 형성된 반도체 기판 상에 제1 비도핑 산화막, 제1 도핑 산화막 및 제2 비도핑 산화막을 차례로 형성하는 제1 단계;A first step of sequentially forming a first undoped oxide film, a first dope oxide film, and a second undoped oxide film on a semiconductor substrate on which a predetermined lower layer is formed; 상기 제2 비도핑 산화막, 제1 도핑 산화막 및 상기 제1 비도핑 산화막을 선택 식각하여 도전층 콘택홀을 형성하되, 후속 금속배선 콘택홀 형성 영역의 가장자리에 소정 폭을 가지는 링 형태의 보조 콘택홀이 더 형성되도록 하는 제2 단계;The second undoped oxide layer, the first dope oxide layer, and the first undoped oxide layer are selectively etched to form a conductive layer contact hole, and a ring-shaped auxiliary contact hole having a predetermined width at an edge of a subsequent metal wiring contact hole forming region. A second step of further forming; 상기 도전층 콘택홀을 통해 상기 하부층과 콘택되는 도전층을 형성하는 제3 단계;Forming a conductive layer in contact with the lower layer through the conductive layer contact hole; 상기 제3 단계를 마친 전체 구조 상부에 제3 비도핑 산화막 및 제2 도핑 산화막을 형성하되, 상기 제3 비도핑 산화막이 상기 보조 콘택홀에 매립되도록 하는 제4 단계;A fourth step of forming a third undoped oxide film and a second doped oxide film on the entire structure after the third step, wherein the third undoped oxide film is buried in the auxiliary contact hole; 상기 제1 및 제2 도핑 산화막과 상기 제1 내지 제3 비도핑 산화막을 선택 식각하여 상기 금속배선 콘택홀을 형성하되, 상기 금속배선 콘택홀이 상기 보조 콘택홀의 일부에 오버랩되도록 하는 제5 단계; 및A fifth step of selectively etching the first and second doped oxide films and the first to third undoped oxide films to form the metal wire contact hole, wherein the metal wire contact hole overlaps a part of the auxiliary contact hole; And 상기 금속배선 콘택홀에 대해 자연 산화막 세정 공정을 실시하는 제6 단계A sixth step of performing a natural oxide film cleaning process on the metallization contact hole; 를 포함하여 이루어진 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 내지 제3 비도핑 산화막은 각각 중온 산화막(MTO)인 것을 특징으로 하는 반도체 소자 제조방법.The first to third undoped oxide film is a semiconductor device manufacturing method, characterized in that each of the medium temperature oxide (MTO). 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제1 및 제2 도핑 산화막이The first and second doped oxide film 보로포스포 실리키트 글래스(BPSG)막인 것을 특징으로 하는 반도체 소자 제조방법.A method of manufacturing a semiconductor device, characterized in that the Borophospho silicate glass (BPSG) film.
KR1019970029081A 1997-06-30 1997-06-30 A method for fabricating semiconductor device KR100265828B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410649A (en) * 1987-07-02 1989-01-13 Nec Corp Manufacture of semiconductor device
JPH01181415A (en) * 1988-01-08 1989-07-19 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410649A (en) * 1987-07-02 1989-01-13 Nec Corp Manufacture of semiconductor device
JPH01181415A (en) * 1988-01-08 1989-07-19 Toshiba Corp Manufacture of semiconductor device

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