KR100299379B1 - Method for forming metal wiring in semiconductor device - Google Patents
Method for forming metal wiring in semiconductor device Download PDFInfo
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- KR100299379B1 KR100299379B1 KR1019980025766A KR19980025766A KR100299379B1 KR 100299379 B1 KR100299379 B1 KR 100299379B1 KR 1019980025766 A KR1019980025766 A KR 1019980025766A KR 19980025766 A KR19980025766 A KR 19980025766A KR 100299379 B1 KR100299379 B1 KR 100299379B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 배선폭 만큼의트랜치를 형성하고 트랜치 측벽에 질화막 스페이서를 형성한 후 이를 이용하여 콘택홀을 형성함으로써 한번의 마스크 공정으로 금속배선이 절연막 내에 완전히 매립되게 하여 소자의 전기적 특성을 향상시킨 것이다. 본 발명에 따른 반도체 소자의 금속 배선 형성방법은 반도체 기판 상에 층간절연용 산화막과 질화막을 순차적으로 형성하는 단계와, 상기 질화막과 상기 산화막을 소정의 깊이만큼 제 1 식각하여 트렌치를 형성하는 단계와, 상기 트랜치의 측벽에 상기 산화막보다 식각선택비가 높은 절연막으로 이루어진 스페이서를 형성하는 단계와. 상기 스페이서에 의해 노출된 산화막을 상기 기판이 노출되도록 제 2 식각하는 단계와, 상기 스페이서 및 질화막을 제거하여 배선 형태의 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, wherein trenches are formed as much as the wiring width, nitride film spacers are formed on the trench sidewalls, and contact holes are formed using the same to form metal wirings completely embedded in the insulating film in one mask process. It is to improve the electrical characteristics of the device. A method of forming a metal wiring of a semiconductor device according to the present invention includes the steps of sequentially forming an interlayer insulating oxide film and a nitride film on a semiconductor substrate, and forming a trench by first etching the nitride film and the oxide film by a predetermined depth; And forming a spacer on the sidewall of the trench, the insulating layer having an etch selectivity higher than that of the oxide layer. And etching the oxide film exposed by the spacer to expose the substrate, and removing the spacer and the nitride film to form a contact hole in the form of a wiring.
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히 배선폭 만큼의 트랜치를 형성하고 트랜치 측벽에 질화막 스페이서를 형성한 후 이를 이용하여 콘택홀을 형성함으로써 한번의 마스크 공정으로 금속배선이 절연막 내에 완전히 매립되게 하여 소자의 전기적 특성을 향상시킨 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In particular, metal wirings are formed in an insulating film by forming a trench as much as the wiring width, forming a nitride spacer on the trench sidewalls, and forming a contact hole using the same. The present invention relates to a method for forming a metal wiring of a semiconductor device that is completely embedded to improve the electrical characteristics of the device.
반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.
도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도이다. 도 1을 참조하면, 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 기판(10)일부가 노출되도록 층간절연막(11)을 식각하여 콘택홀을 형성한다. 상기 콘택홀에 매립되도록 층간절연막(11) 상에 금속막을 증착하고 패터닝하여 금속 배선(12a, 12b)을 형성한다.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device. Referring to FIG. 1, an interlayer insulating layer 11 is formed on a semiconductor substrate 10, and a contact hole is formed by etching the interlayer insulating layer 11 to expose a portion of the substrate 10. Metal wires 12a and 12b are formed by depositing and patterning a metal film on the interlayer insulating film 11 so as to be filled in the contact hole.
그러나, 상기한 바와 같이 양각 공정에 의해 배선을 형성하는데, 금속막의 열악한 식각 특성에 의해, 도 1에 도시된 바와 같이, 식각 후 금속 배선(12a, 12b) 사이에서 브리지가 발생된다. 이러한, 브리지는 소자의 고집적화에 따라 더욱더 심해져서 소자의 전기적 특성을 저하시킨다.However, as described above, the wiring is formed by an embossing process, and due to the poor etching characteristics of the metal film, as shown in FIG. 1, a bridge is generated between the metal wirings 12a and 12b after etching. Such bridges become more severe with high integration of the device, thereby degrading the electrical characteristics of the device.
따라서, 종래에는 고집적화에 따른 배선 사이의 브리지를 방지하기 위하여 데머신(damascene)공정으로 배선을 형성하였다. 즉, 도 2는 데머신 공정에 의해 형성된 반도체 소자의 금속 배선을 나타낸 단면도로서, 도 1에서와는 달리 층간절연막(21) 내에 화학기계연마(Chemical Mechanical Polishing; CMP)로 금속막을 전면 식각하여 금속 배선(22)을 완전히 매립시켜 형성하기 때문에, 금속막의 열악한 식각특성으로 인해 발생되는 인접 배선과의 브리지 문제가 방지된다.Therefore, in the related art, wirings were formed by a damascene process in order to prevent bridges between wirings due to high integration. That is, FIG. 2 is a cross-sectional view illustrating a metal wiring of a semiconductor device formed by a demachine process. Unlike FIG. 1, the metal film is etched by chemical mechanical polishing (CMP) in the interlayer insulating film 21. Since 22) is completely embedded, the bridge problem with the adjacent wiring caused by the poor etching characteristics of the metal film is prevented.
그러나, 상가한 데머신 공정에 의한 금속 배선에서는 도 1에서와는 달리 금속 배선(22)의 형태로 콘택홀을 형성해야 하기 때문에, 2번의 마스크 공정이 요구된다. 즉, 도 1의 콘택홀의 크기와 같은 콘택홀 형성을 위한 제 1 포토레지스트막 패턴과, 상기 콘택홀 상부를 금속 배선(22) 형태로 패터닝하기 위한 제 2 포토레지스트막 패턴이 요구되므로, 2번의 포토리소그라피 공정 및 2번의 마스크 제거공정이 요구된다.However, since the contact hole must be formed in the form of the metal wiring 22 unlike the case of FIG. 1 in the metal wiring by the additional demachine process, two mask processes are required. That is, since a first photoresist film pattern for forming a contact hole having the same size as that of the contact hole of FIG. 1 and a second photoresist film pattern for patterning the upper portion of the contact hole in the form of a metal wiring 22 are required, A photolithography process and two mask removal processes are required.
따라서, 본 발명은 상기 문제점을 해결하기 위하여 발명된 것으로, 본 발명의 목적은 배선폭 만큼의 트랜치를 형성하고 트랜치 측벽에 질화막 스페이서를 형성한 후 이를 이용하여 콘택홀을 형성함으로써 한번의 마스크 공정으로 금속배선이 절연막 내에 완전히 매립되게 하여 소자의 전기적 특성을 향상시킨 반도체 소자의 금속 배선 형성방법을 제공하는데 있다.Accordingly, the present invention has been invented to solve the above problems, and an object of the present invention is to form a trench as much as the wiring width, form a nitride film spacer on the trench sidewall, and then form a contact hole using the same mask process. The present invention provides a method for forming a metal wiring of a semiconductor device in which the metal wiring is completely embedded in the insulating film to improve the electrical characteristics of the device.
상기 목적을 달성하기 위하여, 본 발명의 반도체 소자의 금속 배선 형성방법은,In order to achieve the above object, the metal wiring formation method of the semiconductor device of the present invention,
반도체 기판 상에 층간절연용 산화막과 질화막을 순차적으로 형성하는 단계;Sequentially forming an interlayer insulating oxide film and a nitride film on the semiconductor substrate;
상기 질화막과 상기 산화막을 소정의 깊이만큼 제 1 식각하여 트렌치를 형성하는 단계;Forming a trench by first etching the nitride film and the oxide film by a predetermined depth;
상기 트렌치의 측벽에 상기 산화막보다 식각선택비가 높은 절연막으로 이루어진 스페이서를 형성하는 단계;Forming a spacer on the sidewall of the trench, the insulating layer having an etch selectivity higher than that of the oxide layer;
상기 스페이서에 의해 노출된 산화막을 상기 기판이 노출되도록 제 2 식각하는 단계; 및,Second etching the oxide film exposed by the spacer to expose the substrate; And,
상기 스페이서 및 질화막을 제거하여 배선 형태의 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.And removing the spacers and the nitride film to form contact holes in the form of wires.
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서, 상기 산화막을 고밀도 플라즈마(HDP) 산화막인 것을 특징으로 한다.In the metal wiring formation method of the semiconductor element of this invention, the said oxide film is characterized by being a high density plasma (HDP) oxide film.
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서. 상기 스페이서를 형성하는 단계는 상기 트렌치가 형성된 기판 전면에 상기 절연막을 형성하는 단계; 및, 상기 절연막을 건식식각하는 단계를 포함하는 것을 특징으로 한다.In the metal wiring formation method of the semiconductor element of this invention. The forming of the spacer may include forming the insulating layer on the entire surface of the substrate on which the trench is formed; And dry etching the insulating film.
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서. 상기 절연막은 질화막인 것을 특징으로 한다.In the metal wiring formation method of the semiconductor element of this invention. The insulating film is characterized in that the nitride film.
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서, 상기 제 2 식각은 건식식각으로 진행하는 것을 특징으로 한다.In the method of forming a metal wiring of the semiconductor device of the present invention, the second etching is characterized in that the dry etching proceeds.
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서, 상기 스페이서 및 질화막은 BOE 및 H3PO4을 이용하여 제거하는 것을 특징으로 한다.In the method for forming a metal wiring of the semiconductor device of the present invention, the spacer and the nitride film are removed using BOE and H 3 PO 4 .
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서, 상기 콘택홀을 형성하는 단계 이후에 상기 콘택홀에 매립되도록 상기 기판 전면에 배선용 금속막을 형성하는 단계; 및, 상기 금속막을 상기 산화막이 노출되도록 전면식각하는 단계를더 포함하는 것을 특징으로 한다.A method of forming a metal wiring of a semiconductor device according to the present invention, the method comprising: forming a wiring metal film on an entire surface of the substrate to be filled in the contact hole after the forming of the contact hole; And etching the entire surface of the metal film to expose the oxide film.
본 발명의 반도체 소자의 금속 배선 형성방법에 있어서, 상기 전면식각은 화학기계연마(CMP)로 진행하는 것을 특징으로 한다.In the method of forming a metal wiring of the semiconductor device of the present invention, the front surface etching is characterized in that it proceeds by chemical mechanical polishing (CMP).
도 1은 종래의 반도체 소자의 금속 배선을 나타낸 단면도1 is a cross-sectional view showing a metal wiring of a conventional semiconductor device
도 2는 종래의 데머신 공정에 의한 반도체 소자의 금속 배선을 나타낸 단면도.2 is a cross-sectional view showing a metal wiring of a semiconductor device by a conventional demachine process.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 데머신 공정에 의한 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도3A to 3F are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device by a demachine process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
30 : 반도체 기판 31 : HDP 산화막30 semiconductor substrate 31 HDP oxide film
32, 35 : 제 1 및 제 2 질화막 33 : 포토레지스트막 패턴32, 35: first and second nitride films 33: photoresist film pattern
34 : 트렌치 35a : 질화막 스페이서34: trench 35a: nitride film spacer
36 : 콘택홀 37 : 금속 배선36: contact hole 37: metal wiring
이하, 도면을 참조로하여 본 발명의 실시예를 설명하기로 한다.Hereinafter, embodiments of the present invention will be described with reference to the drawings.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 데머신 공정에 의한 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도이다.3A to 3F are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device by a demachine process according to an embodiment of the present invention.
도 3a를 참조하면, 반도체 기판(30) 상에 층간절연을 위한 산화막으로서 고밀도 플라즈마(High Density Plasma;HDP) 산화막(31)을 형성하고, HDP 산화막(32) 상에 제 1 질화막(32)을 형성한다. 도 3b를 참조하면, 제 1 질화막(32)상에 포토리소그라피로 배선의 폭만큼 질화막(32)이 노출되도록 포토레지스트막 패턴(33)을 형성한다. 포토레지스트막 패턴(33)을 식각 마스크로하여 노출된 제 1 질화막(32)과, 그의 하부의 HDP 산화막(32)을 소정 깊이만큼 식각하여 트렌치(34)를 형성한다.Referring to FIG. 3A, a high density plasma (HDP) oxide film 31 is formed on the semiconductor substrate 30 as an oxide film for interlayer insulation, and the first nitride film 32 is formed on the HDP oxide film 32. Form. Referring to FIG. 3B, the photoresist film pattern 33 is formed on the first nitride film 32 so that the nitride film 32 is exposed by the width of the wiring by photolithography. The trench 34 is formed by etching the first nitride film 32 exposed using the photoresist film pattern 33 as an etching mask and the lower HDP oxide film 32 below the predetermined depth.
도 3c를 참조하면, 공지된 방법으로 포토레지스트막 패턴(33)을 제거하고, 기판 전면에 HDP 산화막(31)과 식각선택비가 높은 절연막으로서 제 2 질화막(35)을 형성한다. 그런 다음, 제 2 질화막(35)을 건식식각하여, 도 3d에 도시된 바와 같이, 트렌치(34)의 측벽에 질화막 스페이서(35a)를 형성한다. 질화막 스페이서(35a)를 식각 마스크로하여 노출된 HDP 산화막(31)을 기판(30)이 노출되도록 식각한다. 이때, 식각은 건식식각으로 진행한다. 즉, 질화막과 산화막의 식각비는 최대 20 : 1로서, HDP 산화막(31)의 식각시 질화막 스페이서(35a)를 마스크로 사용할 수 있다. 그런 다음, BOE(Buffere Oxide Etchant) 및 H3PO4을 이용하여 질화막 스페이서(35a) 및 제 1 질화막(32)을 제거하여, 도 3e에 도시된 바와 같이, 배선 형태의 콘택홀을 형성한다.Referring to FIG. 3C, the photoresist film pattern 33 is removed by a known method, and a second nitride film 35 is formed on the entire surface of the substrate as an insulating film having a high etching selectivity and an HDP oxide film 31. Then, the second nitride film 35 is dry etched to form the nitride film spacer 35a on the sidewall of the trench 34 as shown in FIG. 3D. The exposed HDP oxide film 31 is etched to expose the substrate 30 by using the nitride film spacer 35a as an etch mask. At this time, the etching proceeds to dry etching. That is, the etch ratio of the nitride film and the oxide film is at most 20: 1, and the nitride film spacer 35a may be used as a mask when the HDP oxide film 31 is etched. Then, the nitride film spacer 35a and the first nitride film 32 are removed using BOE (Buffer Oxide Etchant) and H 3 PO 4 to form a contact hole in the form of a wiring, as shown in FIG. 3E.
도 3f를 참조하면, 콘택홀에 매립되도록 HDP 산화막(31) 상에 금속막을 증착하고, CMP로 HDP 산화막(31)이 노출될 때까지 전면식각하여, 금속 배선(37)을 형성한다.Referring to FIG. 3F, a metal film is deposited on the HDP oxide film 31 so as to be buried in a contact hole, and the metal wire 37 is formed by etching the entire surface until the HDP oxide film 31 is exposed by CMP.
이상에서 설명한 바와 같이, 본 발명의 반도체 소자의 금속 배선 형성방법에 의하여, 데머신 공정에 의한 배선의 형성에서, 한번의 마스크 공정을 이용하여 배선폭 만큼의 트렌치를 형성하고, 트렌치 측벽에 질화막 스페이서를 형성한 후, 이 질화막 스페이서를 이용하여 콘택홀을 형성한다. 이에 따라. 종래의 2번의 마스크 공정이 한번으로 감소되므로, 원가절감의 효과를 얻을 수 있을 뿐만 아니라. 홀내에 포토레지스트막이 도포되지 않기 때문에, 포토레지스트막의 잔류 문제도 방지된다. 또한, 금속 배선이 절연막 내에 완전히 매립되어 형성되기 때문에, 인접 배선과이 브리지가 발생되지 않으므로, 소자의 전기적 특성이 향상된다.As described above, according to the metal wiring forming method of the semiconductor element of the present invention, in the formation of the wiring by the demachine process, trenches as wide as the wiring width are formed using one mask process, and nitride film spacers are formed on the trench sidewalls. After forming a contact hole, a contact hole is formed using this nitride film spacer. Accordingly. Since the conventional two mask processes are reduced to one, not only the cost reduction effect can be obtained. Since no photoresist film is applied in the holes, the problem of remaining of the photoresist film is also prevented. In addition, since the metal wiring is completely embedded in the insulating film, the adjacent wiring and the bridge are not generated, so that the electrical characteristics of the device are improved.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
Claims (8)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100428791B1 (en) * | 2002-04-17 | 2004-04-28 | 삼성전자주식회사 | Method of forming dual damascene interconnection using low dielectric material |
| US7132364B2 (en) | 2003-06-27 | 2006-11-07 | Dongbuanam Semiconductor Inc. | Method for forming metal interconnect of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100759256B1 (en) * | 2001-06-30 | 2007-09-17 | 매그나칩 반도체 유한회사 | method of forming dual damascene pattern using photo resist spacer |
| KR20030052815A (en) * | 2001-12-21 | 2003-06-27 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR100772077B1 (en) * | 2001-12-28 | 2007-11-01 | 매그나칩 반도체 유한회사 | A method for forming contact hole of semiconductor device |
| US7572694B2 (en) * | 2005-12-28 | 2009-08-11 | Dongbu Hitek Co., Ltd. | Method of manufacturing a semiconductor device |
| KR100744070B1 (en) * | 2006-03-20 | 2007-07-30 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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| KR970023991A (en) * | 1995-10-24 | 1997-05-30 | 김광호 | Separation method of semiconductor device using Y-shaped trench |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR970023991A (en) * | 1995-10-24 | 1997-05-30 | 김광호 | Separation method of semiconductor device using Y-shaped trench |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100428791B1 (en) * | 2002-04-17 | 2004-04-28 | 삼성전자주식회사 | Method of forming dual damascene interconnection using low dielectric material |
| US7132364B2 (en) | 2003-06-27 | 2006-11-07 | Dongbuanam Semiconductor Inc. | Method for forming metal interconnect of semiconductor device |
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