KR100209279B1 - Method for forming a contact of semiconductor device - Google Patents
Method for forming a contact of semiconductor device Download PDFInfo
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- KR100209279B1 KR100209279B1 KR1019950069469A KR19950069469A KR100209279B1 KR 100209279 B1 KR100209279 B1 KR 100209279B1 KR 1019950069469 A KR1019950069469 A KR 1019950069469A KR 19950069469 A KR19950069469 A KR 19950069469A KR 100209279 B1 KR100209279 B1 KR 100209279B1
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- interlayer insulating
- contact hole
- etching
- insulating film
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012071 phase Substances 0.000 claims description 6
- 239000012808 vapor phase Substances 0.000 claims description 5
- 239000011259 mixed solution Substances 0.000 claims 4
- 239000000243 solution Substances 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 콘택홀 제조 공정시, 콘택홀의 형성으로 인해 노출되는 접합 영역의 손상을 방지할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것으로 접합 영역에 손상이 발생하지 않는 콘택홀 형성시, 층간 절연막의 일부분이 잔존하도록 건식 식각하거나, 또는 건식 식각 공정없이 HF / CH3OH 또는 HF / CH3OH /N2용액에 의한 기상 식각 방식으로 층간 절연막을 식각하여 콘택홀로 노출되는 접합 영역에 데미지가 발생함을 방지하고, 습식 식각을 진행하여도 측부의 식각을 방지하여 소자의 특성을 향상시킨다.The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of forming a contact hole in a semiconductor device, which can prevent damage to a junction region exposed due to formation of a contact hole in a process of manufacturing a contact hole in a semiconductor device. In the case of forming a contact hole that does not cause damage to the junction region, dry etching is carried out so that a portion of the interlayer insulating film remains, or gas phase by HF / CH 3 OH or HF / CH 3 OH / N 2 solution without dry etching process. The etching method of the interlayer insulating layer is etched to prevent damage to the junction region exposed to the contact hole, and the etching of the side part is prevented even when wet etching is performed to improve the device characteristics.
Description
제1도는 종래의 방법에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for forming a contact hole in a semiconductor device according to a conventional method.
제2(a)도 및 제2(b)도는 본 발명의 실시예 1에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도.2 (a) and 2 (b) are cross-sectional views for explaining a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.
제3도는 본 발명의 실시예 2에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도.3 is a cross-sectional view illustrating a method for forming a contact hole in a semiconductor device according to a second exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 15 : 접합 영역11 semiconductor substrate 15 junction region
16 : 층간 절연막 17 : 평탄화 절연막16: interlayer insulation film 17: planarization insulation film
17' : 잔여 산화막 18 : 콘택홀17 ': remaining oxide film 18: contact hole
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 콘택홀 제조 공정시, 콘택홀의 형성으로 인해 노출되는 접합 영역의 손상을 방지할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of forming a contact hole in a semiconductor device, which can prevent damage to a junction region exposed due to formation of a contact hole in a process of manufacturing a contact hole in a semiconductor device. It is about.
알려진 바와 같이, 반도체 소자의 제조 공정에 있어서의, 콘택홀(contact hole)은 하부에 형성된 전극 배선과 상부의 전극 배선을 전기적으로 접속시키기 위한 접속공을 말한다. 현재에는 소자의 고집적화와 더불어 콘택홀의 크기 또한 사진 식각 기술에 의해 형성할 수 있는 최소 노광 한계에 접근하고 있다.As is known, a contact hole in the manufacturing process of a semiconductor element means the connection hole for electrically connecting the electrode wiring formed in the lower part and the upper electrode wiring. In addition to the high integration of devices, the size of contact holes is approaching the minimum exposure limit that can be formed by photolithography.
이러한 미세한 콘택홀을 형성하기 위하여 종래에는, 제1도에 도시된 바와 같이, 반도체 소자를 구성하는 필드 산화막(2), 게이트 절연막(3), 게이트 전극(4) 및 접합 영역(5)등이 형성된 반도체 기판(1) 상부에 층간 절연막(6)을 형성하고, 이어서, 하부의 토포로지를 감소시키기 위하여 평탄화 절연막(7) 예를들어, BPSG막을 형성한다.In order to form such a fine contact hole, as shown in FIG. 1, a field oxide film 2, a gate insulating film 3, a gate electrode 4, a junction region 5, etc. constituting a semiconductor element are conventionally used. An interlayer insulating film 6 is formed over the formed semiconductor substrate 1, and then a planarizing insulating film 7, for example, a BPSG film is formed in order to reduce the underlying topology.
그리고, 상기 접합 영역이 노출될 수 있도록 마스크 패턴(도시되지 않음)을 형성하고, 이의 형태로 SF4, CHF3가스를 이용한 플라즈마 식각 방식에 의하여 콘택홀을 형성한다. 이때, 상기 식각 공정시, 콘택홀의 크기의 감소에 따라 발생하는-로딩 이펙트로 인하여 미세한 간격의 콘택홀을 제조하기 위해서는 기존의 식각 시간보다 장시간의 식각 공정을 진행하는 오버 에칭(over etching)을 실시하여 콘택홀을 형성한다.Then, a mask pattern (not shown) is formed to expose the junction region, and contact holes are formed by plasma etching using SF 4 and CHF 3 gas in the form thereof. At this time, during the etching process, generated due to the decrease in the size of the contact hole Due to the loading effect, in order to manufacture contact holes with a small interval, the contact holes are formed by performing over etching which is performed for a longer time than the conventional etching time.
그러나, 상기와 같은 종래의 방식에 따르면, 각각의 콘택홀 영역에 식각 균일도가 일정하지 않아, 오버 에칭을 진행하게 되면, 어느 한쪽 영역에는 필연적으로 접합 영역이 손상되고, 또한 고밀도의 플라즈마 가스에 식각이 이루어지므로써 콘택홀 저면부의 접합 영역에 식각 가스로 인한 데미지가 발생하는 문제점이 발생하였다.However, according to the conventional method as described above, the etching uniformity is not constant in each contact hole region, and when overetching is performed, the junction region is inevitably damaged in one region, and is etched in a high density plasma gas. As a result, damage caused by etching gas occurred in the junction region of the bottom of the contact hole.
이러한 문제점을 해결하기 위한 종래의 다른 방법은, 상기 콘택홀 식각시 하단 영역에 100정도 층간 절연막을 잔존시킨다음, 잔존하는 절연막을 HF 및 BOE (bufferde oxide etchant)를 이용하여 습식 식각하는 방법이 제안되었지만, 상기 습식 식각시 콘택홀 하단에 측부로 식각이 이루어지게 되어 콘택홀의 사이즈를 증대시키게 되는 또다른 문제점이 발생하였다.Another conventional method for solving this problem, 100 in the lower region during the contact hole etching Although a method of wet etching the remaining insulating film by using HF and buffer oxide etchant (BOE) has been proposed, the wet etching is performed to the side of the bottom of the contact hole during wet etching. Another problem has arisen that has been increased.
따라서, 본 발명은 종래의 문제점을 해결하기 위하여 안출된 것으로, 반도체 소자의 콘택홀의 제조 공정시, 콘택홀 사이즈의 증대 없이 기판의 손상을 최소화할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention has been made to solve the conventional problems, to provide a method for forming a contact hole of a semiconductor device that can minimize damage to the substrate without increasing the contact hole size during the manufacturing process of the contact hole of the semiconductor device. The purpose.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 반도체 소자를 구성하는 기본 전극이 구비된 반도체 기판상에 층간 절연막을 형성하고, 층간 절연막 상부에 콘택홀 형성용 마스크 패턴을 형성한다음, 마스크의 형태로 층간 절연막을 식각하여 콘택홀을 형성하는 반도체 소자의 콘택홀 형성방법에 있어서, 상기 절연막의 식각 공정은, 상기 층간 절연막을 하부에 일부분이 잔존하도록 건식 식각하는 단계; 상기 잔존하는 층간 절연막을 기상 식각 방식에 의한 이방성 식각하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention forms an interlayer insulating film on a semiconductor substrate provided with a base electrode constituting a semiconductor device, and forms a mask pattern for forming a contact hole on the interlayer insulating film, A method for forming a contact hole in a semiconductor device by etching an interlayer insulating film in the form of a contact, the etching process of the insulating film comprises: dry etching a portion of the interlayer insulating film to remain below; And performing anisotropic etching of the remaining interlayer insulating layer by a vapor phase etching method.
또한, 본 발명은 반도체 소자를 구성하는 기본 전극이 구비된 반도체 기판상에 층간 절연막을 형성하고, 층간 절연막 상부에 콘택홀 형성용 마스크 패턴을 형성한다음, 마스크의 형태로 층간 절연막을 식각하여 콘택홀을 형성하는 반도체 소자의 콘택홀 형성방법에 있어서, 상기 층간 절연막은 기상 식각 방식에 의하여 식각하는 것을 특징으로 한다.In addition, the present invention forms an interlayer insulating film on a semiconductor substrate provided with a basic electrode constituting a semiconductor device, and forms a mask pattern for forming a contact hole on the interlayer insulating film, and then etching the contact between the interlayer insulating film in the form of a mask. In the method for forming a contact hole of a semiconductor device to form a hole, the interlayer insulating film is etched by a gas phase etching method.
이하, 첨부한 도면에 의거하여 본 발명을 자세하게 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
[실시예 1]Example 1
첨부한 도면 제2(a)도 및 제2(b)도는 본 발명의 실시예 1에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 도면으로써, 먼저 제2(a)도에 도시된 바와 같이, 반도체 소자를 구성하는 필드 산화막(12), 게이트 절연막(13), 게이트 전극(14) 및 접합 영역(15)등이 형성된 반도체 기판(11) 상부에 층간 절연막(16)을 형성하고, 이어서, 하부의 토포로지를 감소시키기 위하여 평탄화 절연막(17) 예를들어, BPSG막을 형성한다. 그런다음, 상기 접합 영역이 노출될 수 있도록 마스크 패턴(도시되지 않음)을 형성하고, 이의 형태로 SF4, CHF3가스를 이용한 플라즈마 건식 식각을 진행한다. 이때, 식각 공정시 식각이 이루어지는 영역 하단에 층간 절연막의 일부분 예를들어 100정도의 잔여 산화막(16')이 존재하도록 식각한다.2 (a) and 2 (b) are diagrams for describing a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG. 2 (a). The interlayer insulating film 16 is formed on the semiconductor substrate 11 on which the field oxide film 12, the gate insulating film 13, the gate electrode 14, the junction region 15, etc., which constitute the semiconductor element, are formed. In order to reduce the underlying topology, the planarization insulating film 17, for example, a BPSG film is formed. Then, a mask pattern (not shown) is formed to expose the junction region, and plasma dry etching is performed using SF 4 and CHF 3 gas in the form thereof. At this time, a portion of the interlayer insulating film is formed at the bottom of the region where the etching is performed during the etching process It is etched so that a degree of residual oxide film 16 'is present.
이어서, 제2(b)도에 도시된 바와 같이, 상기 잔여 산화막(16')을 HF / CH3OH 용액에 의한 기상 식각(vapor etching) 방식 또는 HF / CH3OH / N2용액에 의한 기상 식각 방식으로 제거하여 콘택홀(18)을 형성한다. 그러면, 노출되는 기판부는 고밀도의 플라즈마 가스로 인한 손상을 방지할 수 있고, 등방성 식각에 의한 측부 식각의 문제점을 해결하여 소기의 효과를 얻을 수 있다.Subsequently, as shown in FIG. 2 (b), the residual oxide layer 16 'is vapor-deposited by HF / CH 3 OH solution or vapor phase by HF / CH 3 OH / N 2 solution. The contact hole 18 is formed by removing by etching. Then, the exposed substrate portion can prevent damage due to high-density plasma gas, and can solve the problem of side etching by isotropic etching, thereby obtaining a desired effect.
[실시예 2]Example 2
첨부한 도면 제3도는 본 발명의 실시예 2에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도로서, 도면에 도시된 바와 같이, 반도체 소자를 구성하는 필드 산화막(12), 게이트 절연막(13), 게이트 전극(14) 및 접합 영역(15)등이 형성된 반도체 기판(11) 상부에 층간 절연막(16)을 형성하고, 이어서, 하부의 토포로지를 감소시키기 위하여 평탄화 절연막(17) 예를들어, BPSG막을 형성한다. 그런다음, 상기 접합 영역이 노출될 수 있도록 마스크 패턴(도시되지 않음)을 형성한다. 이어서, 상기 마스크 패턴의 형태로 하부의 평탄화 산화막(17)과 층간 절연막(16)을 HF / CH3OH 용액을 이용한 기상(氣相) 식각(vapor etching) 방식 또는 HF / CH3OH / N2용액에 의한 기상 식각 방식으로 식각하여 콘택홀(18)을 형성한다. 그러면, 노출되는 기판부는 고밀도의 플라즈마 가스로 인한 손상을 방지할 수 있고, 등방성 식각에 의한 측부 식각의 문제점을 해결하여 소망하는 콘택홀을 형성할 수 있다.3 is a cross-sectional view illustrating a method for forming a contact hole in a semiconductor device according to a second exemplary embodiment of the present invention. As shown in the drawing, the field oxide film 12 and the gate insulating film 13 constituting the semiconductor device are shown. ), An interlayer insulating film 16 is formed on the semiconductor substrate 11 on which the gate electrode 14, the junction region 15, and the like are formed, and then the planarization insulating film 17 is reduced, for example, to reduce the topology of the lower layer. , A BPSG film is formed. Then, a mask pattern (not shown) is formed so that the junction region can be exposed. Subsequently, the lower planarization oxide layer 17 and the interlayer insulating layer 16 in the form of the mask pattern are vapor-etched using HF / CH 3 OH solution or HF / CH 3 OH / N 2. The contact hole 18 is formed by etching by a gas phase etching method using a solution. Then, the exposed substrate portion can prevent damage due to high-density plasma gas, and solve the problem of side etching due to isotropic etching to form a desired contact hole.
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 접합 영역에 손상이 발생하지 않는 콘택홀 형성시, 층간 절연막의 일부분이 잔존하도록 건식 식각하거나, 또는 건식 식각 공정없이 HF / CH3OH 또는 HF / CH3OH / N2용액에 의한 기상 식각 방식으로 층간 절연막을 식각하여 콘택홀로 노출되는 접합 영역에 데미지가 발생함을 방지하고, 습식 식각을 진행하여도 측부의 식각을 방지하여 소자의 특성을 향상시킨다.As described in detail above, according to the present invention, when forming a contact hole that does not cause damage to the junction region, dry etching is performed so that a part of the interlayer insulating film remains, or HF / CH 3 OH or HF / CH without a dry etching process. The interlayer insulating film is etched by the vapor phase etching method using 3 OH / N 2 solution to prevent damage to the junction region exposed to the contact hole, and the side part is prevented even by wet etching, thereby improving the device characteristics. .
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069469A KR100209279B1 (en) | 1995-12-30 | 1995-12-30 | Method for forming a contact of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069469A KR100209279B1 (en) | 1995-12-30 | 1995-12-30 | Method for forming a contact of semiconductor device |
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| Publication Number | Publication Date |
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| KR970052496A KR970052496A (en) | 1997-07-29 |
| KR100209279B1 true KR100209279B1 (en) | 1999-07-15 |
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| KR1019950069469A KR100209279B1 (en) | 1995-12-30 | 1995-12-30 | Method for forming a contact of semiconductor device |
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| KR (1) | KR100209279B1 (en) |
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| KR970052496A (en) | 1997-07-29 |
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