KR0154288B1 - Formation method of contact hole in semiconductor device - Google Patents
Formation method of contact hole in semiconductor device Download PDFInfo
- Publication number
- KR0154288B1 KR0154288B1 KR1019950018556A KR19950018556A KR0154288B1 KR 0154288 B1 KR0154288 B1 KR 0154288B1 KR 1019950018556 A KR1019950018556 A KR 1019950018556A KR 19950018556 A KR19950018556 A KR 19950018556A KR 0154288 B1 KR0154288 B1 KR 0154288B1
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- Prior art keywords
- contact hole
- semiconductor device
- insulating layer
- forming
- junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 콘택홀 내에서의 금속의 층덮힘 특성을 향상시키기 위해 이온주입에 의한 식각비(Etch Rate)의 증가를 이용하여 콘태홀(Contact Hole) 내부의 단차를 감소시키므로써 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. The present invention relates to a method of forming a contact hole in a contact hole using an increase in an etching rate by ion implantation in order to improve a layer covering property of a metal in the contact hole. The present invention relates to a method for forming a contact hole in a semiconductor device to improve the reliability of the device by reducing the step difference.
Description
제1a 내지 제1c도는 종래 반도체 소자의 콘택홀 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a contact hole in a conventional semiconductor device.
제2a 내지 제2d도는 본 발명에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 소자의 단면도.2A through 2D are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 11 : 실리콘기판 2, 12 : 접합부1, 11: silicon substrate 2, 12: junction
3, 13 : 절연층 4, 14 : 감광막3, 13 insulation layer 4, 14 photosensitive film
5, 15 : 콘택홀5, 15: contact hole
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 이온주입에 의한 식각비(Etch Rate)의 증가를 이용하여 콘택홀(Contact Hole) 내부의 단차를 감소시키므로써 금속의 층덮힘특성을 향상시킬 수 있도록 한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, by using an increase in the etching rate by ion implantation to reduce a step inside a contact hole, thereby improving metal layer covering characteristics. It relates to a method for forming a contact hole in a semiconductor device that can be made.
일반적으로 반도체 소자의 제조공정에서 접합부와 도전층 또는 도전층간의 사이에는 절연층이 형성되며, 접합부와 도전층 또는 도전층간의 접속은 절연층에 형성되는 콘택홀을 통해 이루어진다. 그런데 반도체 소자가 고집적화됨에 따라 콘택홀의 크기는 감소되는 반면에 절연층의 두께는 증가하기 때문에 콘택홀내에서의 단차는 더욱 증가하게 되며, 이로인해 콘택홀내에서 금속의 층덮힘특성(Step Coverage)이 저하된다. 그러면 이러한 금속의 층덮힘특성을 향상시키기 위해 사용하는 종래 반도체 소자의 콘택홀 형성방법을 제1a 내지 제1c도를 통해 설명하면 다음과 같다.In general, an insulating layer is formed between the junction and the conductive layer or the conductive layer in the manufacturing process of the semiconductor device, and the connection between the junction and the conductive layer or the conductive layer is made through a contact hole formed in the insulating layer. However, as semiconductor devices become highly integrated, the size of the contact hole decreases while the thickness of the insulating layer increases, so that the step height in the contact hole increases. As a result, the step coverage of the metal in the contact hole decreases. do. Next, a method of forming a contact hole of a conventional semiconductor device used to improve the layer covering characteristic of the metal will be described with reference to FIGS. 1A to 1C.
제1a 내지 제1c도는 종래 반도체 소자의 콘택홀 형성방법을 설명하기 위한 소자의 단면도로서, 제1a도는 접합부(2)가 형성된 실리콘기판(1)상에 절연층(3)이 형성된 상태에서 상기 접합부(2)와 상부에 형성될 도전층(도시않됨)과의 접속을 위한 콘택홀을 형성하기 위하여 상기 절연층(3)상에 감광막(4)을 도포하고, 콘택 마스크(도시않됨)를 이용하여 상기 감광막(4)을 패터닝한 상태의 단면도이다.1A to 1C are cross-sectional views of a device for describing a conventional method for forming a contact hole in a semiconductor device. FIG. 1A is a view illustrating the junction in a state in which an insulating layer 3 is formed on a silicon substrate 1 on which a junction 2 is formed. In order to form a contact hole for the connection between (2) and a conductive layer (not shown) to be formed thereon, a photosensitive film 4 is applied on the insulating layer 3, and a contact mask (not shown) is used. It is sectional drawing of the state which patterned the said photosensitive film 4.
제1b도는 상기 패터닝된 감광막(4)을 마스크로 이용하여 상기 절연층(3)을 소정 깊이 습식 식각(Wet Etch)한 상태의 단면도인데, 비등방성 식각에 의해 상기 절연층(3)의 상부가 곡면이 된다.FIG. 1B is a cross-sectional view of a wet depth of the insulating layer 3 by using the patterned photosensitive film 4 as a mask. An upper portion of the insulating layer 3 is formed by anisotropic etching. It becomes a surface.
제1c도는 상기 제1b도의 상태에서 상기 접합부(2)가 노출되는 시점까지 상기 절연층(3)을 건식 식각(Dry Etch)하여 콘택홀(5)을 형성한 후 상기 감광막(4)을 제거한 상태의 단면도인데, 상기 건식 식각은 등방성 식각이기 때문에 습식 식각된 부분과 건식 식각된 부분이 접하는 부분에 돌출부(A)가 형성되어 콘택홀(5) 내에서 금속의 층덮힘특성이 저하된다.1C is a state in which the contact layer 5 is formed by dry etching the insulating layer 3 until the junction portion 2 is exposed in the state of FIG. 1B, and then the photosensitive film 4 is removed. Since the dry etching is isotropic etching, a protrusion A is formed at a portion where the wet etched portion and the dry etched portion are in contact with each other, thereby lowering the layer covering property of the metal in the contact hole 5.
따라서 본 발명은 이온주입에 의한 식각비의 증가를 이용하여 콘택홀 내부의 단차를 감소시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device which can solve the above-mentioned disadvantages by reducing the step height inside the contact hole by using an increase in the etching ratio by ion implantation.
상기한 목적을 달성하기 위한 본 발명은 접합부가 형성된 실리콘기판상에 절연층이 형성된 상태에서 상기 접합부와 상부에 형성될 도전층과의 접속을 위한 콘택홀을 형성하기 위하여 상기 절연층상에 감광막을 도포하고, 콘택 마스크를 이용하여 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용하여 상기 절연층을 소정 깊이 습식 식각하는 단계와, 상기 단계로부터 상기 감광막의 패터닝된 부분과 일치하는 부위의 절연층에 이온이 주입되도록 경사 이온 주입공정을 실시하는 단계와, 상기 단계로부터 상기 접합부가 노출되는 시점까지 상기 절연층을 건식 식각하여 콘택홀을 형성한 후 상기 감광막을 제거하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to apply a photosensitive film on the insulating layer to form a contact hole for the connection between the junction portion and the conductive layer to be formed on the upper portion in the state where the insulating layer is formed on the silicon substrate formed a junction And patterning the photoresist film using a contact mask, wet etching the insulation layer by a predetermined depth using the patterned photoresist film as a mask, and matching the patterned portion of the photoresist film from the step. Performing an inclined ion implantation process to inject ions into the insulating layer at the site; dry etching the insulating layer from the step to a time point at which the junction is exposed to form a contact hole, and then removing the photoresist film. Characterized in that made.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 내지 제2d도는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도로서, 제2a도는 접합부(12)가 형성된 실리콘기판(11)상에 절연층(13)이 형성된 상태에서 상기 접합부(12)와 상부에 형성될 도전층(도시않됨)과의 접속을 위한 콘택홀을 형성하기 위하여 상기 절연층(13)상에 감광막(14)을 도포하고, 콘택 마스크(도시않됨)를 이용하여 상기 감광막(14)을 패터닝한 상태의 단면도이다.2A through 2D are cross-sectional views of a device for explaining a method of forming a contact hole in a semiconductor device according to the present invention. FIG. 2A is a view in which an insulating layer 13 is formed on a silicon substrate 11 on which a junction part 12 is formed. In order to form a contact hole for connecting the junction portion 12 and the conductive layer (not shown) to be formed thereon, a photosensitive film 14 is applied on the insulating layer 13, and a contact mask (not shown) It is sectional drawing of the patterned state of the said photosensitive film 14 using the following.
제2b도는 상기 패터닝된 감광막(14)을 마스크로 이용하여 상기 절연층(13)을 소정 깊이 습식 식각한 상태의 단면도인데, 비등방성 식각에 의해 상기 절연층(13)의 상부가 곡면이 된다.FIG. 2B is a cross-sectional view of the insulating layer 13 having a predetermined depth wet etching state using the patterned photosensitive film 14 as a mask, and the upper portion of the insulating layer 13 is curved by anisotropic etching.
제2c도는 상기 제2b도의 상태에서 직접 건식 식각을 진행할 경우 발생되는 돌출부위 즉, 상기 감광막(14)의 패터닝된 부분과 일치하는 부위의 절연층(13)에 인(P)과 같은 이온이 주입되도록 이온주입 각도를 좌, 우(실선 및 점선)로 조절하여 경사 이온 주입(Tilt Implant) 공정을 실시하는 상태의 단면도이다.FIG. 2C is a view illustrating the implantation of ions such as phosphorus (P) into the insulating layer 13 at the protrusion portion generated when the dry etching is performed directly in the state of FIG. 2B, that is, the portion corresponding to the patterned portion of the photosensitive film 14. It is sectional drawing of the state which performs the tilt implantation process by adjusting the ion implantation angle to left and right (solid line and a dotted line) as much as possible.
제2d도는 상기 접합부(2)가 노출되는 시점까지 상기 절연층(13)을 건식 식각하여 콘택홀(15)을 형성한 후 상기 감광막(14)을 제거한 상태의 단면도인데, 상기 식각공정시 이온이 주입된 부분의 절연층(13)은 식각비가 증가되어 형성되는 상기 콘택홀(15)의 양측벽은 경사면을 갖게 된다.2d is a cross-sectional view of the insulating layer 13 formed by dry etching the contact layer 15 until the junction portion 2 is exposed, and then removing the photosensitive layer 14. Both side walls of the contact hole 15 formed with the etch ratio of the insulating layer 13 of the injected portion have an inclined surface.
상술한 바와 같이 본 발명에 의하면 이온주입에 의한 식각비의 증가를 이용하여 콘택홀 내부의 단차를 감소시키므로써 금속의 층덮힘특성을 향상시켜 소자의 신뢰성이 향상될 수 있도록 하는 탁월한 효과가 있다.As described above, according to the present invention, there is an excellent effect of improving the layer covering property of the metal by reducing the step height inside the contact hole by using an increase in the etching ratio by ion implantation, thereby improving the reliability of the device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018556A KR0154288B1 (en) | 1995-06-30 | 1995-06-30 | Formation method of contact hole in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018556A KR0154288B1 (en) | 1995-06-30 | 1995-06-30 | Formation method of contact hole in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970003507A KR970003507A (en) | 1997-01-28 |
| KR0154288B1 true KR0154288B1 (en) | 1998-12-01 |
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| KR1019950018556A KR0154288B1 (en) | 1995-06-30 | 1995-06-30 | Formation method of contact hole in semiconductor device |
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| KR20030002715A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for forming a contact hole in a semiconductor device |
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