KR100244404B1 - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor device Download PDFInfo
- Publication number
- KR100244404B1 KR100244404B1 KR1019920026905A KR920026905A KR100244404B1 KR 100244404 B1 KR100244404 B1 KR 100244404B1 KR 1019920026905 A KR1019920026905 A KR 1019920026905A KR 920026905 A KR920026905 A KR 920026905A KR 100244404 B1 KR100244404 B1 KR 100244404B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- forming
- oxide film
- semiconductor device
- film
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
본 발명은 반도체 기판(21)에 산화막(23)을 형성한 후 건식식각으로콘택홀을 형성하고 감광막(24)으로 콘택홀을 메워 장벽을 만들어주는 제1단계, 상기 제1단계 후에 상기 산화막(23)이 드러나도록 건식식각하여 접촉면(D)과 첨점(C)을 형성하는 제2단계, 상기 제2단계 후에 상기 접촉면(D)과 첨점(C)을 습식식각을 하고 상기 감광막(24)을 제거하는 제3단계를 구비하고 있는 것을 특징으로 한다.According to the present invention, after the oxide film 23 is formed on the semiconductor substrate 21, the contact hole is formed by dry etching, and the contact hole is filled with the photosensitive film 24 to form a barrier, and after the first step, the oxide film ( 23) dry etching to reveal the contact surface (D) and the peaks (C), and after the second step wet etching the contact surface (D) and the peaks (C) and the photoresist film (24) And a third step of removing.
Description
제1도는 종래의 반도체 소자의 콘택홀 단면도.1 is a cross-sectional view of a contact hole of a conventional semiconductor device.
제2도 내지 제5도는 본 발명의 일실시 예에 따른 반도체 소자의 콘택홀 형성 공정 단면도.2 to 5 are cross-sectional views of a contact hole forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21 : 반도체 기판 12, 22 : N+또는 P+불순물 도핑 영역11, 21: semiconductor substrate 12, 22: N + or P + impurity doped region
13, 23 : 산화막 24 : 감광막13, 23: oxide film 24: photosensitive film
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device.
일반적으로 반도체 소자의 집적도가 증진될수록 콘택사이즈는 감소하고 콘택 깊이는 깊어진다.In general, as the degree of integration of semiconductor devices increases, the contact size decreases and the contact depth deepens.
종래의 반도체 소자의 콘택홀 형성 방법을 제1도를 통해 상세히 살명한다. 도면에서 11은 반도체 기판, 12는 N+또는 P+불순물 도핑 영역, 13은 산화막을 각각 나타낸다. 먼저, 반도체 기판(11)에 산화막(13)을 형성하고 감광막 등으로 식각 마스크(도시하지 않음)를 형성한 후, 습식식각을 실시하여 콘택홀 입구 부분에 단차비(aspect ratio)를 낮춘 후, 건식식각을 실시하여 콘택홀을 형성한다.A conventional method for forming a contact hole in a semiconductor device will be described in detail with reference to FIG. 1. In the figure, 11 represents a semiconductor substrate, 12 represents an N + or P + impurity doped region, and 13 represents an oxide film, respectively. First, an oxide film 13 is formed on the semiconductor substrate 11, an etch mask (not shown) is formed of a photoresist film, or the like, and then wet etching is performed to lower the aspect ratio at the contact hole inlet. Dry etching is performed to form contact holes.
상기 종래의 콘택홀 형성방법은 첨점 A, B가 형성되어 배선층의 열화된 스텝커버리지로 인하여 배선의 단락을 유발시키는 문제점이 있었다.The conventional method for forming a contact hole has a problem in that cusps A and B are formed to cause a short circuit of the wiring due to deteriorated step coverage of the wiring layer.
상기 문제점을 해결하기 위하여 안출된 본 발명은 단차비를 낮추고 첨점을 제거하며 하층막의 손실을 줄일 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a contact hole in a semiconductor device that can reduce the step ratio, remove the peaks and reduce the loss of the underlayer.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자의 콘택홀 형성 방법에 있어서, 반도체 기판에 산화막을 형성한 후 건식식각으로 상기 산화막을 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 산화막 표면 및 콘택홀내에 감광막을 형성하는 단계; 상기 감광막을 식각하여 상기 산화막 표면이 드러나도록 하며 상기 콘택홀 내에만 감광막이 남도록하는 단계; 상기 노출된 산화막을 습식식각하여 첨점이 없는 콘택홀을 형성하는 단계; 및 상기 감광막을 제거하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of forming a contact hole in a semiconductor device, the method comprising: forming a contact hole by selectively etching the oxide film by dry etching after forming an oxide film on a semiconductor substrate; Forming a photosensitive film in the oxide film surface and in the contact hole; Etching the photoresist to expose the oxide film surface and leaving the photoresist only in the contact hole; Wet etching the exposed oxide layer to form a contact hole having no point; And removing the photosensitive film.
이하, 첨부된 도면을 참조하여 본 발명의 일실시 예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제2도 내지 제5도는 본 발명의 일실시 예에 따른 반도체 소자의 콘택홀 형성 공정 단면도로서, 도면에서 21은 반도체 기판, 22는 N+또는 P+불순물 도핑 영역, 23은 산화막, 24는 감광막을 각각 나타낸다.2 to 5 are cross-sectional views of a contact hole forming process of a semiconductor device according to an embodiment of the present invention, in which 21 is a semiconductor substrate, 22 is an N + or P + impurity doped region, 23 is an oxide film, and 24 is a photosensitive film. Respectively.
제2도는 반도체 기판(21)에 산화막(23)을 형성하고 건식식각으로 상기 산화막(23)을 선택적으로 제거하여 상기 N+또는 P+불순물 도핑 영역(23)을 노출하는 콘택홀을 형성한 후 감광막(24)으로 콘택홀을 메우상태를 나타내는 단면도이다. 이때, 감광막으로 콘택홀을 메우기 전, 후에 접착력 개선을 위한 공정을 하지 않는다.FIG. 2 illustrates the formation of a contact hole exposing the N + or P + impurity doped region 23 by forming an oxide layer 23 on the semiconductor substrate 21 and selectively removing the oxide layer 23 by dry etching. It is sectional drawing which shows the contact hole filling up the photosensitive film 24. FIG. At this time, before or after filling the contact hole with the photosensitive film, a process for improving adhesive strength is not performed.
제3도는 상기 산화막(23)이 드러나도록 건식식각으로 상기 감광막(24)을 식각한 상태의 단면도이다. 이때 상기 콘택홀 내부에만 상기 감광막(24)이 남도록 한다. 미설명 도면 부호 C는 콘택홀 입구의 첨점을, D는 감광막과 절연막이 이루는 경계점을 각각 나타낸다.3 is a cross-sectional view of the photosensitive film 24 etched by dry etching so that the oxide film 23 is exposed. At this time, the photoresist layer 24 remains only inside the contact hole. Reference numeral C denotes the peak of the contact hole inlet, and D denotes the boundary between the photosensitive film and the insulating film.
제4도는 습식식각을 실시하여 첨점(D) 및 경계점(D)을 제거한 상태(E,F)의 단면도이다.4 is a cross-sectional view of a state (E, F) in which wet point (D) and boundary point (D) are removed by wet etching.
제5도는 상기 콘택홀 내에 남은 감광막을 제거한 상태의 단면도이다. 이와 같은 방법으로 형성되는 콘택홀은 첨점이 제거되어 금속 배선의 단락을 방지할 수 있다.5 is a cross-sectional view of a state in which the photosensitive film remaining in the contact hole is removed. The contact hole formed in this manner can be removed to prevent the short-circuit of the metal wiring by removing the point.
상기와 같이 이루어지는 본 발명은 어스펙트비를 낮추고 첨점을 없애고 하층막의 손실을 줄인 콘택홀을 형성시킴으로써 반도체 소자의 고집적도를 실현할 수 있는 효과가 있다.The present invention as described above has the effect of achieving a high integration degree of the semiconductor device by forming a contact hole which lowers the aspect ratio, eliminates the point and reduces the loss of the underlayer film.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920026905A KR100244404B1 (en) | 1992-12-30 | 1992-12-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920026905A KR100244404B1 (en) | 1992-12-30 | 1992-12-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940016694A KR940016694A (en) | 1994-07-23 |
| KR100244404B1 true KR100244404B1 (en) | 2000-02-01 |
Family
ID=19348054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920026905A KR100244404B1 (en) | 1992-12-30 | 1992-12-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100244404B1 (en) |
-
1992
- 1992-12-30 KR KR1019920026905A patent/KR100244404B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR940016694A (en) | 1994-07-23 |
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