KR100256241B1 - Method of forming contact hole with inclined space in semiconductor device - Google Patents

Method of forming contact hole with inclined space in semiconductor device Download PDF

Info

Publication number
KR100256241B1
KR100256241B1 KR1019920027336A KR920027336A KR100256241B1 KR 100256241 B1 KR100256241 B1 KR 100256241B1 KR 1019920027336 A KR1019920027336 A KR 1019920027336A KR 920027336 A KR920027336 A KR 920027336A KR 100256241 B1 KR100256241 B1 KR 100256241B1
Authority
KR
South Korea
Prior art keywords
contact hole
photoresist pattern
etching
insulating layer
forming
Prior art date
Application number
KR1019920027336A
Other languages
Korean (ko)
Other versions
KR940016508A (en
Inventor
김명선
김진웅
설여송
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019920027336A priority Critical patent/KR100256241B1/en
Publication of KR940016508A publication Critical patent/KR940016508A/en
Application granted granted Critical
Publication of KR100256241B1 publication Critical patent/KR100256241B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE: A method for forming a contact hole is to improve the reliability of a semiconductor device by reducing a leakage current and a short-circuit of a metal connected to a contact hole. CONSTITUTION: An insulating layer(3) is formed on a semiconductor substrate with a lower layer formed thereon. A silicon layer(2) is deposited on the insulating layer to prevent damage of the insulating layer in an etching process. A photoresist pattern is formed to form a contact hole. The silicon layer is etched by using the photoresist pattern as an etching stop layer. A part of the insulating layer is removed by dry etching. Here, a lower part of the insulating layer is not exposed, thereby forming a part of a contact hole having the same width as that of the exposed photoresist pattern. After removing the photoresist pattern, the lower part of the insulating layer is exposed by blanket etching. Thereby, a contact hole having a slope is formed.

Description

반도체 장치의 경사면을 갖는 콘택홀 형성 방법Method for forming contact hole having inclined surface of semiconductor device

제1도는 본 발명의 일실시 예에 따른 반도체 장치의 콘택홀 형성 공정 단면도.1 is a cross-sectional view illustrating a process of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 감광막 2 : 실리콘막1 photosensitive film 2 silicon film

3 : 절연막3: insulation film

본 발명은 금속의 스텝 커버리지(Step Coverage)를 향상시키기 위한 반도체 장치의 경사면을 갖는 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole having an inclined surface of a semiconductor device for improving step coverage of a metal.

종래의 경사면을 갖는 콘택홀 형성 방법은 콘택홀 입구 부분에 경사를 만들기 위해, 식각 마스크를 형성한 후 습식 식각을 실시한 후 건식 식각으로 콘택홀을 형성하거나 또는 건식 식각만으로 콘택홀을 형성한 후, 식각 마스크를 제거하고 감광막을 도포하여 전면(blanket) 식각을 실시하는 방법을 이용하여 왔다.In the conventional method of forming a contact hole having an inclined surface, after forming an etching mask and performing wet etching after forming an inclination at the contact hole inlet, the contact hole is formed by dry etching or by forming only the contact hole by dry etching. A method of removing the etching mask and applying a photoresist to perform a blanket etching has been used.

그러나, 상기 종래의 방법은 식각 공정시간이 길고, 표면상태에 여러 문제점들을 발생시키며, 콘택홀 형성으로 하부층이 드러난 후에 전면 식각을 실시하여 과도 식각시에 의한 하부층의 손상으로 누설전류의 증가를 가져오는 문제점이 있었다.However, the conventional method has a long etching process time and causes various problems in the surface state, and after the lower layer is exposed by contact hole formation, the entire surface is etched to increase the leakage current due to damage of the lower layer during excessive etching. There was a problem coming.

상기 문제점을 해결하기 위하여 안출된 본 발명은 콘택홀에 접속되어지는 금속의 단락 및 누설전류를 감소시켜 반도체 소자의 신뢰성을 증가시킬 수 있는 반도체 장치의 경사면을 갖는 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems provides a method for forming a contact hole having an inclined surface of a semiconductor device that can increase the reliability of the semiconductor device by reducing the short circuit and leakage current of the metal connected to the contact hole. There is this.

상기 목적을 달성하기 위하여 본 발명은, 반도체 장치의 경사면을 갖는 콘택홀 형성 방법에 있어서, 반도체 기판 상에 형성된 절연막 상에 실리콘막을 증착하고 콘택홀을 형성하기 위한 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 식각 마스크로 상기 실리콘막을 등방성 식각하여 상기 감광막 패턴으로 노출되는 폭보다 넓게 상기 실리콘막을 제거하는 단계; 상기 감광막 패턴을 식각마스크로 상기 절연막을 건식식각하되 절연막의 하부층이 노출되지 않도록 상기 절연막의 일부를 제거하며, 상기 감광막 패턴으로 노출된 폭과 동일한 크기의 폭을 갖는 콘택홀의 일부를 형성하는 단계; 및 상기 감광막 패턴을 제거하고, 상기 절연막을 전면 식각하여 절연막의 하부층이 드러나도록하며 콘택홀 입구에 경사면을 갖는 콘택홀을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method for forming a contact hole having an inclined surface of a semiconductor device, comprising: forming a photoresist pattern for depositing a silicon film on an insulating film formed on a semiconductor substrate and forming a contact hole; Isotropically etching the silicon film using the photoresist pattern as an etch mask to remove the silicon film wider than the width exposed by the photoresist pattern; Dry etching the insulating layer using the photoresist pattern as an etch mask, but removing a portion of the insulating layer so that the lower layer of the insulating layer is not exposed, and forming a portion of the contact hole having a width equal to the width exposed by the photoresist pattern; And removing the photoresist pattern, etching the entire insulating layer to expose the lower layer of the insulating layer, and forming a contact hole having an inclined surface at the entrance of the contact hole.

이하, 첨부된 도면 제 1 도를 참조하여 본 발명에 따른 일실시예를 상세히 설명한다. 도면에서 1은 감광막, 2는 실리콘막, 3은 절연막을 각각 나타낸다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 1. In the figure, 1 represents a photosensitive film, 2 represents a silicon film, and 3 represents an insulating film.

먼저, 제 1 도(a)와 같이 소정의 하부층이 형성된 반도체 기판(도시하지 않음) 상에 절연막(3)을 형성한 후, 상기 절연막(3) 상에 이후의 식각 공정에서 절연막 손실을 방지하기 위하여 실리콘막(2)을 증착시키고, 감광막(1)을 도포하여 식각방지막인 감광막 패턴을 형성한다. 여기서 상기 실리콘막(3)은 다결정 실리콘막 또는 비정질 실리콘막으로 이루어 진다.First, as shown in FIG. 1A, an insulating film 3 is formed on a semiconductor substrate (not shown) on which a predetermined lower layer is formed, and then an insulating film is prevented on the insulating film 3 in a subsequent etching process. In order to deposit the silicon film 2, the photosensitive film 1 is applied to form a photoresist pattern as an etch stop film. The silicon film 3 is made of a polycrystalline silicon film or an amorphous silicon film.

다음으로, 제 1 도(b)에 도시된 바와 같이 상기 감광막(1) 패턴을 식각 방지막으로 상기 실리콘막(2)을 식각한다. 이때 실리콘막(2)의 식각은 SF6와 같은 등방성을 갖는 식각기체로 실시하여, 상기 감광막(1) 패턴으로 노출되지 않는 소정 영역까지 실리콘막(2)이 식각되도록 한다.Next, as illustrated in FIG. 1B, the silicon layer 2 is etched using the photoresist layer 1 pattern as an etch stop layer. At this time, the etching of the silicon film 2 is performed using an etching gas having an isotropy such as SF 6 so that the silicon film 2 is etched to a predetermined area not exposed by the photosensitive film 1 pattern.

다음으로, 제 1 도(c)에 도시한 바와 같이 일반적인 절연층 식각 방법으로 상기 절연막(3)을 건식식각하여 절연막의 일부분을 제거한다. 즉, 이때 절연막(3)식각으로 하부층이 드러나지 않도록 콘택홀의 일부분만을 형성한다.Next, as shown in FIG. 1C, a portion of the insulating film is removed by dry etching the insulating film 3 by a general insulating layer etching method. That is, only a portion of the contact hole is formed so that the lower layer is not exposed by etching the insulating film 3.

이어서, 제 1 도(d)에 도시한 바와 같이 상기 감광막(1)을 제거한다.Next, as shown in FIG. 1 (d), the photosensitive film 1 is removed.

다음으로, 제 1 도(e)에 도시한 바와 같이 상기 실리콘막(2)으로 덮이지 않고 노출되어져 있는 절연막(3)을 하부층이 드러날 때까지 식각하여 콘택홀을 형성한다. 상기 콘택홀 형성을 위한 절연막 식각시 수직방향인 90°의 식각 속도보다는 45°방향의 식각 속도가 2배 이상 빠르기 때문에 콘택홀 입구에 경사면이 형성된다.Next, as shown in FIG. 1E, the exposed insulating film 3, which is not covered with the silicon film 2, is etched until the lower layer is exposed to form a contact hole. When the insulating layer is etched to form the contact hole, the inclined surface is formed at the inlet of the contact hole because the etching speed in the 45 ° direction is more than twice faster than the 90 ° in the vertical direction.

이때 노출되어 있지 않은 상기 절연막(3)은 상기 실리콘막(2)이 식각 장벽역할을 하게 됨으로 손실이 거의 없게 된다. 또한, 상기 실리콘막(2)은 그 두께가 얇으므로 콘택홀 형성에 의한 과도 식각시에 제거되거나, 또는 추가 식각 단계를 실시하여 쉽게 제거할 수 있으며, 제거하지 않은 상태에서 금속막을 적층하여, 금속막 식각 공정에서 식각하여도 된다.In this case, the insulating layer 3 which is not exposed has almost no loss since the silicon layer 2 serves as an etching barrier. In addition, since the thickness of the silicon film 2 is thin, it may be removed during excessive etching due to contact hole formation, or may be easily removed by performing an additional etching step. You may etch in a film etching process.

절연막의 식각 속도가 90°방향보다는 45°방향이 훨씬 빠르다는 점을 이용하여 경사면을 형성했기 때문에 원하는 만큼의 경사면을 만들기 위해서는 절연막의 90°방향의 손실이 발생하게 되는데, 이는 P/R을 도포함으로써 방지할 수 있다.Since the inclined surface was formed using the etching speed of the insulating film is much faster than the 45 ° direction than the 90 ° direction, the loss of the 90 ° direction of the insulating film occurs in order to make as many inclined surfaces as desired. This can be prevented.

상기와 같이 이루어지는 본 발명은 실리콘막을 식각 장벽막으로 사용하고, 90°방향과 45°방향의 식각 속도비를 이용하여 절연막의 손실 없이 콘택홀 내의 경사면을 형성하고, 하부층의 손실을 방지하는 것이 가능하여 금속의 단락을 방지하며 반도체 소자의 신뢰도를 증가 시키는 효과가 있다.According to the present invention made as described above, by using a silicon film as an etch barrier film, by using an etching rate ratio in the 90 ° direction and the 45 ° direction, it is possible to form an inclined surface in the contact hole without losing the insulating film, and to prevent the loss of the lower layer. This prevents the short circuit of metal and increases the reliability of the semiconductor device.

Claims (3)

반도체 기판 상에 형성된 절연막 상에 실리콘막을 증착하고 콘택홀을 형성하기 위한 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 식각 마스크로 상기 실리콘막을 등방성 식각하여 상기 감광막 패턴으로 노출되는 폭보다 넓게 상기 실리콘막을 제거하는 단계; 상기 감광막 패턴을 식각마스크로 상기 절연막을 건식식각하되 절연막의 하부층이 노출되지 않도록 상기 절연막의 일부를 제거하며, 상기 감광막 패턴으로 노출된 폭과 동일한 크기의 폭을 갖는 콘택홀의 일부를 형성하는 단계; 및 상기 감광막 패턴을 제거하고, 상기 절연막을 전면 식각하여 절연막의 하부층이 드러나도록하며, 콘택홀 입구에 경사면을 갖는 콘택홀을 형성하는 단계를 포함하여 이루어지는 반도체 장치의 경사면을 갖는 콘택홀 형성 방법.Depositing a silicon film on an insulating film formed on the semiconductor substrate and forming a photoresist pattern for forming contact holes; Isotropically etching the silicon film using the photoresist pattern as an etch mask to remove the silicon film wider than the width exposed by the photoresist pattern; Dry etching the insulating layer using the photoresist pattern as an etch mask, but removing a portion of the insulating layer so that the lower layer of the insulating layer is not exposed, and forming a portion of the contact hole having a width equal to the width exposed by the photoresist pattern; And removing the photoresist pattern, etching the entire insulating film to expose the lower layer of the insulating film, and forming a contact hole having an inclined surface at a contact hole inlet. 제1항에 있어서, 상기 감광막 패턴을 제거한 후 실시하는 절연막 식각은 수직방향인 90°의 식각 속도보다 45°방향의 식각 속도가 2배 이상 빠르게 이루어지도록 실시하는 반도체 장치의 경사면을 갖는 콘택홀 형성 방법.2. The contact hole formation method of claim 1, wherein the etching of the insulating layer after removing the photoresist pattern is performed such that the etching speed in the 45 ° direction is more than two times faster than the etching speed of 90 ° in the vertical direction. Way. 제1항에 있어서, 상기 실리콘막을 SF6가스를 사용하여 식각하는 반도체 장치의 경사면을 갖는 콘택홀 형성 방법.The method of claim 1, further comprising an inclined surface of the semiconductor device to etch the silicon film using SF 6 gas.
KR1019920027336A 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device KR100256241B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027336A KR100256241B1 (en) 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027336A KR100256241B1 (en) 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device

Publications (2)

Publication Number Publication Date
KR940016508A KR940016508A (en) 1994-07-23
KR100256241B1 true KR100256241B1 (en) 2000-05-15

Family

ID=19348500

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027336A KR100256241B1 (en) 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device

Country Status (1)

Country Link
KR (1) KR100256241B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414949B1 (en) * 1996-12-28 2004-03-31 주식회사 하이닉스반도체 Method for forming contact hole of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414949B1 (en) * 1996-12-28 2004-03-31 주식회사 하이닉스반도체 Method for forming contact hole of semiconductor device

Also Published As

Publication number Publication date
KR940016508A (en) 1994-07-23

Similar Documents

Publication Publication Date Title
KR20010058774A (en) Method for manufacturing semiconductor device
KR100256241B1 (en) Method of forming contact hole with inclined space in semiconductor device
KR100289660B1 (en) Trench Formation Method for Semiconductor Devices
KR100587036B1 (en) Contact formation method of semiconductor device
KR100245075B1 (en) Method of forming an element field oxide film in a semiconductor device
KR100426490B1 (en) Method for forming contact hole of semiconductor device
KR960008563B1 (en) Fine contact hall forming method of semiconductor using double spacer
KR100367694B1 (en) Method for manufacturing contact in semiconductor device
KR0182176B1 (en) Method for forming meatal contact hall of semiconductor device
KR100244404B1 (en) Manufacture of semiconductor device
KR960002071B1 (en) Contact forming method of semiconductor device
KR100209279B1 (en) Method for forming a contact of semiconductor device
KR100529569B1 (en) Manufacturing method of thin film transistor for liquid crystal display device
KR100202657B1 (en) Manufacturing method of transistor
KR0137433B1 (en) Contact hole fabrication method of semiconductor device
KR100314738B1 (en) Method for forming gate electrode in semiconductor device
KR100298427B1 (en) Method for fabricating semiconductor device
KR0137980B1 (en) Fabrication method of tungsten plug
KR100192439B1 (en) Method for forming a contact hole of a semiconductor device
KR0147424B1 (en) Formation method of self-alignment contact in semiconductor device
KR100604759B1 (en) Method for manufacturing semiconductor device
KR100400763B1 (en) Method for manufacturing capacitor of semiconductor device
KR100316181B1 (en) Method for forming tungsten plug
KR0156168B1 (en) Capacitor manufacture method of dram
KR920008400B1 (en) Wet etch-back method of blanket tungsten for via-filling

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080102

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee