KR940016508A - Method for manufacturing a contact of a semiconductor device having an inclined surface - Google Patents

Method for manufacturing a contact of a semiconductor device having an inclined surface Download PDF

Info

Publication number
KR940016508A
KR940016508A KR1019920027336A KR920027336A KR940016508A KR 940016508 A KR940016508 A KR 940016508A KR 1019920027336 A KR1019920027336 A KR 1019920027336A KR 920027336 A KR920027336 A KR 920027336A KR 940016508 A KR940016508 A KR 940016508A
Authority
KR
South Korea
Prior art keywords
film
etching
contact
silicon film
insulating film
Prior art date
Application number
KR1019920027336A
Other languages
Korean (ko)
Other versions
KR100256241B1 (en
Inventor
김명선
김진웅
설여송
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027336A priority Critical patent/KR100256241B1/en
Publication of KR940016508A publication Critical patent/KR940016508A/en
Application granted granted Critical
Publication of KR100256241B1 publication Critical patent/KR100256241B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 콘택 접속을 이룰 전도층위에 절연막(3)이 도포되어 있는 상태의 경사면을 갖는 반도체 소자의 콘택 제조 방법에 있어서, 상기 절연막(3) 상에 실리콘막(2)을 증착하고 감광막(1)을 도포하여 콘택 패턴을 형성하는 제 1 단계, 상기 제 1 단계 후에 감광막(1) 패턴을 이용하여 상기 실리콘막(2)을 식각하되 상기 감광막(1) 패턴을 보다 넓게 식각하는 제 2 단계, 상기 제 2 단계 후에 상기 절연막(3)을 부분 건식식각하여 상기 실리콘막(2)의 식각폭 보다 좁게 식각하는 제 3 단계, 및 상기 제 3 단계 후에 상기 감광막(1)을 제거하고, 노출되어져 있는 상기 절연막(3)을 과도식각하는 제 4 단계를 포함하여 이루어지는 것을 특징으로 하는 경사면을 갖는 반도체 소자의 콘택 제조 방법에 관한 것이다.The present invention provides a contact manufacturing method for a semiconductor device having an inclined surface in which the insulating film 3 is applied on a conductive layer to form a contact connection, wherein the silicon film 2 is deposited on the insulating film 3 and the photosensitive film 1 A second step of etching the silicon film 2 using the photosensitive film 1 pattern after the first step to form a contact pattern by applying a second step; After the second step, the insulating film 3 is partially dry-etched to etch narrower than the etching width of the silicon film 2, and after the third step, the photosensitive film 1 is removed and exposed. And a fourth step of overetching the insulating film (3).

Description

경사면을 갖는 반도체 소자의 콘택 제조 방법Method for manufacturing a contact of a semiconductor device having an inclined surface

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 반도체 소자의 콘택 제조 공정도.1 is a contact manufacturing process diagram of a semiconductor device according to the present invention.

Claims (5)

콘택 접속을 이룰 전도층위에 절연막(3)이 도포되어 있는 상태의 경사면을 갖는 반도체 소자의 콘택 제조 방법에 있어서, 상기 절연막(3) 상에 실리콘막(2)을 증착하고 감광막(1)을 도포하여 콘택 패턴을 형성하는 제 1 단계, 상기 제 1 단계 후에 감광막(1) 패턴을 이용하여 상기 실리콘막(2)을 식각하되 상기 감광막(1) 패턴폭 보다 넓게 식각하는 제 2 단계, 상기 제 2 단계 후에 상기 절연막(3)을 부분 건식식각하여 상기 실리콘막(2)의 식각폭 보다 좁게 식각하는 제 3 단계, 및 상기 제 3 단계 후에 상기 감광막(1)을 제거하고, 노출되어져 있는 상기 절연막(3)을 과도식각하는 제 4 단계를 포함하여 이루어지는 것을 특징으로 하는 경사면을 갖는 반도체 소자의 콘택 제조 방법.In the method for manufacturing a contact of a semiconductor device having an inclined surface in which the insulating film 3 is coated on the conductive layer to make contact connection, a silicon film 2 is deposited on the insulating film 3 and the photosensitive film 1 is coated. A second step of etching the silicon film 2 using the photosensitive film 1 pattern after the first step and forming a contact pattern to be wider than the pattern width of the photosensitive film 1. A third step of etching the insulating film 3 to be narrower than the etching width of the silicon film 2 after the step, and removing the photosensitive film 1 after the third step, and exposing the exposed insulating film ( And a fourth step of overetching 3). 제 1 항에 있어서, 상기 제 1 단계의 실리콘막(2)은 다결정 실리콘막 또는 비정질 실리콘막인 것을 특징으로 하는 경사면을 갖는 반도체 소자의 콘택 제조 방법.2. The method of claim 1, wherein the silicon film (2) of the first step is a polycrystalline silicon film or an amorphous silicon film. 제 1 항에 있어서, 상기 제 2 단계의 실리콘막(2) 식각의 식각제는 등방성을 갖는 식각기체인 것을 특징으로 하는 경사면을 갖는 반도체 소자의 콘택 제조 방법.2. The method of claim 1, wherein the etchant for etching the silicon film (2) in the second step is an etching gas having isotropy. 제 1 항에 있어서, 상기 제 4 단게의 절연막(3) 과도식각은 수직방향인 90°의 식각 속도보다는 45°방향의 식각 속도가 2배 이상 빠르게 식각되어지는 것을 특징으로 하는 경사면을 갖는 반도체 소자의 콘택 제조 방법.2. The semiconductor device according to claim 1, wherein the transient etching of the insulating film 3 of the fourth step is performed by etching more than twice as fast as the etching speed of 90 degrees in the vertical direction. Contact manufacturing method. 제 3 항에 있어서, 상기 실리콘막(2) 식각에 사용되는 등방성 식각기체는 SF6인 것을 특징으로 하는 경사면을 갖는 반도체 소자의 콘택 제조 방법.The method of claim 3, wherein the isotropic etching gas used in the silicon film 2, an etching method for manufacturing a semiconductor device having a contact inclined surface, characterized in that SF 6. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027336A 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device KR100256241B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027336A KR100256241B1 (en) 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027336A KR100256241B1 (en) 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device

Publications (2)

Publication Number Publication Date
KR940016508A true KR940016508A (en) 1994-07-23
KR100256241B1 KR100256241B1 (en) 2000-05-15

Family

ID=19348500

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027336A KR100256241B1 (en) 1992-12-31 1992-12-31 Method of forming contact hole with inclined space in semiconductor device

Country Status (1)

Country Link
KR (1) KR100256241B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414949B1 (en) * 1996-12-28 2004-03-31 주식회사 하이닉스반도체 Method for forming contact hole of semiconductor device

Also Published As

Publication number Publication date
KR100256241B1 (en) 2000-05-15

Similar Documents

Publication Publication Date Title
KR950015715A (en) Method of forming device isolation film in semiconductor device
KR970052489A (en) Wiring Structure of Semiconductor Device and Formation Method
KR940016508A (en) Method for manufacturing a contact of a semiconductor device having an inclined surface
KR950034415A (en) Manufacturing method of fine pattern of semiconductor device
KR940022702A (en) Metal wiring formation method of semiconductor device
KR960030327A (en) Contact hole formation method of semiconductor device
KR950021522A (en) Method for forming fine conductive line in semiconductor device
KR940001268A (en) Self-aligned contact formation method of semiconductor device
KR970018032A (en) Small contact formation method of semiconductor device
KR930024106A (en) Contact Forming Method of Semiconductor Device
KR970052317A (en) Method for forming micro contact window of semiconductor device
KR940016470A (en) Method for forming contact hole with inclined surface
KR950021090A (en) Contact hole formation method of semiconductor device
KR970077456A (en) Method of forming a contact hole in a semiconductor device
KR960002547A (en) Contact hole formation method of semiconductor device
KR940010366A (en) Method for manufacturing contact hole of semiconductor device
KR970003851A (en) Metal wiring formation method of semiconductor device
KR960001884A (en) Fine contact hole formation method
KR940016483A (en) How to Form Metal Plugs
KR970054071A (en) Cell Capacitor Formation Method of Semiconductor Device Using Double Spacer
KR970054601A (en) Metal layer patterning method in semiconductor device manufacturing process
KR950021096A (en) Contact hole formation method of semiconductor device
KR970053509A (en) Method of forming multiple metal layers in semiconductor devices
KR970052274A (en) Method for forming fine contact and conductive line in semiconductor device
KR960005784A (en) Buried contact hole formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080102

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee