KR970003851A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR970003851A
KR970003851A KR1019950018540A KR19950018540A KR970003851A KR 970003851 A KR970003851 A KR 970003851A KR 1019950018540 A KR1019950018540 A KR 1019950018540A KR 19950018540 A KR19950018540 A KR 19950018540A KR 970003851 A KR970003851 A KR 970003851A
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KR
South Korea
Prior art keywords
photoresist film
forming
semiconductor device
etching
metal
Prior art date
Application number
KR1019950018540A
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Korean (ko)
Inventor
조승건
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950018540A priority Critical patent/KR970003851A/en
Publication of KR970003851A publication Critical patent/KR970003851A/en

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Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 낫칭 및 넥킹 현상의 발생으로 인한 불량을 방지하기 위하여 절연층에 소정 깊이의 트렌치 (Trench)를 형성하고, 그 트렌치 내부에 금속(Metal)을 매립시키므로써 소자의 수율 및 전기적특성을 향상시킬 수 있도록 한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and to form a trench of a predetermined depth in an insulating layer in order to prevent a defect due to the hardening and necking phenomenon, and to form a metal in the trench The present invention relates to a method for forming metal wirings in a semiconductor device, which allows the device to improve yield and electrical characteristics of the device by being buried.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A 내지 제2E도는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.2A through 2E are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 금속배선 형성방법에 있어서, 접합부가 형성된 실리콘기판상에 절연층이 형성된 상태에서, 전체 상부면에 제1감광막을 도포한 후 금속배선용 마스크를 이용하여 상기 제1감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 제1감광막을 마스크로 이용한 식각공정으로 상기 절연층을 식각하여 소정 깊이의 트렌치를 형성하는 단계와, 상기 단계로부터 상기 제1감광막을 제거한 후 전체 상부면에 제2감광막을 도포하고 콘택 마스크를 이용하여 상기 제2감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 제2감광막을 도포하고 콘택 마스크로 이용한 식각공정으로 상기 접합부가 노출되도록 상기 절연층을 식각하여 콘택홀을 형성하는 단계와, 상기 단계로부터 상기 콘택홀이 매립되도록 전체 상부면에 금속층을 형성한 후 제3감광막을 도포하여 전체 상부면을 평탄화시키는 단계와, 상기 단계로부터 상기 실리콘기판의 표면이 노출되는 시점까지 상기 제3감광막 및 금속층을 전면식각하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.A method of forming a metal wiring in a semiconductor device, the method comprising: applying a first photoresist film to an entire upper surface of an insulating layer on a silicon substrate on which a junction is formed, and then patterning the first photoresist film using a metal wiring mask; And forming a trench having a predetermined depth by etching the insulating layer by an etching process using the patterned first photoresist film as a mask, removing the first photoresist film from the step, and then forming a second photoresist film on the entire upper surface thereof. Applying a contact mask and patterning the second photoresist film using a contact mask; and applying the patterned second photoresist film from the step, and etching the insulating layer to expose the junction part by an etching process using the contact mask. Forming a metal layer on the entire upper surface of the contact hole to fill the contact hole; And applying a third photoresist film to planarize the entire upper surface, and etching the third photoresist film and the metal layer to the entire surface from the step until the surface of the silicon substrate is exposed. Wiring formation method. 제1항에 있어서, 상기 트렌치의 깊이는 6000 내지 8000Å 인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the trench has a depth of 6000 to 8000 Å. 제1항에 있어서, 상기 제3감광막은 상기 금속과의 식각 선택비가 1 내지 1.5:1인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the third photoresist layer has an etching selectivity ratio of 1 to 1.5: 1 with respect to the metal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018540A 1995-06-30 1995-06-30 Metal wiring formation method of semiconductor device KR970003851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950018540A KR970003851A (en) 1995-06-30 1995-06-30 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950018540A KR970003851A (en) 1995-06-30 1995-06-30 Metal wiring formation method of semiconductor device

Publications (1)

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KR970003851A true KR970003851A (en) 1997-01-29

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KR1019950018540A KR970003851A (en) 1995-06-30 1995-06-30 Metal wiring formation method of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132791B2 (en) 2003-04-11 2006-11-07 Kabushiki Kaisha Toyota Jidoshokki Electroluminescence display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132791B2 (en) 2003-04-11 2006-11-07 Kabushiki Kaisha Toyota Jidoshokki Electroluminescence display

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