KR20010058774A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20010058774A
KR20010058774A KR1019990066136A KR19990066136A KR20010058774A KR 20010058774 A KR20010058774 A KR 20010058774A KR 1019990066136 A KR1019990066136 A KR 1019990066136A KR 19990066136 A KR19990066136 A KR 19990066136A KR 20010058774 A KR20010058774 A KR 20010058774A
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South Korea
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semiconductor device
method
trench
polysilicon
etching
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KR1019990066136A
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Korean (ko)
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김충배
정중택
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990066136A priority Critical patent/KR20010058774A/en
Publication of KR20010058774A publication Critical patent/KR20010058774A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce a loss of an active region of a semiconductor substrate by using a polysilicon sidewall to form a trench. CONSTITUTION: An insulating layer(22,23) is formed on an upper portion of the semiconductor substrate(21). The insulating layer(22,23) is etched and patterned and a polysilicon is formed thereon. A polysilicon sidewall is formed at a side of the patterned insulating layer(22,23) by etching the polysilicon. The semiconductor substrate(21) is etched to form a trench by using the insulating layer(22,23) including the polysilicon sidewall as a mask. Defects generated from the trench formation process are corrected by performing a thermal process.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE} Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 기판의 액티브 영역의 손실을 감소시킨 반도체 소자의 제조 방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device which reduces the loss of active area of ​​the present invention relates to a method for manufacturing a semiconductor device, in particular a substrate.

일반적으로 반도체 소자는 격리 산화막(Isolation oxide)을 성장시키거나, 트렌치(Trench)를 이용한 STI(Shallow Trench Isolation) 방법등을 이용하여 소자를 격리시킨다. Generally to a semiconductor device is isolated the element by using a STI (Shallow Trench Isolation) method using the isolation oxide film (Isolation oxide), or to the growth, the trench (Trench).

이와같은 트렌치를 이용한 격리 방법은 실리콘 기판위에 질화막을 증착하고 포토 레지스트 마스크를 사용하여 질화막 및 실리콘 기판을 식각하는 것으로, 트렌치 식각 후 열공정을 이용하여 기판의 결함을 제거하는 과정에서 필연적으로 트렌치 식각면에 손실이 발생하므로 액티브 영역의 손실이 불가피하였다. The isolation method using the same trench depositing a nitride film on a silicon substrate by etching the nitride film and the silicon substrate by using a photoresist mask, inevitably trench etch in the process after the trench etching using a thermal process to remove the defects of the substrate Since the loss in surface loss in the active region was inevitable. 이로 인하여 트랜지스터의 전기적 특성의 악화를 초래하였다. Due to this it resulted in a deterioration of the electrical characteristics of the transistor.

이하 첨부도면을 참조하여 종래기술에 따른 반도체 소자의 제조 방법에 대해 설명하기로 한다. Reference to the accompanying drawings, a description about the method for manufacturing a semiconductor device according to the prior art.

도 1 은 종래기술의 트렌치 식각후 반도체 소자를 나타낸 도면으로서, 반도체 기판(1) 상부에 질화막(2)을 증착한 후, 상기 질화막(2) 상부에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한다. As figure 1 is a view of the semiconductor device after the trench etching of the prior art, depositing a nitride film (2) on a semiconductor substrate (1), coating a photosensitive film on an upper part of the nitride film 2 and then patterned by exposure and development process, . 이어 패터닝된 감광막(3)을 마스크로 이용하여 상기 질화막(2) 및 반도체 기판(1)을 선택적으로 식각하여 트렌치(4)를 형성한다. Followed by using the patterned photoresist 3 as a mask, selectively etching the nitride film 2 and the semiconductor substrate 1 to form a trench (4).

도 2 는 도 1 의 트렌치(4) 식각후 후속 열처리 공정을 진행한 후 액티브 손실이 나타난 반도체 기판(1)을 나타내고 있다. 2 shows the semiconductor substrate 1 is an active loss appears after the subsequent heat treatment process conducted after the trench (4) etched in Fig. 즉 열처리 공정을 이용하여 반도체 기판의 결함을 제거하는 과정에서 트렌치(4) 식각면의 과다한 산화로 인한 손실(A)이 발생되어 트렌치 상측 모서리 부분(B)이 각지게 된다. That is, the loss of (A) due to the excess oxidation of the trench (4) Etching surface generated in the process of removing the defects of the semiconductor substrate using a heat treatment process is the trench upper edge portion (B) angular.

전술한 종래기술의 반도체 소자의 소자 격리 방법은 기판의 결함을 제거하기 위한 열처리 공정시 트렌치 식각면의 과다한 산화로 인해 반도체 기판의 액티브 영역이 손실되어 소자 격리 영역의 상측 모서리 부분이 각지게 되므로, 역방향 좁은 폭 현상(Inverse Narrow Width Effect)이 악화되는 문제점이 있다. Device isolation method for a semiconductor device of the prior art is the active region of a semiconductor substrate loss due to excessive oxidation of the trench etched surface during the heat treatment process for removing defects of the substrate since the upper edge of the element isolation region angular, there is a reverse narrow phenomenon (Inverse narrow width Effect) the problem is exacerbated.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 반도체 기판의 과도한 액티브 영역의 손실을 줄이는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다. The present invention is one devised to solve the above problems, to provide a method of manufacturing a semiconductor device suitable for reducing the loss of the excess active region of the semiconductor substrate it is an object.

도 1 은 종래기술에 따른 트렌치 식각 후 반도체 소자를 나타낸 도면, A view of the semiconductor device 1 is then etched trench in accordance with the prior art,

도 2 는 도 1의 트렌치 식각후 열처리 공정이 진행된 반도체 소자를 나타낸 도면, Figure 2 is a view of the semiconductor element is conducted after the heat treatment step trench etch of Figure 1,

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면. Figures 3a to 3c are views showing a manufacturing method of a semiconductor device according to an embodiment of the invention.

*도면의 주요부분에 대한 부호의 설명* * Description of the Related Art *

21 : 반도체 기판 22 : 패드산화막 21: Semiconductor substrate 22: pad oxide film

23 : 질화막 24 : 폴리실리콘 23: nitride film 24: Polysilicon

25 : 폴리실리콘측벽 26 : 트렌치 25: polysilicon sidewall 26: trench

상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상부에 절연막을 형성하는 단계, 상기 절연막을 선택적으로 식각하여 패터닝하고 상기 결과물의 표면을 따라 폴리실리콘을 형성하는 단계, 상기 폴리실리콘을 전면 식각하여 상기 패터닝된 절연막 측면에 측벽을 형성하는 단계, 상기 측벽을 포함한 절연막을 마스크로 이용하여 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계, 열처리하여 상기 트렌치 형성을 위한 식각시 발생된 결함을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다. A method for manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film on a semiconductor substrate, patterning and selectively etching the insulating film to form a polysilicon along the surface of the resultant product, the poly forming a side wall on the patterned insulating film side by the front etching the silicon, the method comprising: using an insulating film including the sidewall as a mask to form a trench by etching the semiconductor substrate to heat treatment occurs during etching for trench formation It characterized by yirueojim by removing a defect.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다. Hereinafter to be described in detail enough to easily carry out self technical features of the present invention one of ordinary skill in the art, with reference to the accompanying drawings, the preferred embodiment of the present invention will be described .

도 3a 내지 도 3c 는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면이다. Figures 3a to 3c are views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 3a 에 도시된 바와 같이, 반도체 기판(21) 상에 패드 산화막(22)를 증착한 후, 1000Å∼3000Å 두께의 질화막(23) 또는 산화막을 증착하고, 상기 질화막(23) 상에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한다. As shown in Figure 3a, after depositing a pad oxide film 22 on the semiconductor substrate 21, depositing a nitride film 23 or oxide film of 1000Å~3000Å ​​thickness, coating a photosensitive film on the nitride film 23 and it is patterned by exposure and development processes. 이어 패터닝된 감광막을 마스크로 이용하여 질화막(23), 패드 산화막(22)을 식각한다. Followed by using the patterned photoresist as a mask to etch the nitride film 23, the pad oxide film 22. 이 때 상기 질화막(23)은 2 ∼200 mTorr의 압력을 유지한 상태에서 CHF 3 또는 CF 4 에 첨가가스로서 Ar가스를 첨가하여 식각한다. At this time, the nitride film 23 is etched by an Ar gas is added as an additive gas to the CHF 3 or CF 4 in a state of maintaining the ~200 2 mTorr pressure. 이어 상기 질화막(23)의 표면을 따라 300Å 두께의 폴리실리콘(24)을 증착한다. Following deposited polysilicon (24) of 300Å thickness along the surface of the nitride film 23.

도 3b에 도시된 바와 같이, 상기 질화막(23)의 측벽에만 남도록 폴리실리콘 (24)을 식각하여 폴리실리콘측벽(25)을 형성한다. As shown in Figure 3b, to leave only the side wall of the nitride film 23 by etching the polysilicon (24) to form a polysilicon sidewall 25. The

이어 상기 폴리실리콘측벽(25)을 포함한 질화막(23)을 마스크로 이용하여 반도체 기판(21)을 식각하여 필드영역을 정의하기 위한 트렌치(26)를 형성한다. Followed by using the nitride film 23 including the polysilicon sidewall 25 as a mask to etch the semiconductor substrate 21 to form a trench 26 to define the field area.

이 때, 폴리실리콘(24)의 전면식각과 그 하부의 반도체기판(21) 식각은 동일 챔버에서 단일 공정으로 실시할 수 있는바, 이는 폴리실리콘(24)이 식각된 후 질화막(23)이 마스크 역할을 하기 때문이다. At this time, the poly front etched and a lower portion of the semiconductor substrate 21. Etching is a bar that can be performed in a single step in the same chamber, which after the polysilicon 24 is etched nitride film 23 of the silicon 24, the mask because the role.

또한 상기 트렌치(26)는 2∼200 mTorr의 압력을 유지한 상태에서 Cl 2 에 HBr또는 Ar 또는 N 2 가스를 첨가하여 반도체 기판(21)을 식각하여 형성된다. In addition, the trench 26 is formed by the addition of HBr or Ar or N 2 gas to Cl 2 in a state of maintaining the pressure of 2~200 mTorr etching the semiconductor substrate 21.

도 3c에 도시된 바와 같이, 열처리 공정을 실시하여 트렌치(26) 식각시 발생된 반도체 기판(21)의 결함을 제거한다. As it is shown in Figure 3c, by performing an annealing process to remove the defects of the semiconductor substrate 21 caused during the trench 26 etching. 이 때 폴리실리콘측벽(25)의 두께만큼의 액티브 영역이 확보되므로 열처리 공정시 산화로 인한 반도체 기판(21)의 액티브 영역의 과도한 손실을 방지한다. At this time, since the poly-silicon of the active region by the thickness of the side wall 25 is secured to prevent the excessive loss of the active region of the semiconductor substrate 21 due to oxidation during the heat treatment process.

또한 폴리실리콘측벽(25) 하측의 각진 모서리 부분을 완화시키어(C) 역방향 좁은 폭 효과(inverse narrow width effect)를 향상시킨다. In addition, to improve the sikieo ease the angled edges of the lower polysilicon sidewalls (25) (C) reverse narrow effect (inverse narrow width effect).

그리고 상기 열처리 공정시 공정 온도는 700℃∼1200℃를 유지하고, 트렌치 (26) 측벽은 100Å∼500Å두께만큼 산화된다. And the heat treatment process when the process temperature is the trench 26 maintain 700 ℃ ~1200 ℃, and the side walls are oxidized by 100Å~500Å thickness.

이와 같이 본 발명에서는 식각속도가 느린 질화막(23)을 마스크로 하여 반도체기판(21)을 식각할 때 액티브영역은 질화막(23)에서 식각이 늦게 발생하므로 트렌치(26) 구조의 필드영역을 형성할 수 있으며, 폴리실리콘측벽(25)을 이용하므로 액티브영역이 증대되어 후속 열공정에서 산화될 때 과도한 액티브영역의 손실을 방지할 수 있다. In this way the present invention, by the slow etching rate nitride film 23 as a mask, the active region to etch the semiconductor substrate 21 so late etching occurs in the nitride film 23 to form a field region of the trench 26, the structure number and, using the polysilicon side wall 25, so it is possible to prevent the excessive loss of the active region when the active area is increased to be oxidized in a subsequent thermal process.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. Although the teachings of the present invention is specifically described in accordance with the preferred embodiment, the above-described embodiment is for a description thereof should be noted that not for the limitation. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. In addition, if an ordinary specialist in the art of the present invention will be understood by example various embodiments are possible within the scope of the technical idea of ​​the present invention.

상술한 본 발명의 반도체 소자의 제조 방법은 폴리실리콘 측벽을 이용하여트렌치를 형성하므로써, 열처리 공정시 액티브 영역의 손실을 감소시키고 트렌치 상측 모서리 부분을 완화시킬 수 있어 소자의 신뢰성 및 전기적 특성을 향상시킬 수 있다. Method of manufacturing a semiconductor device of the present invention described above will be By forming a trench using the polysilicon sidewalls, reducing the loss of active area during the heat treatment process and it is possible to alleviate the trench upper edge of improving reliability and electrical characteristics of the element can.

Claims (5)

  1. 반도체 소자의 제조 방법에 있어서, In the production method of the semiconductor device,
    반도체 기판 상부에 절연막을 형성하는 단계; Forming an insulating film on a semiconductor substrate;
    상기 절연막을 선택적으로 식각하여 패터닝하고 상기 결과물의 표면을 따라 폴리실리콘을 형성하는 단계; Patterning and selectively etching the insulating film to form a polysilicon along the surface of the resultant product;
    상기 폴리실리콘을 전면 식각하여 상기 패터닝된 절연막 측면에 폴리실리콘측벽을 형성하는 단계; Forming a polysilicon side wall insulating film on the patterned side of the front etching the polysilicon;
    상기 폴리실리콘측벽을 포함한 절연막을 마스크로 이용하여 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계; A step of etching the semiconductor substrate to form a trench using the insulating film including the polysilicon side wall as a mask; And
    열처리하여 상기 트렌치 형성을 위한 식각시 발생된 결함을 제거하는 단계 Heat treatment step of removing a defect generated during the etching for forming the trench
    를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법. The method of producing a semiconductor device, characterized by including yirueojim.
  2. 제 1 항에 있어서, According to claim 1,
    상기 절연막은 질화막 또는 산화막을 이용함을 특징으로 하는 반도체 소자의 제조 방법. The insulating film A method of manufacturing a semiconductor device, characterized by utilizing a nitride film or oxide film.
  3. 제 1 항에 있어서, According to claim 1,
    상기 트렌치 형성시 Cl 2 에 HBr 또는 Ar 또는 N 2 가스를 첨가하여 식각제로 이용하는 것을 특징으로 하는 반도체 소자의 제조 방법. The method of producing a semiconductor device by the addition of HBr or Ar or N 2 gas into the trench formed when Cl 2, characterized in that using an etching agent.
  4. 제 1 항에 있어서, According to claim 1,
    상기 열처리 공정에서 상기 트렌치의 측벽을 100Å∼500Å 두께로 산화시키는 것을 특징으로 하는 반도체 소자의 제조 방법. The method of producing a semiconductor device, comprising a step of oxidizing the sidewalls of the trench with 100Å~500Å thickness in the heat treatment step.
  5. 제 1 항에 있어서, According to claim 1,
    상기 열처리 공정은 700∼1200℃ 에서 실시되는 것을 특징으로 하는 반도체 소자의 제조 방법. The method of producing a semiconductor device characterized in that said heat treatment step is carried out at 700~1200 ℃.
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