KR20010058774A - Method for manufacturing semiconductor device - Google Patents
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- KR20010058774A KR20010058774A KR1019990066136A KR19990066136A KR20010058774A KR 20010058774 A KR20010058774 A KR 20010058774A KR 1019990066136 A KR1019990066136 A KR 1019990066136A KR 19990066136 A KR19990066136 A KR 19990066136A KR 20010058774 A KR20010058774 A KR 20010058774A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 기판의 액티브 영역의 손실을 감소시킨 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having reduced loss of an active region of a substrate.
일반적으로 반도체 소자는 격리 산화막(Isolation oxide)을 성장시키거나, 트렌치(Trench)를 이용한 STI(Shallow Trench Isolation) 방법등을 이용하여 소자를 격리시킨다.In general, a semiconductor device may grow an isolation oxide, or isolate the device by using a trench trench isolation (STI) method using a trench.
이와같은 트렌치를 이용한 격리 방법은 실리콘 기판위에 질화막을 증착하고 포토 레지스트 마스크를 사용하여 질화막 및 실리콘 기판을 식각하는 것으로, 트렌치 식각 후 열공정을 이용하여 기판의 결함을 제거하는 과정에서 필연적으로 트렌치 식각면에 손실이 발생하므로 액티브 영역의 손실이 불가피하였다. 이로 인하여 트랜지스터의 전기적 특성의 악화를 초래하였다.This isolation method using a trench is to deposit a nitride film on a silicon substrate and to etch the nitride film and the silicon substrate using a photoresist mask. Loss of the surface caused a loss of the active region. This resulted in deterioration of the electrical characteristics of the transistor.
이하 첨부도면을 참조하여 종래기술에 따른 반도체 소자의 제조 방법에 대해 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도 1 은 종래기술의 트렌치 식각후 반도체 소자를 나타낸 도면으로서, 반도체 기판(1) 상부에 질화막(2)을 증착한 후, 상기 질화막(2) 상부에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한다. 이어 패터닝된 감광막(3)을 마스크로 이용하여 상기 질화막(2) 및 반도체 기판(1)을 선택적으로 식각하여 트렌치(4)를 형성한다.FIG. 1 is a view illustrating a semiconductor device after trench etching according to the prior art. After the nitride film 2 is deposited on the semiconductor substrate 1, the photoresist film is coated on the nitride film 2 and patterned by an exposure and development process. . Next, the trench 4 is formed by selectively etching the nitride film 2 and the semiconductor substrate 1 using the patterned photosensitive film 3 as a mask.
도 2 는 도 1 의 트렌치(4) 식각후 후속 열처리 공정을 진행한 후 액티브 손실이 나타난 반도체 기판(1)을 나타내고 있다. 즉 열처리 공정을 이용하여 반도체 기판의 결함을 제거하는 과정에서 트렌치(4) 식각면의 과다한 산화로 인한 손실(A)이 발생되어 트렌치 상측 모서리 부분(B)이 각지게 된다.FIG. 2 illustrates a semiconductor substrate 1 in which an active loss is observed after etching the trench 4 of FIG. 1 and then performing a subsequent heat treatment process. That is, in the process of removing defects of the semiconductor substrate using a heat treatment process, a loss A due to excessive oxidation of the etching surface of the trench 4 is generated, and the upper corner portion B of the trench is angled.
전술한 종래기술의 반도체 소자의 소자 격리 방법은 기판의 결함을 제거하기 위한 열처리 공정시 트렌치 식각면의 과다한 산화로 인해 반도체 기판의 액티브 영역이 손실되어 소자 격리 영역의 상측 모서리 부분이 각지게 되므로, 역방향 좁은 폭 현상(Inverse Narrow Width Effect)이 악화되는 문제점이 있다.In the aforementioned device isolation method of the semiconductor device of the prior art, the active region of the semiconductor substrate is lost due to excessive oxidation of the trench etching surface during the heat treatment process for removing the defect of the substrate, so that the upper edge portion of the device isolation region is angled. There is a problem in that the inverse narrow width effect (Inverse Narrow Width Effect) is deteriorated.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 반도체 기판의 과도한 액티브 영역의 손실을 줄이는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for reducing the loss of excessive active regions of a semiconductor substrate.
도 1 은 종래기술에 따른 트렌치 식각 후 반도체 소자를 나타낸 도면,1 is a view showing a semiconductor device after trench etching according to the prior art,
도 2 는 도 1의 트렌치 식각후 열처리 공정이 진행된 반도체 소자를 나타낸 도면,FIG. 2 is a view illustrating a semiconductor device in which a heat treatment process is performed after the trench etching of FIG. 1;
도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면.3A to 3C illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판 22 : 패드산화막21 semiconductor substrate 22 pad oxide film
23 : 질화막 24 : 폴리실리콘23 nitride film 24 polysilicon
25 : 폴리실리콘측벽 26 : 트렌치25 polysilicon side wall 26 trench
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상부에 절연막을 형성하는 단계, 상기 절연막을 선택적으로 식각하여 패터닝하고 상기 결과물의 표면을 따라 폴리실리콘을 형성하는 단계, 상기 폴리실리콘을 전면 식각하여 상기 패터닝된 절연막 측면에 측벽을 형성하는 단계, 상기 측벽을 포함한 절연막을 마스크로 이용하여 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계, 열처리하여 상기 트렌치 형성을 위한 식각시 발생된 결함을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film on the semiconductor substrate, selectively etching and patterning the insulating film and forming polysilicon along the surface of the resultant, the poly Forming a sidewall on the sidewall of the patterned insulating layer by etching the entire surface of the silicon; forming a trench by etching the semiconductor substrate using the insulating layer including the sidewall as a mask; and heat treating the substrate to form a trench. Characterized in that it comprises a step of removing the defect.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3c 는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면이다.3A to 3C illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 3a 에 도시된 바와 같이, 반도체 기판(21) 상에 패드 산화막(22)를 증착한 후, 1000Å∼3000Å 두께의 질화막(23) 또는 산화막을 증착하고, 상기 질화막(23) 상에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한다. 이어 패터닝된 감광막을 마스크로 이용하여 질화막(23), 패드 산화막(22)을 식각한다. 이 때 상기 질화막(23)은 2 ∼200 mTorr의 압력을 유지한 상태에서 CHF3또는 CF4에 첨가가스로서 Ar가스를 첨가하여 식각한다. 이어 상기 질화막(23)의 표면을 따라 300Å 두께의 폴리실리콘(24)을 증착한다.As shown in FIG. 3A, after depositing the pad oxide film 22 on the semiconductor substrate 21, a nitride film 23 or an oxide film having a thickness of 1000 kV to 3000 kV is deposited, and a photoresist film is coated on the nitride film 23. And patterning by exposure and development processes. Subsequently, the nitride film 23 and the pad oxide film 22 are etched using the patterned photoresist as a mask. At this time, the nitride film 23 is etched by adding Ar gas as an additive gas to CHF 3 or CF 4 while maintaining a pressure of 2 to 200 mTorr. Then, polysilicon 24 having a thickness of 300 Å is deposited along the surface of the nitride film 23.
도 3b에 도시된 바와 같이, 상기 질화막(23)의 측벽에만 남도록 폴리실리콘 (24)을 식각하여 폴리실리콘측벽(25)을 형성한다.As shown in FIG. 3B, the polysilicon 24 is etched to remain only on the sidewall of the nitride film 23 to form the polysilicon sidewall 25.
이어 상기 폴리실리콘측벽(25)을 포함한 질화막(23)을 마스크로 이용하여 반도체 기판(21)을 식각하여 필드영역을 정의하기 위한 트렌치(26)를 형성한다.Next, the semiconductor substrate 21 is etched using the nitride film 23 including the polysilicon side wall 25 as a mask to form a trench 26 for defining a field region.
이 때, 폴리실리콘(24)의 전면식각과 그 하부의 반도체기판(21) 식각은 동일 챔버에서 단일 공정으로 실시할 수 있는바, 이는 폴리실리콘(24)이 식각된 후 질화막(23)이 마스크 역할을 하기 때문이다.At this time, the front surface etching of the polysilicon 24 and the lower portion of the semiconductor substrate 21 may be etched in a single process in the same chamber. This is because the nitride film 23 is masked after the polysilicon 24 is etched. Because it plays a role.
또한 상기 트렌치(26)는 2∼200 mTorr의 압력을 유지한 상태에서 Cl2에 HBr또는 Ar 또는 N2가스를 첨가하여 반도체 기판(21)을 식각하여 형성된다.In addition, the trench 26 is formed by etching the semiconductor substrate 21 by adding HBr, Ar, or N 2 gas to Cl 2 while maintaining a pressure of 2 to 200 mTorr.
도 3c에 도시된 바와 같이, 열처리 공정을 실시하여 트렌치(26) 식각시 발생된 반도체 기판(21)의 결함을 제거한다. 이 때 폴리실리콘측벽(25)의 두께만큼의 액티브 영역이 확보되므로 열처리 공정시 산화로 인한 반도체 기판(21)의 액티브 영역의 과도한 손실을 방지한다.As shown in FIG. 3C, a heat treatment process is performed to remove defects in the semiconductor substrate 21 generated during the etching of the trench 26. At this time, since the active area as much as the thickness of the polysilicon side wall 25 is secured, excessive loss of the active area of the semiconductor substrate 21 due to oxidation during the heat treatment process is prevented.
또한 폴리실리콘측벽(25) 하측의 각진 모서리 부분을 완화시키어(C) 역방향 좁은 폭 효과(inverse narrow width effect)를 향상시킨다.In addition, the angled corner portion under the polysilicon side wall 25 is relaxed (C) to improve the inverse narrow width effect.
그리고 상기 열처리 공정시 공정 온도는 700℃∼1200℃를 유지하고, 트렌치 (26) 측벽은 100Å∼500Å두께만큼 산화된다.In the heat treatment step, the process temperature is maintained at 700 ° C. to 1200 ° C., and the sidewalls of the trench 26 are oxidized by a thickness of 100 kPa to 500 kPa.
이와 같이 본 발명에서는 식각속도가 느린 질화막(23)을 마스크로 하여 반도체기판(21)을 식각할 때 액티브영역은 질화막(23)에서 식각이 늦게 발생하므로 트렌치(26) 구조의 필드영역을 형성할 수 있으며, 폴리실리콘측벽(25)을 이용하므로 액티브영역이 증대되어 후속 열공정에서 산화될 때 과도한 액티브영역의 손실을 방지할 수 있다.As described above, in the present invention, when the semiconductor substrate 21 is etched using the nitride film 23 having a slow etching speed as a mask, since the etching occurs in the nitride film 23 later, the field region having the trench 26 structure can be formed. The use of the polysilicon sidewall 25 allows the active area to be increased to prevent loss of excessive active area when oxidized in subsequent thermal processes.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명의 반도체 소자의 제조 방법은 폴리실리콘 측벽을 이용하여트렌치를 형성하므로써, 열처리 공정시 액티브 영역의 손실을 감소시키고 트렌치 상측 모서리 부분을 완화시킬 수 있어 소자의 신뢰성 및 전기적 특성을 향상시킬 수 있다.The method of manufacturing the semiconductor device of the present invention described above forms a trench using polysilicon sidewalls, thereby reducing the loss of the active region during the heat treatment process and alleviating the upper edge portion of the trench, thereby improving the reliability and electrical characteristics of the device. Can be.
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