KR100586538B1 - Method for forming contact hole of semiconductor device - Google Patents

Method for forming contact hole of semiconductor device Download PDF

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KR100586538B1
KR100586538B1 KR1019990065778A KR19990065778A KR100586538B1 KR 100586538 B1 KR100586538 B1 KR 100586538B1 KR 1019990065778 A KR1019990065778 A KR 1019990065778A KR 19990065778 A KR19990065778 A KR 19990065778A KR 100586538 B1 KR100586538 B1 KR 100586538B1
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contact hole
forming
film
selective epitaxial
photoresist pattern
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KR1019990065778A
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Korean (ko)
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KR20010065822A (en
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오훈정
이종민
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H

Abstract

본 발명은 반도체장치의 미세 콘택홀 형성방법에 관한 것으로서, 특히 그 방법은 반도체 기판에 형성된 반도체 소자의 구조물과 상부 배선간의 전기적 절연을 위해 층간 절연막을 형성한 후에 그 위에 반사방지막을 형성하고, 반사방지막 상부에 형성하고자 하는 콘택홀의 폭보다 넓은 폭을 갖는 포토레지스트 패턴을 형성하고, 포토레지스트 패턴에 셀프 얼라인해서 하부의 반사방지막을 선택식각한 후에, 포토레지스트 패턴을 제거하고 패터닝된 반사방지막의 상부 및 측면에 선택적 애피택셜 성장공정을 실시하여 선택적 애피택셜막을 형성한 후에, 선택적 애피택셜막에 의해 노출되는 층간절연막을 식각해서 하부 구조물이 노출되는 콘택홀을 형성한다. 따라서, 본 발명은 포토레지스트의 두께를 증가시키지 않고서도 최초의 콘택 마스크의 크기보다 더 폭이 좁게 층간 절연막내에 콘택홀을 형성할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. In particular, the method includes forming an anti-reflection film thereon and forming an anti-reflection film thereon for electrical insulation between the structure of the semiconductor element formed on the semiconductor substrate and the upper wiring, After forming a photoresist pattern having a width wider than the width of the contact hole to be formed on the protective layer, and self-aligning the photoresist pattern to selectively etch the lower antireflective layer, the photoresist pattern is removed and the upper portion of the patterned antireflective layer is removed. And forming a selective epitaxial layer by performing a selective epitaxial growth process on the side, and etching the interlayer insulating layer exposed by the selective epitaxial layer to form a contact hole through which the lower structure is exposed. Therefore, the present invention can form contact holes in the interlayer insulating film narrower than the size of the original contact mask without increasing the thickness of the photoresist.

Description

반도체장치의 미세 콘택홀 형성방법{Method for forming contact hole of semiconductor device} Method for forming contact hole of semiconductor device             

도 1 내지 도 5는 본 발명에 따른 반도체장치의 미세 콘택홀 형성방법을 설명하기 위한 공정 순서도이다. 1 to 5 are flowcharts illustrating a method for forming a fine contact hole in a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10: 실리콘 기판 12: 필드산화막10 silicon substrate 12 field oxide film

14: 게이트전극 16: 스페이서14: gate electrode 16: spacer

18: 소스/드레인 영역 20: 층간 절연막18: source / drain region 20: interlayer insulating film

22: 반사방지막 24: 포토레지스트 패턴22: antireflection film 24: photoresist pattern

26: 선택적 애피택셜막 28: 콘택홀26: optional epitaxial film 28: contact hole

본 발명은 반도체 장치의 콘택홀 형성방법에 관한 것으로서, 특히 고집적 반 도체 장치의 콘택홀의 에스팩트 비에 대한 이득을 충분히 확보할 수 있고 콘택홀 크기를 감소시킬 수 있는 반도체장치의 미세 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, a method for forming a fine contact hole in a semiconductor device capable of sufficiently securing a gain for an aspect ratio of a contact hole of a highly integrated semiconductor device and reducing a contact hole size. It is about.

최근에는 반도체 소자의 고집적화에 따라 회로 선폭과 간격의 축소가 지속적으로 진행되고 있다. 일반적으로 회로 패턴은 반도체 소자 공정에서 기존의 형성되어 있는 패턴에 새로운 패턴을 형성할 경우 발생할 수 있는 패턴 간의 어긋남을 사전에 고려하여 설계, 제작되고 있다. 이러한 설계 패턴에서의 마진은 소자의 고집적화에 따라 점차 축소되어 가고 있다. 더욱이 소자의 고집적화도에 직접적으로 영향을 미치는 트랜지스터의 형성과 이후 형성되는 다층의 금속 배선을 연결하는 콘택홀의 패턴 마진은 아주 작다. 이 때문에 식각 선택비가 다른 다층의 층간 절연막 내에 미세 콘택홀을 형성하는 제조 공정은 소자의 고집적화에 바람직하지 않다. In recent years, as the integration of semiconductor devices increases, circuit line widths and spacings continue to decrease. In general, a circuit pattern is designed and manufactured in advance in consideration of a deviation between patterns that may occur when a new pattern is formed on an existing pattern in a semiconductor device process. Margins in these design patterns are gradually shrinking with higher integration of devices. Furthermore, the pattern margin of contact holes connecting the formation of transistors that directly affect the high degree of integration of the device and the subsequent multi-layered metal wirings is very small. For this reason, a manufacturing process for forming fine contact holes in a multilayer interlayer insulating film having different etching selectivity is not preferable for high integration of the device.

또한, 에스팩트 비가 큰 콘택홀을 형성하기 위하여 콘택홀 식각시 직진성을 높이거나 다양한 식각 가스 또는 용해제를 개발 중이나 식각이 진행되면서 생기는 포토레지스트의 손실이나 버닝(burning)에 의해 콘택홀의 위쪽 크기가 커지는 문제가 발생하게 되고 이에 따라 콘택홀의 배선 사이에 쇼트가 발생하게 된다. In addition, in order to form a contact hole having a large aspect ratio, the contact hole may be increased in straightness, or a variety of etching gases or solvents may be developed or the photoresist may be increased due to burning or loss of photoresist. A problem occurs and a short occurs between the wirings of the contact hole.

그리고, 포토레지스트의 두께를 높일수록 식각시 손실이나 버닝에 의한 부작용은 막을 수 있으나 콘택홀의 수직 프로파일이 아래로 갈수록 좁아지거나 이를 디파인(define)하기 어려웠다. In addition, as the thickness of the photoresist increases, side effects due to loss or burning during etching can be prevented, but the vertical profile of the contact hole is narrowed downward or it is difficult to define it.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 콘택홀을 형성할 때 포토레지스트 패턴 두께를 높이지 않고 층간 절연막 상부의 반사방지막을 식각하고, 반사방지막 위에 선택 애피택셜 성장(selective epitalxial growth) 공정으로 폴리실리콘막을 형성한 후에 반사방지막을 감싼 폴리실리콘막에 의해 노출된 개구부를 이용하여 층간 절연막에 식각 공정을 진행하여 콘택홀을 형성함으로써 최초의 콘택 마스크의 크기보다 더 폭이 좁은 콘택홀을 형성할 수 있는 반도체장치의 미세 콘택홀 형성방법을 제공하는데 있다.
SUMMARY OF THE INVENTION An object of the present invention is to etch an antireflective film on top of an interlayer insulating film without increasing the thickness of a photoresist pattern when forming a contact hole in order to solve the above problems of the prior art, and to selective epitaxial growth on the antireflective film. After forming the polysilicon film by the process, the contact hole is formed by etching the interlayer insulating film using the opening exposed by the polysilicon film wrapped with the anti-reflection film to form a contact hole, which is narrower than the size of the first contact mask. The present invention provides a method for forming a fine contact hole in a semiconductor device capable of forming a hole.

상기 목적을 달성하기 위하여 본 발명은 반도체장치의 콘택홀 제조 방법에 있어서, 반도체 기판에 형성된 반도체 소자의 구조물과 상부 배선간의 전기적 절연을 위해 층간 절연막을 형성하는 단계와, 층간 절연막 상부에 반사방지막을 형성하는 단계와, 반사방지막 상부에 형성하고자 하는 콘택홀의 폭보다 넓은 폭을 갖는 포토레지스트 패턴을 형성하는 단계와, 포토레지스트 패턴에 셀프 얼라인해서 하부의 반사방지막을 선택식각하는 단계와, 포토레지스트 패턴을 제거하고, 패터닝된 반사방지막의 상부 및 측면에 선택적 애피택셜 성장공정을 실시하여 선택적 애피택셜막을 형성하는 단계와, 선택적 애피택셜막에 의해 노출되는 층간절연막을 식각해서 하부 구조물이 노출되는 콘택홀을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of manufacturing a contact hole in a semiconductor device, the method comprising: forming an interlayer insulating film for electrical insulation between a structure of a semiconductor element formed on a semiconductor substrate and an upper wiring; Forming a photoresist pattern, forming a photoresist pattern having a width wider than that of a contact hole to be formed on the antireflection film, self-aligning the photoresist pattern to selectively etching the lower antireflection film, and Forming a selective epitaxial layer by performing a selective epitaxial growth process on the upper and side surfaces of the patterned antireflective layer, and etching the interlayer insulating layer exposed by the selective epitaxial layer to expose the lower structure. It comprises a step of forming.

본 발명에 따른 콘택홀 형성방법은, 산화막 위에서는 실리콘막이 형성되지 않는 반면에 반사방지막에서는 폴리실리콘의 형태로 실리콘막이 성장되는 선택적 애피택셜 성장 공정을 이용한다. 즉, 층간 절연막 상부에 반사방지막을 형성한 후에 콘택 마스크를 이용한 포토레지스트 패턴을 형성하고 첫 번째 식각 공정으로 상기 반사방지막 아래 층간 절연막의 산화물질이 드러나도록 반사방지막을 패터닝한다. 그리고, 선택적 애피택셜 성장 공정을 진행하여 반사방지막 상부 및 측면에 선택적 애피택셜막을 성장시키고 상기 애피택셜막을 하드 마스크로 삼아서 포토레지스트:산화막(층간절연막)보다 식각 선택비가 좋은 실리콘:산화막 식각 공정을 실시하여 콘택홀을 형성한다. 이에 따라, 본 발명은 콘택홀의 에스팩트 비에 대한 이득을 충분히 확보할 수 있고 콘택홀 크기를 감소시킬 수 있다.The method for forming a contact hole according to the present invention uses a selective epitaxial growth process in which a silicon film is not formed on the oxide film, but the silicon film is grown in the form of polysilicon in the antireflection film. That is, after the anti-reflection film is formed on the interlayer insulating film, a photoresist pattern using a contact mask is formed, and the anti-reflection film is patterned so that the oxide quality of the interlayer insulating film under the anti-reflection film is exposed by the first etching process. In addition, a selective epitaxial growth process is performed to grow a selective epitaxial layer on the top and side surfaces of the anti-reflection film, and the silicon epitaxial etching process is performed with a better etching selectivity than the photoresist: oxide film (interlayer insulating film) using the epitaxial film as a hard mask. To form contact holes. Accordingly, the present invention can sufficiently secure the gain for the aspect ratio of the contact hole and reduce the contact hole size.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 5는 본 발명에 따른 반도체장치의 미세 콘택홀 형성방법을 설명하기 위한 공정 순서도이다. 1 to 5 are flowcharts illustrating a method for forming a fine contact hole in a semiconductor device according to the present invention.

이를 참조하면 본 발명의 콘택홀 제조 공정은 다음과 같다.Referring to this, the contact hole manufacturing process of the present invention is as follows.

우선, 도 1에 도시된 바와 같이 반도체기판으로서 실리콘 기판(10)에 통상의 제조 공정을 거쳐 필드산화막(12)을 형성하고, 그 기판의 활성 영역에 게이트전극(14) 및 스페이서(16)을 형성한 후에 게이트 전극과 필드산화막(12) 사이에 드러난 기판내에 소스/드레인 영역(18)을 구비한 트랜지스터를 형성한다. First, as shown in FIG. 1, a field oxide film 12 is formed on a silicon substrate 10 through a conventional manufacturing process as a semiconductor substrate, and the gate electrode 14 and the spacer 16 are formed in the active region of the substrate. After formation, a transistor having a source / drain region 18 is formed in the substrate exposed between the gate electrode and the field oxide film 12.

그 다음, 상기 트랜지스터가 형성된 기판 전면에 BPSG(Boro Phosphorus Silicate Glass) 혹은 PSG(Phosphorus Silicate Glass) 계열의 절연막을 1000∼3000Å의 두께로 증착하여 층간 절연막(20)을 형성한다. 그리고, 상기 층간 절연막(20) 상부에 Si, Si3N4, SiO2의 혼합 화합물의 형태인 SiON(Silicon OxyNitride)를 증착하여 반사방지막(22)을 형성한다. Next, an interlayer insulating film 20 is formed by depositing a BPSG (Boro Phosphorus Silicate Glass) or PSG (Phosphorus Silicate Glass) -based insulating film on the entire surface of the substrate on which the transistor is formed. In addition, an anti-reflection film 22 is formed by depositing silicon oxide nitride (SiON) in the form of a mixed compound of Si, Si 3 N 4 , and SiO 2 on the interlayer insulating film 20.

이어서, 도 2에 도시된 바와 같이, 사진 공정을 진행하여 하부의 트랜지스터 소스/드레인 영역을 개방하기 위하여 형성하고자 하는 콘택홀의 폭보다 넓은 창(a)을 갖는 포토레지스트 패턴(24)을 형성한다. Subsequently, as shown in FIG. 2, the photolithography process is performed to form a photoresist pattern 24 having a window a wider than the width of the contact hole to be formed to open the lower transistor source / drain region.

그 다음, 도 3에 도시된 바와 같이, 포토레지스트 패턴(24)에 셀프 얼라인해서 하부의 반사방지막(22)을 선택식각한다. 이때, 반사방지막(22)의 식각 공정은 건식 내지 습식식각 공정을 이용하되, 도면 부호 25에서와 같이 하부 층간 절연막(20)이 과도 식각되도록 한다. 그리고, 포토레지스트 패턴(24)을 제거한 후에 기판 표면의 불순물을 제거하기 위해 세정공정을 실시한다.Next, as shown in FIG. 3, self-alignment is performed on the photoresist pattern 24 to selectively etch the lower anti-reflection film 22. At this time, the etching process of the anti-reflection film 22 uses a dry to wet etching process, as shown in reference numeral 25 so that the lower interlayer insulating film 20 is excessively etched. After the photoresist pattern 24 is removed, a cleaning process is performed to remove impurities from the surface of the substrate.

이어서, 도 4에 도시된 바와 같이, 패터닝된 반사방지막(22')에 선택적 애피택셜 성장공정을 실시하여 반사방지막 패턴 사이에 상기 a에 비해 작은 폭(b)을 갖는 폴리실리콘막인 선택적 애피택셜막(26)을 형성한다. 여기서, 상기 선택적 애피택셜 성장 공정에 의해 반사방지막 패턴(22')의 측면에도 선택적 애피택셜막(26)이 성장되어 결국, 층간 절연막내에 형성될 콘택홀의 폭은 약 a-2b의 크기를 갖는다.Next, as shown in FIG. 4, a selective epitaxial growth process is performed on the patterned anti-reflective film 22 ′ to form a selective epitaxial film, which is a polysilicon film having a width (b) smaller than a between the anti-reflective film patterns. The sher film 26 is formed. In this case, the selective epitaxial layer 26 is also grown on the side surface of the anti-reflective layer pattern 22 'by the selective epitaxial growth process, and thus, the contact hole to be formed in the interlayer insulating layer has a size of about a-2b.

여기서, 선택적 애피택셜 성장 공정은 실리콘단결정이 산화막 위에 성장되지 않는 특성을 활용한 에피층 성장 방법으로서, 주로 화학기상증착법에 의한 성장 공정은 공정 조건과 형성 온도에 따라 초고진공(ultra high-vacuum) 화학기상증착 방법 내지 저온/고속열처리 화학기상증착을 이용하여 진행한다.In this case, the selective epitaxial growth process is an epitaxial growth method utilizing the characteristic that silicon single crystals are not grown on the oxide film, and the growth process mainly by chemical vapor deposition is ultra high-vacuum depending on process conditions and formation temperature. The process is carried out using a chemical vapor deposition method or a low temperature / high speed heat treatment chemical vapor deposition.

본 실시예에서는 고진공 화학기상증착 챔버에서 실리콘 소스가스(SiH2Cl2, SiH4,Si2H6)과 수소 또는 HCl 가스를 이용하여 폴리실리콘을 성장한다. In the present embodiment, polysilicon is grown using silicon source gas (SiH 2 Cl 2 , SiH 4 , Si 2 H 6 ) and hydrogen or HCl gas in a high vacuum chemical vapor deposition chamber.

그 다음, 도 5에 도시된 바와 같이, 산화막에 대해 선택비가 우수한, 반사방지막(22')을 감싼 선택적 애피택셜막(26)을 식각 하드마스크로 삼아 층간절연막(20)을 선택 식각해서 하부 구조물인 소스/드레인(18)이 노출되는 콘택홀(28)을 형성한다. 여기서, 식각 공정은 층간절연막(20)인 산화물층의 실리콘 식각비에 대해 10:1 이상의 선택비를 갖는 건식 내지 습식 식각 공정을 진행한다. Next, as shown in FIG. 5, the interlayer insulating film 20 is selectively etched using the selective epitaxial film 26 wrapped around the anti-reflection film 22 ′, which has an excellent selectivity with respect to the oxide film, as an etch hard mask. A contact hole 28 is formed through which the phosphorus source / drain 18 is exposed. Here, the etching process is a dry to wet etching process having a selectivity of 10: 1 or more relative to the silicon etching ratio of the oxide layer, which is the interlayer insulating film 20.

이로 인해, 본 발명은 선택적 애피택셜막(26)이 반사방지막 패턴(22')의 측면에도 성장하므로 이 애피택셜막의 성장 두께를 조절하여 콘택홀 크기를 원하는 크기로 축소시킬 수 있다. 바람직하게는, 애피택셜막의 성장 두께를 콘택홀 마스크 공정에 의해 얻어진 포토레지스트 패턴의 폭의 0.5 이하가 되도록 한다. For this reason, according to the present invention, since the selective epitaxial film 26 also grows on the side surface of the antireflection film pattern 22 ', the contact hole size can be reduced to a desired size by controlling the growth thickness of the epitaxial film. Preferably, the growth thickness of the epitaxial film is set to 0.5 or less of the width of the photoresist pattern obtained by the contact hole mask process.

상기와 같은 제조 공정에 의하면, 본 발명은 포토레지스트의 두께를 증가시키지 않고서도 최초의 콘택 마스크의 크기보다 더 폭이 좁게 층간 절연막내에 콘택홀을 형성할 수 있어 에스팩트비가 높은 콘택홀 제조 공정의 수율을 높일 수 있는 효과가 있다. According to the manufacturing process as described above, the present invention can form a contact hole in the interlayer insulating film narrower than the size of the original contact mask without increasing the thickness of the photoresist, so that the contact hole manufacturing process with high aspect ratio It is effective to increase the yield.

Claims (4)

반도체장치의 콘택홀 제조 방법에 있어서,In the contact hole manufacturing method of a semiconductor device, 반도체 기판에 형성된 반도체 소자의 구조물과 상부 배선간의 전기적 절연을 위해 층간 절연막을 형성하는 단계;Forming an interlayer insulating film for electrical insulation between the structure of the semiconductor element formed on the semiconductor substrate and the upper wiring; 상기 층간 절연막 상부에 반사방지막을 형성하는 단계;Forming an anti-reflection film on the interlayer insulating film; 상기 반사방지막 상부에 형성하고자 하는 콘택홀의 폭보다 넓은 폭을 갖는 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern having a width wider than that of a contact hole to be formed on the anti-reflection film; 상기 포토레지스트 패턴에 셀프 얼라인해서 하부의 반사방지막을 선택식각하는 단계;Self-aligning the photoresist pattern to selectively etch a lower anti-reflection film; 상기 포토레지스트 패턴을 제거하고, 상기 패터닝된 반사방지막의 상부 및 측면에 선택적 애피택셜 성장공정을 실시하여 선택적 애피택셜막을 형성하는 단계; 및Removing the photoresist pattern and performing a selective epitaxial growth process on the top and side surfaces of the patterned anti-reflective film to form a selective epitaxial film; And 상기 선택적 애피택셜막에 의해 노출되는 층간절연막을 식각해서 하부 구조물이 노출되는 콘택홀을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 장치의 미세 콘택홀 형성방법.And forming a contact hole through which the underlying structure is exposed by etching the interlayer insulating layer exposed by the selective epitaxial layer. 제1항에 있어서, 상기 반사방지막은 SiON인 것을 특징으로 하는 반도체장치의 미세 콘택홀 형성방법.The method of claim 1, wherein the anti-reflection film is SiON. 제1항에 있어서, 상기 반사방지막의 식각 공정은 건식 내지 습식식각 공정을 이용하되 과도 식각 공정을 실시하는 것을 특징으로 하는 반도체장치의 미세 콘택홀 형성방법.The method of claim 1, wherein the etching process of the anti-reflection film is performed using a dry to wet etching process but performing an excessive etching process. 제1항에 있어서, 상기 선택적 애피택셜막의 두께는 콘택홀 마스크 공정에 의해 얻어진 포토레지스트 패턴의 폭의 0.5 이하가 되도록 하는 것을 특징으로 하는 반도체장치의 미세 콘택홀 형성방법.The method of claim 1, wherein the selective epitaxial film has a thickness of 0.5 or less of the width of the photoresist pattern obtained by the contact hole mask process.
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