KR100953025B1 - Method for forming contact hole in a semiconductor device - Google Patents

Method for forming contact hole in a semiconductor device Download PDF

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KR100953025B1
KR100953025B1 KR1020030029260A KR20030029260A KR100953025B1 KR 100953025 B1 KR100953025 B1 KR 100953025B1 KR 1020030029260 A KR1020030029260 A KR 1020030029260A KR 20030029260 A KR20030029260 A KR 20030029260A KR 100953025 B1 KR100953025 B1 KR 100953025B1
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contact hole
forming
trench
interlayer insulating
film
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KR1020030029260A
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KR20040096324A (en
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정우영
김정현
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 낸드(NAND)형 플래쉬 메모리 셀 어레이의 비트라인 형성을 위한 드레인(Drain) 콘택홀 형성 방법에 관한 것으로, 층간절연막을 형성한 후 게이트 전극 양측벽의 산화막 스페이서와 일치되는 부분에 트렌치를 형성하고, 트렌치 내에 유기물의 반사방지막을 매립하여 패턴을 형성한다. 콘택홀 형성 과정에서 반사방지막 패턴이 식각 방지층으로 작용하여 산화막 스페이서의 손실이 방지되고, 마스크에 형성된 콘택홀 패턴보다 작은 크기의 콘택홀이 형성된다. 따라서 게이트 전극 간의 거리를 증가시키지 않아도 게이트 전극과의 중첩 마진을 충분히 확보할 수 있으며 웨이퍼 당 다이 수가 감소되지 않아 수율 저하가 방지된다. The present invention relates to a method of forming a drain contact hole for forming a bit line of a NAND type flash memory cell array. After forming an interlayer insulating film, a trench is formed in a portion of the gate electrode corresponding to the oxide spacers on both sidewalls of the gate electrode. And a pattern is formed by embedding the antireflection film of the organic material in the trench. In the process of forming the contact hole, the anti-reflection film pattern serves as an etch stop layer to prevent loss of the oxide spacer, and a contact hole having a smaller size than the contact hole pattern formed in the mask is formed. Accordingly, even if the distance between the gate electrodes is not increased, the overlap margin with the gate electrodes can be sufficiently secured, and the number of dies per wafer is not reduced, thereby preventing a decrease in yield.

콘택홀, 콘택홀 패턴, 트렌치, 유기물, 식각방지층Contact hole, contact hole pattern, trench, organic material, etching prevention layer

Description

반도체 소자의 콘택홀 형성 방법 {Method for forming contact hole in a semiconductor device}Method for forming contact hole in semiconductor device

도 1a 및 도 1b는 종래 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method for forming a contact hole in a conventional semiconductor device.

도 2는 도 1a의 공정에 사용되는 콘택홀 형성용 마스크의 평면도.FIG. 2 is a plan view of a contact hole forming mask used in the process of FIG. 1A. FIG.

도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 단면도.3A to 3E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.

도 4는 도 3a의 공정에 사용되는 트렌치 형성용 마스크의 평면도.4 is a plan view of a trench forming mask used in the process of FIG. 3A.

도 5는 도 3c의 공정에 사용되는 콘택홀 형성용 마스크의 평면도.5 is a plan view of a contact hole forming mask used in the process of FIG. 3C.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1, 31: 반도체 기판 2a, 2b, 32a, 32b: 게이트 전극1, 31: semiconductor substrate 2a, 2b, 32a, 32b: gate electrode

3, 33: 접합영역 4, 34: 산화막 스페이서3, 33: junction region 4, 34: oxide film spacer

5, 35: 캡핑층 6, 36: 층간절연막5, 35: capping layer 6, 36: interlayer insulating film

7, 37, 42: 반사방지막 8, 38, 43: 감광막7, 37, 42: antireflection film 8, 38, 43: photosensitive film

9, 46: 콘택홀 10, 40, 44: 마스크9, 46: contact holes 10, 40, 44: mask

11, 45: 콘택홀 패턴 39: 트렌치11, 45: contact hole pattern 39: trench

41: 트렌치 패턴 47: 플러그41: trench pattern 47: plug

본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 더욱 상세하게는 낸드(NAND)형 플래쉬 메모리 셀 어레이의 비트라인 형성을 위한 드레인(Drain) 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact hole of a semiconductor device, and more particularly, to a method of forming a drain contact hole for forming a bit line of a NAND type flash memory cell array.

일반적으로 낸드(NAND)형 플래쉬 메모리 셀 어레이는 다수의 메모리 셀이 일렬로 접속된 스트링(String) 형태로 이루어진다. 스트링 형태로 연결된 다수의 메모리 셀에는 워드라인이 각각 접속되며, 각 스트링의 메모리 셀은 셀렉트 트랜지스터를 통해 비트라인에 접속된다. 이 때 비트라인은 절연막에 형성된 콘택홀을 통해 메모리 셀의 드레인에 연결되는데, 비트라인과의 연결을 위한 종래의 드레인 콘택홀 형성 방법을 도 1a 및 도 1b를 통해 설명하면 다음과 같다. In general, a NAND flash memory cell array has a string form in which a plurality of memory cells are connected in a line. A plurality of memory cells connected in a string form are connected to word lines, and memory cells of each string are connected to bit lines through select transistors. At this time, the bit line is connected to the drain of the memory cell through the contact hole formed in the insulating film. A conventional method of forming a drain contact hole for connection with the bit line will be described below with reference to FIGS. 1A and 1B.

도 1a를 참조하면, 반도체 기판(1) 상에 게이트 산화막, 플로팅 게이트, 유전체막 및 콘트롤 게이트가 적층된 구조를 갖는 메모리 셀의 게이트 전극(2a)과 트랜지스터의 게이트 전극(2b)을 각각 형성한 후 게이트 전극(2a 및 2b) 양측의 반도체 기판(1)에 접합영역(3)을 형성한다. 게이트 전극(2a 및 2b) 양측벽에 산화막 스페이서(4)를 형성한 후 전체 상부면에 캡핑층(5)과 층간절연막(6)을 순차적으로 형성하고 평탄화시킨다. 층간절연막(6) 상에 반사방지막(7) 및 감광막(8)을 순차적으로 형성한 후 도 2에 도시된 콘택홀 형성용 마스크를 이용하여 감광막(8)을 패터닝한다. Referring to FIG. 1A, a gate electrode 2a of a memory cell and a gate electrode 2b of a transistor having a structure in which a gate oxide film, a floating gate, a dielectric film, and a control gate are stacked on a semiconductor substrate 1 are formed, respectively. The junction region 3 is then formed in the semiconductor substrate 1 on both sides of the gate electrodes 2a and 2b. After the oxide spacers 4 are formed on both sidewalls of the gate electrodes 2a and 2b, the capping layer 5 and the interlayer insulating film 6 are sequentially formed and planarized on the entire upper surface. After the antireflection film 7 and the photoresist film 8 are sequentially formed on the interlayer insulating film 6, the photoresist film 8 is patterned by using the contact hole forming mask shown in FIG. 2.                         

도 2에 도시된 바와 같이 콘택홀 형성용 마스크(10)에는 타원형의 콘택홀 패턴(11)이 일렬로 형성된다. 248㎚ 파장의 KrF 노광 장비에서는 120㎚의 지름을 갖는 원형의 콘택홀 패턴을 형성하기 어렵기 때문에 도 2에 도시된 바와 같이 콘택홀 패턴(11)을 120㎚×180㎚ 크기의 타원형으로 형성한다. 따라서 0.090㎛의 디자인 룰을 적용하는 낸드(NAND)형 플래쉬 메모리 소자의 제조 공정에서는 도 2와 같은 콘택홀 형성용 마스크를 사용한다. As shown in FIG. 2, an elliptical contact hole pattern 11 is formed in a line in the contact hole forming mask 10. In the KrF exposure equipment having a wavelength of 248 nm, since it is difficult to form a circular contact hole pattern having a diameter of 120 nm, as shown in FIG. 2, the contact hole pattern 11 is formed into an ellipse having a size of 120 nm × 180 nm. . Therefore, a contact hole forming mask as shown in FIG. 2 is used in a manufacturing process of a NAND type flash memory device to which a design rule of 0.090 μm is applied.

도 1b를 참조하면, 패터닝된 감광막(8)을 마스크로 이용한 식각 공정으로 노출된 부분의 반사방지막(7), 층간절연막(6) 및 캡핑층(5)을 순차적으로 식각하여 게이트 전극(2a 및 2b) 사이의 접합영역(3)이 노출되도록 콘택홀(9)을 형성한다.Referring to FIG. 1B, the anti-reflection film 7, the interlayer insulating film 6, and the capping layer 5 of the exposed portions are sequentially etched by the etching process using the patterned photoresist 8 as a mask to form the gate electrodes 2a and The contact hole 9 is formed so that the junction region 3 between 2b) is exposed.

이 후 감광막(8)과 반사방지막(7)을 제거하고 상기 콘택홀(9) 내에 폴리실리콘을 매립하여 플러그(도시않됨)를 형성한 다음 상기 플러그를 통해 접합영역(3)과 접속되도록 비트라인을 형성한다.Thereafter, the photoresist film 8 and the anti-reflection film 7 are removed, and a polysilicon is embedded in the contact hole 9 to form a plug (not shown), and then the bit line is connected to the junction region 3 through the plug. To form.

노광 장비가 갖는 파장의 한계로 인하여 종래의 공정에서는 도 2에 도시된 바와 같이 120㎚×180㎚ 크기의 타원형으로 이루어진 콘택홀 패턴(11)을 갖는 마스크(10)를 사용하여 콘택홀(9)을 형성한다. 따라서 콘택홀(9)이 타원 형태로 형성되기 때문에 식각 과정에서 콘택홀(9)의 가장자리부와 인접하는 부분의 산화막 스페이서(4)가 손상된다. 또한, 콘택홀(9)을 타원 형태로 형성함에 따라 게이트 전극(2a 및 2b)과의 중첩 마진(overlap margin)을 확보하기 위해 게이트 전극(2a 및 2b) 간의 거리를 증가시켜야 하기 때문에 웨이퍼(wafer) 당 다이(die)의 수가 감소되고, 이에 따라 소자의 수율이 감소된다.Due to the limitation of the wavelength of the exposure equipment, in the conventional process, as shown in FIG. 2, the contact hole 9 is formed by using the mask 10 having the contact hole pattern 11 formed of an elliptical shape having a size of 120 nm × 180 nm. To form. Therefore, since the contact hole 9 is formed in an ellipse shape, the oxide spacer 4 in the portion adjacent to the edge of the contact hole 9 is damaged during the etching process. In addition, since the contact hole 9 is formed in an ellipse shape, the distance between the gate electrodes 2a and 2b must be increased in order to secure an overlap margin with the gate electrodes 2a and 2b. The number of dies per die is reduced, thereby reducing the yield of the device.

따라서 본 발명은 층간절연막을 형성한 후 게이트 전극 양측벽의 산화막 스페이서와 일치되는 부분에 트렌치를 형성하고, 트렌치 내에 유기물을 매립하여 패턴을 형성함으로써 상기한 단점을 해소할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는 데 그 목적이 있다.Therefore, in the present invention, a trench is formed in a portion of the gate electrode on both sidewalls of the gate electrode, and a pattern is formed by filling an organic material in the trench. The purpose is to provide a formation method.

상기한 목적을 달성하기 위한 본 발명은 반도체 기판 상에 게이트 전극을 형성한 후 상기 게이트 전극 양측부의 반도체 기판에 접합영역을 형성하는 단계와, 상기 게이트 전극 양측벽에 스페이서를 형성한 후 전체 상부면에 캡핑층 및 층간절연막을 순차적으로 형성하는 단계와, 상기 스페이서와 일치되는 부분의 상기 층간절연막에 소정 깊이의 트렌치를 형성하고 상기 트렌치 내에 유기물을 매립하는 단계와, 상기 층간절연막 상에 감광막 패턴을 형성한 후 상기 감광막 패턴과 상기 유기물을 마스크로 이용한 식각 공정으로 노출된 부분의 층간절연막과 캡핑층을 제거하여 상기 접합영역이 노출되도록 콘택홀을 형성하는 단계와, 상기 감광막 패턴을 제거하고, 상기 콘택홀을 매립하는 플러그를 형성하는 단계와, 상기 유기물이 제거되는 시점까지 상기 플러그 및 상기 층간 절연막을 평탄화 공정으로 제거하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, a gate electrode is formed on a semiconductor substrate, and then a junction region is formed on a semiconductor substrate at both sides of the gate electrode, and a spacer is formed on both sidewalls of the gate electrode. Sequentially forming a capping layer and an interlayer insulating film, forming a trench having a predetermined depth in the interlayer insulating film in a portion coinciding with the spacer, and embedding an organic material in the trench, and forming a photoresist pattern on the interlayer insulating film. Forming a contact hole to expose the junction region by removing the interlayer insulating layer and the capping layer of the portion exposed by the etching process using the photoresist pattern and the organic material as a mask, and removing the photoresist pattern; Forming a plug to bury the contact hole, and up to a point where the organic material is removed And removing the pre-plug and the interlayer insulating film by a planarization process.

상기 트렌치의 깊이는 상기 감광막 패턴의 두께보다 두꺼우며, 상기 반도체 기판에서 상기 트렌치까지의 높이는 상기 반도체 기판에서 상기 캡핑층까지의 높이와 상기 제거된 층간절연막의 두께보다 큰 것을 특징으로 한다.The depth of the trench is thicker than the thickness of the photoresist pattern, and the height from the semiconductor substrate to the trench is greater than the height from the semiconductor substrate to the capping layer and the thickness of the removed interlayer insulating film.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하 기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 단면도이다.3A to 3E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.

도 3a를 참조하면, 반도체 기판(31) 상에 게이트 산화막, 플로팅 게이트, 유전체막 및 콘트롤 게이트가 적층된 구조를 갖는 메모리 셀의 게이트 전극(32a)과 트랜지스터의 게이트 전극(32b)을 각각 형성한 후 게이트 전극(32a 및 32b) 양측의 반도체 기판(31)에 접합영역(33)을 형성한다. 게이트 전극(32a 및 32b) 양측벽에 산화막 스페이서(34)를 형성한 후 전체 상부면에 캡핑층(35)과 층간절연막(36)을 순차적으로 형성하고 평탄화시킨다. 층간절연막(36) 상에 반사방지막(37) 및 감광막(38)을 순차적으로 형성한 후 도 4에 도시된 트렌치 형성용 마스크를 이용하여 감광막(38)을 패터닝한다. 도 4에 도시된 바와 같이 트렌치 형성용 마스크(40)에는 게이트 전극(32a 및 32b) 양측벽의 산화막 스페이서(34)와 일치되도록 트렌치 패턴(41)이 형성된다. 상기 캡핑층(35)은 질화막 등으로 형성하며, 상기 층간절연막(36)은 산화막 등으로 형성한다.Referring to FIG. 3A, a gate electrode 32a of a memory cell and a gate electrode 32b of a transistor having a structure in which a gate oxide film, a floating gate, a dielectric film, and a control gate are stacked on a semiconductor substrate 31 are formed, respectively. Afterwards, a junction region 33 is formed in the semiconductor substrate 31 on both sides of the gate electrodes 32a and 32b. After the oxide spacer 34 is formed on both sidewalls of the gate electrodes 32a and 32b, the capping layer 35 and the interlayer insulating layer 36 are sequentially formed and planarized on the entire upper surface thereof. After the anti-reflection film 37 and the photosensitive film 38 are sequentially formed on the interlayer insulating film 36, the photosensitive film 38 is patterned by using the trench forming mask shown in FIG. 4. As shown in FIG. 4, a trench pattern 41 is formed in the trench forming mask 40 to coincide with the oxide spacers 34 on both sidewalls of the gate electrodes 32a and 32b. The capping layer 35 is formed of a nitride film or the like, and the interlayer insulating film 36 is formed of an oxide film or the like.

도 3b를 참조하면, 패터닝된 감광막(38)을 마스크로 이용한 식각 공정으로 노출된 부분의 반사방지막(37) 및 층간절연막(36)을 식각하여 층간절연막(36)에 소정 깊이의 트렌치(39)를 형성한 후 잔류된 감광막(38) 및 반사방지막(37)을 제거한다.Referring to FIG. 3B, a trench 39 having a predetermined depth in the interlayer insulating layer 36 is etched by etching the anti-reflective layer 37 and the interlayer insulating layer 36 in the exposed portion by an etching process using the patterned photosensitive film 38 as a mask. After forming, the remaining photosensitive film 38 and the anti-reflection film 37 are removed.

도 3c를 참조하면, 상기 트렌치(39)가 완전히 매립되도록 전체 상부면에 반사방지막(42)을 형성한 후 반사방지막(42) 상에 감광막(43)을 형성하고 도 5에 도 시된 콘택홀 형성용 마스크를 이용하여 감광막(43)을 패터닝한다. 도 5에 도시된 바와 같이 콘택홀 형성용 마스크(44)에는 타원형의 콘택홀 패턴(45)이 일렬로 형성된다. 상기 반사방지막(42)은 유기물로 형성하며, 트렌치(39) 폭의 1/2보다 두껍게 형성하여 트렌치(39)가 완전히 매립되도록 한다.Referring to FIG. 3C, an anti-reflection film 42 is formed on the entire upper surface of the trench 39 so as to completely fill the trench 39, and then a photoresist film 43 is formed on the anti-reflection film 42, and the contact hole illustrated in FIG. 5 is formed. The photosensitive film 43 is patterned using the mask for a mask. As shown in FIG. 5, an elliptical contact hole pattern 45 is formed in a line in the contact hole forming mask 44. The anti-reflection film 42 is formed of an organic material, and is formed to be thicker than 1/2 of the width of the trench 39 to completely fill the trench 39.

도 3d를 참조하면, 패터닝된 감광막(43)을 마스크로 이용한 식각 공정으로 노출된 부분의 반사방지막(42), 층간절연막(36) 및 캡핑층(35)을 순차적으로 식각하여 게이트 전극(32a 및 32b) 사이의 접합영역(33)이 노출되도록 콘택홀(46)을 형성한 후 잔류된 감광막(43)과 반사방지막(42)을 제거한다. 이 때 트렌치(39) 내에 매립된 반사방지막(42)이 산화막 스페이서(34)의 상부에 위치되기 때문에 산화막 스페이서(34)의 손상이 방지되며, 반사방지막(42)이 식각방지층으로 작용하기 때문에 마스크(44)에 형성된 콘택홀 패턴(45)보다 크기가 작은 콘택홀(46)이 형성된다.Referring to FIG. 3D, the anti-reflective film 42, the interlayer insulating film 36, and the capping layer 35 of the exposed portion are sequentially etched by the etching process using the patterned photoresist 43 as a mask to form the gate electrodes 32a and After forming the contact hole 46 to expose the junction region 33 between 32b), the remaining photosensitive film 43 and the anti-reflection film 42 are removed. At this time, since the anti-reflection film 42 embedded in the trench 39 is located above the oxide spacer 34, damage to the oxide spacer 34 is prevented, and since the anti-reflection film 42 acts as an etch stop layer, the mask A contact hole 46 having a smaller size than the contact hole pattern 45 formed in the 44 is formed.

도 3e를 참조하면, 콘택홀(46)이 매립되도록 전체 상부면에 폴리실리콘을 증착한 후 잔류된 반사방지막(42)이 제거되는 시점까지 화학적기계적연마(CMP) 공정으로 폴리실리콘 및 층간절연막(36)을 평탄화하여 콘택홀(46) 내에 접합영역(33)과 연결된 플러그(47)가 형성되도록 한다.Referring to FIG. 3E, polysilicon is deposited on the entire upper surface of the contact hole 46 to be filled, and then the polysilicon and the interlayer dielectric layer are formed by a chemical mechanical polishing (CMP) process until the remaining anti-reflection film 42 is removed. 36 is planarized to form a plug 47 connected to the junction region 33 in the contact hole 46.

상기 트렌치(39)의 깊이는 콘택홀(46) 형성시 식각 마스크로 이용되는 감광막 패턴(43)의 두께보다 두꺼워야 하며, 반도체 기판(31)에서 트렌치(39)까지의 높이는 반도체 기판(31)에서 캡핑층(35)까지의 높이와 화학적기계적연마(CMP) 공정시 연마되는 층간절연막(36)의 두께보다 커야 한다. The depth of the trench 39 should be thicker than the thickness of the photoresist pattern 43 used as an etch mask when the contact hole 46 is formed, and the height from the semiconductor substrate 31 to the trench 39 is increased. It should be greater than the height to the capping layer 35 and the thickness of the interlayer insulating film 36 to be polished during the chemical mechanical polishing (CMP) process.

상술한 바와 같이 본 발명은 층간절연막을 형성한 후 게이트 전극 양측벽의 산화막 스페이서와 일치되는 부분에 트렌치를 형성하고, 트렌치 내에 유기물의 반사방지막을 매립하여 패턴을 형성한다. 콘택홀 형성 과정에서 반사방지막 패턴이 식각 방지층으로 작용하여 산화막 스페이서의 손실이 방지되고, 마스크에 형성된 콘택홀 패턴보다 작은 크기의 콘택홀이 형성된다. 따라서 본 발명을 이용하면 게이트 전극 간의 거리를 증가시키지 않아도 게이트 전극과의 중첩 마진을 충분히 확보할 수 있으며 웨이퍼 당 다이 수가 감소되지 않아 수율 저하가 방지된다.  As described above, in the present invention, after the interlayer insulating film is formed, a trench is formed in a portion coinciding with the oxide spacers on both side walls of the gate electrode, and a pattern is formed by embedding an antireflection film of organic material in the trench. In the process of forming the contact hole, the anti-reflection film pattern serves as an etch stop layer to prevent loss of the oxide spacer, and a contact hole having a smaller size than the contact hole pattern formed in the mask is formed. Therefore, the present invention can sufficiently secure the overlap margin with the gate electrode without increasing the distance between the gate electrodes, and the yield decrease is prevented because the number of dies per wafer is not reduced.

Claims (5)

반도체 기판 상에 게이트 전극을 형성한 후 상기 게이트 전극 양측부의 반도체 기판에 접합영역을 형성하는 단계와,Forming a junction region on the semiconductor substrate at both sides of the gate electrode after forming the gate electrode on the semiconductor substrate; 상기 게이트 전극 양측벽에 스페이서를 형성한 후 전체 상부면에 캡핑층 및 층간절연막을 순차적으로 형성하는 단계와,Forming spacers on both sidewalls of the gate electrode and sequentially forming a capping layer and an interlayer insulating film on the entire upper surface thereof; 상기 스페이서와 일치되는 부분의 상기 층간절연막에 소정 깊이의 트렌치를 형성하고 상기 트렌치 내에 유기물을 매립하는 단계와,Forming a trench having a predetermined depth in the interlayer insulating film at a portion coinciding with the spacer, and filling an organic material in the trench; 상기 층간절연막 상에 감광막 패턴을 형성한 후 상기 감광막 패턴과 상기 유기물을 마스크로 이용한 식각 공정으로 노출된 부분의 층간절연막과 캡핑층을 제거하여 상기 접합영역이 노출되도록 콘택홀을 형성하는 단계와,Forming a contact hole to expose the junction region by forming a photoresist pattern on the interlayer insulating layer and then removing the interlayer insulating layer and the capping layer exposed by an etching process using the photoresist pattern and the organic material as a mask; 상기 감광막 패턴을 제거하고, 상기 콘택홀을 매립하는 플러그를 형성하는 단계와,Removing the photoresist pattern and forming a plug to fill the contact hole; 상기 유기물이 제거되는 시점까지 상기 플러그 및 상기 층간 절연막을 평탄화 공정으로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.And removing the plug and the interlayer insulating layer by a planarization process until the organic material is removed. 제 1 항에 있어서, 상기 게이트 전극은 게이트 산화막, 플로팅 게이트, 유전체막 및 콘트롤 게이트가 적층된 구조로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the gate electrode is formed by stacking a gate oxide film, a floating gate, a dielectric film, and a control gate. 제 1 항에 있어서, 상기 캡핑층은 질화막으로 형성하며, 상기 층간절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the capping layer is formed of a nitride film, and the interlayer insulating film is formed of an oxide film. 제 1 항에 있어서, 상기 트렌치의 깊이는 상기 감광막 패턴의 두께보다 두꺼우며, 상기 반도체 기판에서 상기 트렌치까지의 높이는 상기 반도체 기판에서 상기 캡핑층까지의 높이와 상기 제거된 층간절연막의 두께보다 큰 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the depth of the trench is thicker than the thickness of the photoresist pattern, the height from the semiconductor substrate to the trench is greater than the height from the semiconductor substrate to the capping layer and the thickness of the removed interlayer insulating film. A method for forming a contact hole in a semiconductor device. 제 1 항에 있어서, 상기 유기물은 반사방지막인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the organic material is an antireflection film.
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KR100256237B1 (en) 1993-12-29 2000-05-15 김영환 Method of forming contact hole
KR19980055932A (en) * 1996-12-28 1998-09-25 김영환 Contact hole formation method of semiconductor device
KR20010003469A (en) * 1999-06-23 2001-01-15 김영환 method of manufacturing semiconductor device
KR20010065822A (en) * 1999-12-30 2001-07-11 박종섭 Method for forming contact hole of semiconductor device

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