KR100256237B1 - Method of forming contact hole - Google Patents

Method of forming contact hole Download PDF

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KR100256237B1
KR100256237B1 KR1019930030788A KR930030788A KR100256237B1 KR 100256237 B1 KR100256237 B1 KR 100256237B1 KR 1019930030788 A KR1019930030788 A KR 1019930030788A KR 930030788 A KR930030788 A KR 930030788A KR 100256237 B1 KR100256237 B1 KR 100256237B1
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film
forming
layer
oxide film
metal oxide
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KR1019930030788A
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Korean (ko)
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KR950021107A (en
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은용석
이호석
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE: A method for forming a contact hole is to simplify the number of processes and to improve a design margin. CONSTITUTION: A field oxide layer(2), a gate oxide layer(3), and a polysilicon layer(4) are deposited on a silicon substrate(1), and are selectively etched to form a word line pattern. An insulating layer(10) having a high etching selectivity is deposited on the entire surface of the substrate, and is selectively etched to form a spacer insulating layer on a sidewall of the word line pattern. An insulating layer(100) having a high etching selectivity is formed on the entire surface of the substrate, and is planarized with a planarizing layer(6). After a polysilicon layer(7) is deposited on the entire surface of the substrate to function as a contact mask, the polysilicon layer is selectively etched to expose the planarizing layer. A metallic oxide film(20) is formed on the entire surface of the substrate in such a way that an edge thereof is sharpened, and is annealed.

Description

콘택홀 형성방법How to Form Contact Holes

제1a도 내지 제1g도는 본 발명에 따른 콘택홀 형성공정을 나타내는 예시도.1A to 1G are exemplary views showing a contact hole forming process according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film

3 : 게이트산화막 4,7 : 다결정실리콘막3: gate oxide film 4,7 polycrystalline silicon film

5 : 질화막 6 : 평탄화막5: nitride film 6: planarization film

10,10',10 : 절연막 20 : 금속산화막10,10 ', 10 Insulation film 20 Metal oxide film

본 발명은 반도체 소자 제조공정중 금속 배선과 하부층 배선과의 연결을 위한 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole for connecting a metal wiring and a lower layer wiring during a semiconductor device manufacturing process.

반도체 소자의 집적화가 가속됨에 따라 일정 크기 이하의 콘택 예를 들면 64메가 디램급에서는 0.5마이크로미터 이하 규모의 콘택 형성을 위한 포토레지스터 형성 공정이 어렵게 되었다. 종래의 기술로, 다결정실리콘막을 이용한 PSSAC(Poly Silicon Self Aligned Contact), 건식 식각(Dry etch)의 비등방성 식각(Unisot-ropic etch) 특성을 이용한 공정들이 쓰이고 있으나, 공정의 복잡성과 만족할 만한 설계 여유도(Margine) 획득이 어려운 단점이 따른다.As the integration of semiconductor devices is accelerated, the photoresist formation process for contact formation of a certain size or less, for example, a contact size of 0.5 micrometer or less, becomes difficult in a 64 mega DRAM class. Conventionally, processes using polysilicon self-aligned contact (PSSAC) and dry etch (Unisot-ropic etch) characteristics using a polysilicon film have been used, but the complexity of the process and a satisfactory design margin It is difficult to obtain Margine.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 공정은 단순화하면서도 설계여유도는 증대된 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a contact hole with a simplified design but increased design flexibility.

상기 목적을 달성하기 위하여 본 발명은 콘택홀 형성방법에 있어서, 실리콘기판에 필드산화막, 게이트산화막, 다결정실리콘막을 차례로 형성하고, 상기 다결정실리콘막, 게이트산화막을 선택식각하여 워드라인 패턴을 형성하는 단계; 전체구조 상부에 금속산화막과의 식각선택비가 높은 절연막을 형성한, 선택식각하여 상기 워드라인 패턴 측벽에 스페이서 절연막을 형성하는 단계; 전체구조 상부에 금속산화막과의 식각선택비가 높은 절연막을 다시 형성한 뒤, 평탄화막으로 평탄화하는 단계; 전체구조 상부에 콘택 마스크로 쓰일 다결정실리콘막을 증착한 뒤 상기 다결정실리콘막을 선택식각하여 콘택 형성부위의 상기 평탄화막을 노출시키는 단계; 전체구조 상부에 금속산화막을 가장자리 부분이 뾰족하게 되도록 형성하고, 열처리 하는 단계; 상기 금속산화막을 소정부위 식각한 후, 평탄화막 및 절연막의 식각 선택비를 이용해 식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a contact line, in which a field oxide film, a gate oxide film, and a polysilicon film are sequentially formed on a silicon substrate, and the word line pattern is formed by selectively etching the polysilicon film and the gate oxide film. ; Forming a spacer insulating layer on sidewalls of the word line pattern by selectively etching an insulating layer having a high etching selectivity with the metal oxide layer on the entire structure; Re-forming an insulating film having a high etching selectivity with the metal oxide film on the entire structure, and then flattening the flattening film; Depositing a polysilicon layer to be used as a contact mask on the entire structure, and then selectively etching the polysilicon layer to expose the planarization layer on the contact forming portion; Forming a metal oxide film on the entire structure such that an edge thereof becomes sharp, and performing heat treatment; And etching the metal oxide layer by a predetermined portion, using the etching selectivity of the planarization layer and the insulating layer.

본 발명은 플라즈마보조 화학기상증착(Plasma Enhanced Chemical Vapor Deposition, PECVD)된 금속산화막 특히, Ta2O5의 특성중 하나인 가장자리 부분이 뾰족해지는 커스핑(Cusping) 현상을 충분히 활용하여 Ta2O5스페이서를 형성하고, 또한 BPSG, TEOS 등의 산화막과 Ta2O5등의 금속산화막 간의 식각 선택비(Etch Selectivity) 현저한 특성을 이용하여 미세 콘택홀을 형성하는 기술이다.The present invention is plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) a metal oxide in particular, to take full advantage of the coarse ping (Cusping) developer becomes one of the edge portions of the features of the Ta 2 O 5 pointed Ta 2 O 5 It is a technique for forming a fine contact hole by forming a spacer and using the outstanding characteristics of etching selectivity between an oxide film such as BPSG and TEOS and a metal oxide film such as Ta 2 O 5 .

이때, 커스핑 현상은 막을 형성하고자 하는 부위인 단차가 있는 하부막의 윗부분에 반응가스가 집중되어 다른 부분보다 두껍게 증착되는 현상을 일컬는다. 편, 건식 식각(Dry etch) 장비의 산화막 식각조건에서 각 물질에 대한 식각 특성은 CHF3/CF4/Ar 혼합가스를 적절히 조절해서 얻을 수 있으며, 관심 있는 재료의 식각비는 아래 표 1.과 같다.In this case, the cusp phenomenon refers to a phenomenon in which a reaction gas is concentrated on the upper portion of the lower layer having a step, which is a portion to be formed, and is deposited thicker than other portions. In the oxide etching conditions of dry etching equipment, the etching characteristics of each material can be obtained by appropriately adjusting the CHF 3 / CF 4 / Ar mixed gas, and the etch ratios of the materials of interest are shown in Table 1. same.

상기 표에서 알 수 있는 바와 같이 Ta2O5와 BPSG의 식각선택비는 1 대 6 정도가 된다.As can be seen from the table, the etching selectivity of Ta 2 O 5 and BPSG is about 1 to 6.

그러면, 상기 기술을 구현하는 공정방법을 첨부된 도면 제1a도 내지 제1h도를 통하여 구체적으로 살펴보자.Next, a process method for implementing the technique will be described in detail with reference to FIGS. 1A to 1H.

먼저, 제 1a 도는 실리콘기판(1)에 필드산화막(2), 게이트산화막(3)을 성장시키고, 워드라인으로 쓰일 다결정실리콘막(4)을 증착한 뒤 불순물을 도핑한 상태의 단면도이다.First, FIG. 1A is a cross-sectional view of growing a field oxide film 2 and a gate oxide film 3 on a silicon substrate 1, depositing a polysilicon film 4 to be used as a word line, and then doping impurities.

제 1b 도는 상기 다결정실리콘막(4) 상부에 질화막(5)을 증착한 후 마스크 작업으로 상기 질화막(5), 다결정실리콘막(4), 게이트산화막(3)을 선택식각하여 워드라인 패턴을 형성한 상태의 단면도이다.In FIG. 1B, after the nitride film 5 is deposited on the polysilicon film 4, a word line pattern is formed by selectively etching the nitride film 5, the polysilicon film 4, and the gate oxide film 3 by a mask operation. It is sectional view of one state.

제 1c 도는 전체구조 상부에 TEOS막을 증착한 다음, 선택식각하여 상기 워드라인 패턴 측벽에 스페이서 TEOS막(10)을 형성한 상태의 단면도이다.FIG. 1C is a cross-sectional view of a spacer TEOS film 10 formed on the sidewall of the word line pattern by selectively etching the TEOS film on the entire structure.

제 1d 도는 전체구조 상부에 TEOS막(100)을 다시 증착한 뒤 평탕화를 위해 BPSG막(6)을 증착하고 고온에서 플로우시킨 상태의 단면도이다.1D is a cross-sectional view of a state in which the TEOS film 100 is again deposited on the entire structure, and then the BPSG film 6 is deposited for leveling and flowed at a high temperature.

제 1e 도는 전체구조 상부에 콘택 마스크로 쓰일 다결정실리콘막(7)을 증착한 뒤 마스크 작업하여, 상기 다결정실리콘막(7)을 선택식각하여 콘택 형성부위의 상기 BPSG막(6)을 노출시킨 상태의 단면도이다.1e or the mask is formed by depositing a polysilicon film 7 to be used as a contact mask on the entire structure, and then selectively etching the polysilicon film 7 to expose the BPSG film 6 on the contact forming portion. It is a cross section of.

제 1f 도는 전체구조 상부에 스페이서 Ta2O5막(20)을 가장자리 부분이 뾰족하게(Cusp) 되도록 증착하고, 700℃ 이상의 온도에서 열처리한 상태의 단면도이다.FIG. 1F is a cross-sectional view of the spacer Ta 2 O 5 film 20 deposited on the entire structure so as to have a sharp edge and heat-treated at a temperature of 700 ° C. or higher.

제 1g 도는 상기 Ta2O5막(20)을 소정부위 식각한 후, BPSG막(6) 및 TEOS막(100,10')의 식각 선택비를 이용해 콘택홀을 완성한 상태의 단면도이다.FIG. 1G is a cross-sectional view of a state in which a contact hole is completed using an etching selectivity of the BPSG film 6 and the TEOS films 100 and 10 'after etching a predetermined portion of the Ta 2 O 5 film 20.

상기와 같이 이루어지는 본 발명은 종래 비트라인 콘택 형성공정으로 사용되고 있는 다결정실리콘막 자기정렬 콘택(Poly Silicon Self Aligned Contact)의 증착공정이 5단계, 식각공정이 5단계, 마스크 공정이 1단계로 모두 11단계나 되지만, 본 발명은 증착공정 3단계, 식각공정 2단계, 마스크공정 1단계의 6단계로 공정을 줄임으로써 공정을 단순화시킬 수 있으며, 공정 여유도 확보가 용이한 효과도 아울러 얻을 수 있다.According to the present invention, the deposition process of the polysilicon film self-aligned contact (Poly Silicon Self Aligned Contact), which is conventionally used as a bit line contact forming process, is performed in five steps, etching in five steps, and mask in one step. However, the present invention can simplify the process by reducing the process to six steps, three steps of the deposition process, two steps of the etching process, and one step of the mask process, it is also possible to obtain the effect of easy to secure the process margin.

Claims (4)

반도체 소자 제조공정중 금속 배선과 하부층 배선과의 연결을 위한 콘택홀 형성방법에 있어서, 실리콘기판(1)에 필드산화막(2), 게이트산화막(3), 다결정실리콘막(4)을 차례로 형성하고, 상기 다결정실리콘막(4), 게이트산화막(3)을 선택식각하여 워드라인 패턴을 형성하는 단계; 전체구조 상부에 금속산화막과의 식각선택비가 높은 절연막(10)을 형성한, 선택식각하여 상기 워드라인 패턴 측벽에 스페이서 절연막(10')을 형성하는 단계; 전체구조 상부에 금속산화막과의 식각선택비가 높은 절연막(100)을 다시 형성한 뒤, 평탄화막(6)으로 평탄화하는 단계; 전체구조 상부에 콘택 마스크로 쓰일 다결정실리콘막(7)을 증착한 뒤 상기 다결정실리콘막(7)을 선택식각하여 콘택 형성부위의 상기 평탄화막(6)을 노출시키는 단계; 전체구조 상부에 금속산화막(20)을 가장자리 부분이 뾰족하게 되도록 형성하고, 열처리 하는 단계; 상기 금속산화막(20)을 소정부위 식각한 후, 평탄화막(6) 및 절연막(100,10')의 식각 선택비를 이용해 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 콘택홀 형성방법.In the method for forming a contact hole for connecting a metal wiring and a lower layer wiring during a semiconductor device manufacturing process, a field oxide film 2, a gate oxide film 3, and a polysilicon film 4 are sequentially formed on a silicon substrate 1. Forming a word line pattern by selectively etching the polysilicon layer 4 and the gate oxide layer 3; Forming a spacer insulating film 10 'on the sidewalls of the word line pattern by selectively etching the insulating film 10 having a high etching selectivity with the metal oxide film over the entire structure; Re-forming the insulating film 100 having a high etching selectivity with the metal oxide film on the entire structure, and then flattening the flattening film 6; Depositing a polysilicon layer (7) to be used as a contact mask on the entire structure, and then selectively etching the polysilicon layer (7) to expose the planarization layer (6) at the contact forming portion; Forming a metal oxide film 20 on the entire structure such that the edges thereof become sharp, and performing heat treatment; And etching the metal oxide film 20 by using an etching selectivity of the planarization film 6 and the insulating films 100 and 10 '. 제1항에 있어서, 상기 금속산화막(20)은 Ta2O5막인 것을 특징으로 하는 콘택홀 형성방법.The method of claim 1, wherein the metal oxide film is a Ta 2 O 5 film. 제2항에 있어서, 상기 금속산화막(20)과의 식각선택비가 높은 절연막(10)은 BPSG막, TEOS막 중 어느 하나인 것을 특징으로 하는 콘택홀 형성방법.3. The method of claim 2, wherein the insulating film having a high etching selectivity with respect to the metal oxide film is one of a BPSG film and a TEOS film. 제1항에 있어서, 상기 워드라인 패턴 형성단계는 다결정실리콘막(4) 상부에 질화막(5) 형성후 소정부위 식각하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 콘택홀 형성방법.The method of claim 1, wherein the forming of the word line pattern further comprises etching a predetermined portion after forming the nitride film (5) on the polysilicon film (4).
KR1019930030788A 1993-12-29 1993-12-29 Method of forming contact hole KR100256237B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030054669A (en) * 2001-12-26 2003-07-02 주식회사 하이닉스반도체 Method for forming a metal line
KR100953025B1 (en) 2003-05-09 2010-04-14 주식회사 하이닉스반도체 Method for forming contact hole in a semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100232224B1 (en) * 1996-11-16 1999-12-01 김영환 Method of forming metal interconnector of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030054669A (en) * 2001-12-26 2003-07-02 주식회사 하이닉스반도체 Method for forming a metal line
KR100953025B1 (en) 2003-05-09 2010-04-14 주식회사 하이닉스반도체 Method for forming contact hole in a semiconductor device

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