KR100682166B1 - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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KR100682166B1
KR100682166B1 KR1020000036942A KR20000036942A KR100682166B1 KR 100682166 B1 KR100682166 B1 KR 100682166B1 KR 1020000036942 A KR1020000036942 A KR 1020000036942A KR 20000036942 A KR20000036942 A KR 20000036942A KR 100682166 B1 KR100682166 B1 KR 100682166B1
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forming
insulating film
bit line
charge storage
storage electrode
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KR20020002690A (en
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김대영
김준기
이동덕
공필구
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Ceramic Engineering (AREA)
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Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자 제조 공정 중 자기 정렬(Self align)의 방법으로 콘택을 형성함에 있어서 전하 저장 전극 영역이 식각되는 부분에 빈 공간(Void)을 만들어 둠으로써 전하 저장 전극을 형성하는 공정 마진을 증가시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in forming a contact by a self alignment method in a semiconductor device manufacturing process, a void is formed in a portion where an electric charge storage electrode region is etched. A method of increasing the process margin for forming a charge storage electrode is provided.

Description

반도체 소자의 제조방법{Manufacturing method for semiconductor device}Manufacturing method for semiconductor device

도 1 내지 도 7의 각 (a)는 본 발명의 방법에 따른 반도체 소자의 제조 공정 단계를 도시한 평면도.
도 1 내지 도 7의 각 (b)는 상기 도 1 내지 도 7의 각 (a)의 XX' 방향에 따른 단면도.1 (a) to 7 (a) are plan views showing the manufacturing process steps of the semiconductor device according to the method of the present invention.
(B) of FIG. 1 thru | or 7 is sectional drawing along the XX 'direction of said (a) of FIG.

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도 1 내지 도 7의 각 (c)는 상기 도 1 내지 도 7의 각 (a)의 YY' 방향에 따른 단면도.(C) of FIG. 1 thru | or 7 is sectional drawing along the YY 'direction of angle (a) of said FIG.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

1 : 반도체 기판 2 : 워드라인1 semiconductor substrate 2 word line

3 : 워드라인 스페이서 4 : 제1 절연막3: word line spacer 4: first insulating film

5 : 랜딩플러그 폴리실리콘 6 : 제2 절연막5: landing plug polysilicon 6: second insulating film

7 : 공간(Void) 8 : 비트라인7: Void 8: Bitline

9 : 비트라인 스페이서 10 : 제3 절연막9 bit line spacer 10 third insulating film

11 : 제1 감광막 패턴 12 : 전하 저장 전극용 콘택11: first photosensitive film pattern 12: contact for charge storage electrode

13 : 제3 절연막의 식각부위 14 : 제4 절연막13 etching portion of the third insulating film 14 fourth insulating film

15 : 식각 방지막 16 : 전하 저장 전극 형성용 산화막15 etch stop layer 16 oxide film for charge storage electrode formation

17 : 제2 감광막 패턴17: second photosensitive film pattern

18 : 전하 저장 전극 영역 18: charge storage electrode region

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자 제조 공정 중 자기 정렬(Self align)의 방법으로 콘택을 형성함에 있어서 전하 저장 전극 영역이 식각되는 부분에 빈 공간(Void)을 만들어 둠으로써 전하 저장 전극을 형성하는 공정 마진을 증가시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in forming a contact by a self alignment method in a semiconductor device manufacturing process, a void is formed in a portion where an electric charge storage electrode region is etched. A method of increasing the process margin for forming a charge storage electrode is provided.

자기 정렬에 의한 방법으로 콘택을 형성하는 종래의 기술에서는 콘택을 형성하기 위한 식각을 하는 과정에서 식각 해야 할 양이 많을 경우 식각 장벽으로 사용하는 다른 물질도 같이 소진되어 콘택 형성 공정이 중간에 중지되는 문제가 있다.In the conventional technique of forming a contact by a self-aligned method, when a large amount of etching is required in the process of etching to form a contact, other materials used as an etch barrier are also exhausted and the contact forming process is stopped in the middle. there is a problem.

따라서, 반도체 소자가 고집적화됨에 따라 상기한 종래의 자기 정렬의 방법으로는 공정을 진행할 수 없게 되는 문제점이 있다. 특히 캐패시터 형성 공정에 있어서 전하 저장 전극 형성용 산화막의 높이가 점점 증가하므로 캐패시터 형성 공정 마진이 점점 감소하는 문제가 있다.Therefore, there is a problem that the process cannot be performed by the conventional self-alignment method as the semiconductor device is highly integrated. In particular, in the capacitor forming process, since the height of the oxide film for forming the charge storage electrode is gradually increased, there is a problem that the capacitor forming process margin gradually decreases.

상기한 종래의 문제점을 감안하여, 본 발명은 자기정렬의 방법으로 식각할 때 식각할 부분을 빈 공간(Void)으로 만들고 후속으로 식각할 시에는 식각해야할 양을 상대적으로 적게 하여 식각 장벽물질을 보호할 수 있는 원리를 이용하며 이를 캐패시터 형성시 이용하도록 함으로써, 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.In view of the above-described conventional problems, the present invention protects the etching barrier material by making the portion to be etched into a void when etching by the self-aligning method and relatively small amount to be etched during subsequent etching. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the yield and reliability of the manufacturing process of the semiconductor device by using the principle that can be used and when forming the capacitor.

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은,
반도체 기판 상부에 워드라인을 형성하고, 상기 워드라인의 양 측벽에 워드라인 스페이서를 형성한 후, 랜딩플러그 폴리실리콘을 포함하는 제 1 절연막을 형성하는 단계와, 전체 구조 상부에 제 2 절연막을 형성하고, 제 2 절연막 상부에 비트라인을 형성한 후, 비트라인 스페이서를 형성하는 단계와, 전체 구조 상부에 제 3 절연막을 형성하되, 비트라인과 비트라인 사이의 영역에 빈 공간(Void)이 형성되도록 하는 단계와, 제 3 절연막 상부에 전하 저장 전극 영역을 차단하는 제 1 감광막 패턴을 형성하는 단계와, 제 1 감광막 패턴을 식각 장벽으로 하여 상기 랜딩플러그 폴리실리콘이 드러나도록 상기 제 3 절연막 및 제 2 절연막을 식각 하고, 제 1 감광막 패턴을 제거하는 단계와, 전체구조 상부에 제 4 절연막을 형성하고 평탄화하는 단계와, 전체구조 상부에 식각 방지막을 형성한 후, 전하 저장 전극 형성용 산화막을 형성하고, 전하 저장 전극을 영역을 노출시키는 제 2 감광막 패턴을 형성하는 단계와, 제 2 감광막 패턴을 식각 장벽으로 하여 랜딩플러그 폴리실리콘이 노출되도록 상기 전하 저장 전극 형성용 산화막, 식각 방지막, 제 4 절연막, 제 3 절연막 및 제 2 절연막을 순차적으로 식각하는 단계 및 전체구조 표면에 전하 저장 전극 형성용 물질을 형성하고 평탄화한 후, 전체구조 표면에 유전체막을 형성하고, 플레이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
Forming a word line on the semiconductor substrate, forming word line spacers on both sidewalls of the word line, forming a first insulating film including a landing plug polysilicon, and forming a second insulating film on the entire structure And forming a bit line spacer over the second insulating film, and forming a bit line spacer, forming a third insulating film over the entire structure, and forming a void in a region between the bit line and the bit line. And forming a first photoresist pattern on the third insulating layer, the first photoresist pattern blocking the charge storage electrode region, and using the first photoresist pattern as an etch barrier to expose the landing plug polysilicon. Etching the second insulating film, removing the first photoresist pattern, forming and planarizing a fourth insulating film on the entire structure, and After forming the etch stop layer, forming an oxide film for forming a charge storage electrode, forming a second photoresist pattern for exposing the region of the charge storage electrode, and exposing the landing plug polysilicon using the second photoresist pattern as an etch barrier. Sequentially etching the oxide storage film, the anti-etching film, the fourth insulating film, the third insulating film, and the second insulating film to form the charge storage electrode forming material and planarizing the surface of the entire structure, And forming a plate electrode on the dielectric film.

여기서, 워드라인은 폴리실리콘 및 텅스텐 실리콘의 적층구조로 형성하고, 비트라인과 비트라인 사이에 형성된 빈 공간의 높이는 비트라인의 높이보다 높게 형성하고, 스텝 커버리지가 좋지 않은 PE-산화막을 사용하되, 비트라인과 비트라인 사이의 빈 공간은 랜딩플러그 폴리실리콘 상부의 제 2 절연막을 습식 식각 방법으로 제거한 후 수행하는 것을 특징으로 한다. 또한, 제 2 감광막 패턴으로 전하 저장 전극 형성용 산화막을 식각하되, 식각 방지막의 상부까지 식각하고 제 2 감광막 패턴을 제거한 후 다시 그 하부의 절연막을 식각하는 것을 특징으로 한다.Here, the word line is formed of a laminated structure of polysilicon and tungsten silicon, and the height of the empty space formed between the bit line and the bit line is higher than the height of the bit line, and a PE oxide film having poor step coverage is used. The empty space between the bit line and the bit line is performed after removing the second insulating film on the landing plug polysilicon by a wet etching method. In addition, the oxide film for forming the charge storage electrode may be etched using the second photoresist layer pattern, and the upper portion of the etch stop layer may be etched, the second photoresist layer pattern is removed, and the lower insulating layer may be etched again.

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이하 첨부된 도면을 참조하여 본 발명에 대해 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

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도 1 내지 도 7 은 본 발명의 방법에 따른 반도체 소자의 제조 공정 단계를 도시한 도면으로서,1 to 7 illustrate the manufacturing process steps of the semiconductor device according to the method of the present invention.

상기 각 도면의 (a)는 평면도, (b) 및 (c) 는 상기 각 도 (a)의 XX' 및 YY' 방향에 따른 단면을 도시한 도면이다.(A) of each said figure is a top view, (b) and (c) are the figure which showed the cross section along the XX 'and YY' direction of said each figure (a).

도 1을 참조하면, 반도체 기판(1) 상부에 워드라인(2)을 형성하고, 워드라인(2)의 양 측벽에 워드라인 스페이서(3)를 형성한 후, 랜딩플러그 폴리실리콘(5)을 포함하는 제 1 절연막(4)을 형성한다. 이때, 워드라인(2)은 폴리실리콘 및 텅스텐 실리콘의 적층구조로 형성하는 것이 바람직하다.
다음에는, 제 2 절연막(6) 상부에 비트라인(8)을 형성한 후, 비트라인(8)의 양 측벽에 비트라인 스페이서(9)를 형성한다. 이때, 비트라인 스페이서(9)는 실리콘 질화막으로 형성하는 것이 바람직하다.
여기서, 실리콘 질화막으로 된 비트라인 스페이서(9)를 형성한 후 비트라인 스페이서(9)를 식각 장벽으로하여 랜딩플러그 폴리실리콘(5) 상부의 제 2 절연막(6)을 소정 부분 식각 한 다음 후속 공정을 진행할 수 있다.Referring to FIG. 1, the word line 2 is formed on the semiconductor substrate 1, the word line spacers 3 are formed on both sidewalls of the word line 2, and then the landing plug polysilicon 5 is formed. A first insulating film 4 is formed. At this time, the word line 2 is preferably formed of a laminated structure of polysilicon and tungsten silicon.
Next, after the bit line 8 is formed on the second insulating film 6, the bit line spacers 9 are formed on both sidewalls of the bit line 8. At this time, the bit line spacer 9 is preferably formed of a silicon nitride film.
Here, after forming the bit line spacer 9 made of a silicon nitride film, the second insulating film 6 on the landing plug polysilicon 5 is partially etched using the bit line spacer 9 as an etch barrier, and then a subsequent process. You can proceed.

그 다음에는, 전체구조 상부에 제 3 절연막(10)을 형성하는데 스텝 커버리지(step-coverage)가 좋지 않은 PE-산화막을 이용하여 비트라인(8)과 비트라인(8)의 사이에 영역에 빈 공간(7)이 형성되도록 한다. 이때, 빈 공간(7)의 높이는 비트라인(8)의 높이보다 더 높게 형성하는 것이 바람직하다.Next, a third insulating film 10 is formed over the entire structure, and a PE-oxide film having poor step coverage is used to fill the region between the bit line 8 and the bit line 8. Allow the space 7 to be formed. At this time, the height of the empty space 7 is preferably formed higher than the height of the bit line (8).

도 2를 참조하면, 전체 구조 상부에 감광막을 코팅한 후 셀 영역에서 전하 저장 전극 영역이 될 부분은 가리고 비트라인 콘택이 들어가는 부분이 노출되도록 워드라인의 길이 방향으로 감광막을 노광 및 현상하여 제 1 감광막 패턴(11)을 형성한다.Referring to FIG. 2, after the photoresist is coated over the entire structure, the photoresist is exposed and developed in the longitudinal direction of the word line so as to cover a portion of the cell region to be the charge storage electrode region and expose a portion where the bit line contact enters. The photosensitive film pattern 11 is formed.

도 3을 참조하면, 제 1 감광막 패턴(11)을 식각 장벽으로 노출된 제 3 절연막(10)을 식각 하여, 비트라인 콘택 영역 및 이와 인접한 소정 영역이 식각된 제 3 절연막(10)의 식각 영역을 형성한다. 다음에는, 제 1 감광막 패턴(11)을 제거한다.Referring to FIG. 3, the third insulating layer 10 having the first photoresist pattern 11 as an etch barrier is etched to etch the bit line contact region and the predetermined region adjacent to the third insulating layer 10. To form. Next, the first photosensitive film pattern 11 is removed.

도 4를 참조하면, 제 3 절연막의 식각 영역(13) 하부의 제 2 절연막(6)을 랜딩플러그 폴리실리콘(5)이 드러나도록 식각하고, 전체구조 상부에 제 4 절연막(14)을 형성하여 비트라인과 비트라인을 각각 분리시킨다.Referring to FIG. 4, the second insulating film 6 under the etching region 13 of the third insulating film is etched to expose the landing plug polysilicon 5, and the fourth insulating film 14 is formed on the entire structure. Separate bit lines and bit lines, respectively.

도 5를 참조하면, 제 4 절연막(14)을 평탄화한다. 이때, 평탄화는 화학적 기계적 연마(Chemical Mechanical Polishing) 공정을 이용하는 것이 바람직하다.Referring to FIG. 5, the fourth insulating film 14 is planarized. In this case, the planarization is preferably performed using a chemical mechanical polishing process.

도 6을 참조하면, 제 4 절연막(14)의 상부에 식각 방지막(15)으로 실리콘 질화막을 형성한 후, 그 상부에 전하 저장 전극 형성용 산화막(16)을 형성한다.
다음에는, 전하 저장 전극 형성용 산화막(16) 상부에 전하 저장 전극을 형성할 부분을 노출시키는 제 2 감광막 패턴(17)을 형성한다.Referring to FIG. 6, after forming the silicon nitride film as the etch stop layer 15 on the fourth insulating layer 14, the oxide film 16 for forming the charge storage electrode is formed thereon.
Next, a second photosensitive film pattern 17 is formed on the charge storage electrode forming oxide film 16 to expose a portion where the charge storage electrode is to be formed.

도 7을 참조하면, 제 2 감광막 패턴(17)을 식각장벽으로 하여 전하 저장 전극 형성용 산화막(16), 식각 방지막(15), 제 4 절연막(14), 제 3 절연막(10) 및 제 2 절연막(6)을 차례로 식각하고 랜딩플러그 폴리실리콘(5)이 드러나도록 하여 전하 저장 전극 영역(18)을 형성한다.
다음에는, 전하 저장 전극 영역(18) 표면에 전하 저장 전극 형성용 물질을 형성하고, 이를 평탄화하여 각각의 전하 저장 전극으로 분리시킨다.
그 다음에는, 전체구조 표면에 유전체막을 형성하고, 플레이트 전극을 형성하여 캐패시터를 완성한다.Referring to FIG. 7, an oxide film 16 for forming a charge storage electrode, an etch stop layer 15, a fourth insulating layer 14, a third insulating layer 10, and a second layer is formed using the second photoresist layer pattern 17 as an etch barrier. The insulating film 6 is sequentially etched and the landing plug polysilicon 5 is exposed to form the charge storage electrode region 18.
Next, a material for forming a charge storage electrode is formed on the surface of the charge storage electrode region 18, and flattened to separate the charge storage electrode into respective charge storage electrodes.
Next, a dielectric film is formed on the entire structure surface, and plate electrodes are formed to complete the capacitor.

상술한 바와 같이, 본 발명에 따른 반도체 소자의 제조 방법은 전하 저장 전극 영역이 형성되는 영역의 제 3 및 제 2 절연막에 빈 공간을 미리 형성하여 둠으로써 후속의 전하 저장 전극 형성용 산화막 식각 공정을 용이하게 수행할 수 있도록 한다. 또한, 빈 공간을 랜딩플러그 폴리실리콘이 노출될 때까지 형성함으로써, 전하 저장 전극 영역을 형성하는 공정에서 전하 저장 전극 콘택 플러그가 형성되므로 전하 저장 전극을 형성하는 공정 단계를 감소시킬 수 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an empty space is previously formed in the third and second insulating films of the region where the charge storage electrode region is to be formed, thereby performing the subsequent oxide film etching process for forming the charge storage electrode. Make it easy to perform. In addition, by forming the empty space until the landing plug polysilicon is exposed, the charge storage electrode contact plug is formed in the process of forming the charge storage electrode region, thereby reducing the process step of forming the charge storage electrode.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 제조 방법은 자기 정렬(Self align)의 방법으로 콘택을 형성함에 있어서 전하 저장 전극 영역이 형성되는 부분에 빈 공간(Void)을 만들어 둠으로써 전하 저장 전극을 형성하는 공정 마진을 향상시키고, 그에 따른 반도체 소자의 불량 발생을 감소시키므로 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in forming a contact by a self align method, charge storage is performed by making a void in a portion where a charge storage electrode region is formed. Since the process margin for forming the electrode is improved, and thereby the occurrence of defects in the semiconductor device is reduced, the yield and reliability of the semiconductor device can be improved.

Claims (6)

반도체 기판 상부에 워드라인을 형성하고, 상기 워드라인의 양 측벽에 워드라인 스페이서를 형성한 후, 랜딩플러그 폴리실리콘을 포함하는 제 1 절연막을 형성하는 단계;Forming a word line on the semiconductor substrate, forming word line spacers on both sidewalls of the word line, and then forming a first insulating layer including a landing plug polysilicon; 전체 구조 상부에 제 2 절연막을 형성하고, 제 2 절연막 상부에 비트라인을 형성한 후, 비트라인 스페이서를 형성하는 단계;Forming a second insulating film over the entire structure, forming a bit line over the second insulating film, and then forming a bit line spacer; 전체 구조 상부에 제 3 절연막을 형성하되, 비트라인과 비트라인 사이의 영역에 빈 공간(Void)이 형성되도록 하는 단계;Forming a third insulating film on the entire structure, wherein a void is formed in a region between the bit line and the bit line; 상기 제 3 절연막 상부에 전하 저장 전극 영역을 차단하는 제 1 감광막 패턴을 형성하는 단계;Forming a first photoresist pattern on the third insulating layer to block the charge storage electrode region; 상기 제 1 감광막 패턴을 식각 장벽으로 하여 상기 랜딩플러그 폴리실리콘이 드러나도록 상기 제 3 절연막 및 제 2 절연막을 식각 하고, 제 1 감광막 패턴을 제거하는 단계;Etching the third insulating film and the second insulating film to expose the landing plug polysilicon using the first photoresist pattern as an etch barrier, and removing the first photoresist pattern; 전체구조 상부에 제 4 절연막을 형성하고 평탄화하는 단계;Forming and planarizing a fourth insulating film on the entire structure; 전체구조 상부에 식각 방지막을 형성한 후, 전하 저장 전극 형성용 산화막을 형성하고, 전하 저장 전극을 영역을 노출시키는 제 2 감광막 패턴을 형성하는 단계;Forming an etch stop layer over the entire structure, forming an oxide film for forming a charge storage electrode, and forming a second photoresist pattern for exposing a region of the charge storage electrode; 상기 제 2 감광막 패턴을 식각 장벽으로 하여 랜딩플러그 폴리실리콘이 노출되도록 상기 전하 저장 전극 형성용 산화막, 식각 방지막, 제 4 절연막, 제 3 절연막 및 제 2 절연막을 순차적으로 식각하는 단계; 및Sequentially etching the charge storage electrode forming oxide film, the etch stop film, the fourth insulating film, the third insulating film, and the second insulating film so that the landing plug polysilicon is exposed using the second photoresist pattern as an etch barrier; And 전체구조 표면에 전하 저장 전극 형성용 물질을 형성하고 평탄화한 후, 전체구조 표면에 유전체막을 형성하고, 플레이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a dielectric film on the surface of the entire structure and forming a plate electrode after forming and planarizing the material for forming a charge storage electrode on the surface of the entire structure. 제 1 항에 있어서,The method of claim 1, 상기 워드라인은 폴리실리콘 및 텅스텐 실리콘의 적층구조로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The word line is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of polysilicon and tungsten silicon. 제 1 항에 있어서,The method of claim 1, 상기 비트라인과 비트라인 사이에 형성된 빈 공간의 높이는 비트라인의 높이보다 높게 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.And the height of the empty space formed between the bit line and the bit line is higher than the height of the bit line. 제 1 항 및 제 3 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 빈 공간의 형성은 스텝 커버리지가 좋지 않은 PE-산화막을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법. The formation of the empty space is a method of manufacturing a semiconductor device, characterized in that a stepped PE-oxide film is used. 제 1 항에 있어서,The method of claim 1, 상기 비트라인과 비트라인 사이의 빈 공간은 랜딩플러그 폴리실리콘 상부의 제 2 절연막을 습식 식각 방법으로 제거한 후 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The empty space between the bit line and the bit line is performed after removing the second insulating film on the landing plug polysilicon by a wet etching method. 제 1 항에 있어서,The method of claim 1, 상기 제 2 감광막 패턴으로 전하 저장 전극 형성용 산화막을 식각하되, 식각 방지막의 상부까지 식각하고 제 2 감광막 패턴을 제거한 후 다시 그 하부의 절연막을 식각하는 것을 특징으로 하는 반도체 소자의 제조방법.And etching an oxide film for forming a charge storage electrode using the second photoresist pattern, followed by etching up to an upper portion of the etch stop layer, removing the second photoresist pattern, and etching the insulating film under the second photoresist pattern.
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