KR20000013396A - Capacitor and fabricating method of the same - Google Patents

Abstract

PURPOSE: A capacitor is provided to secure a misalignment margin between a storage node and a storage node contact and reduce a step between a cell region and a core region. CONSTITUTION: The capacitor comprises a semiconductor substrate, a gate electrode formed on the semiconductor device to be surrounded by insulating material, a first and a second self-aligned contact pads formed between the gate electrode to be electrically connected to the semiconductor substrate, a landing pad overlapped with the first self-aligned contact pad and a part of the insulating material on the gate electrode, a storage electrode formed on both sidewalls of an insulating layer formed on an overall surface of the semiconductor substrate to be electrically connected to the landing pad, wherein the landing pad is so large as not to be electrically connected to the second self-aligned contact pad.

Description

Capacitor and method of fabrication the capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a capacitor of a dynamic random access memory (DRAM) device and a manufacturing method thereof.

As the integration of DRAM increases due to the development of semiconductor process technology, 1Giga Bit DRAM has been developed and 4Giga DRAM is being developed, and the device size is required to have a line width of 0.15㎛ or less. The contact hole size and mis-align margin are also decreasing.

In order to solve this problem, self-aligned contact has been proposed because the contact hole should be as small as possible in the photolithography process and the alignment accuracy in the photo equipment should be increased. When forming the contacts by the self-aligning method, it is possible to reduce the burden on the formation of small contact holes in the photo process, the alignment margin is increased, and all areas can be used for the contact as compared to the small contact holes. Can be lowered.

1A to 1D are sequential flowcharts illustrating processes of a conventional capacitor and a method of manufacturing the same, and are cross-sectional views taken along a direction parallel to a word line.

Referring to FIG. 1A, in a conventional capacitor and a method of manufacturing the same, a shallow trench isolation 12 is first formed in the semiconductor substrate 10 to define active and inactive regions. The first oxide layer 14 is formed to completely cover the semiconductor substrate 10 including the trench isolation 12.

The pad forming contact hole is formed by etching the first oxide layer 14 on the active region using a contact hole forming mask. After filling the contact hole with a polysilicon layer, the polysilicon layer is self-aligned to be electrically connected to the semiconductor substrate 10 by flat etching by a chemical mechanical polishing (CMP) process so as to be parallel to the first oxide layer 14. Storage node contact pads 16 are formed. At this time, in a subsequent process, a bit line contact pad for electrically connecting the bit line with the semiconductor substrate 10 is also formed at the same time (not shown).

In FIG. 1B, a second oxide layer 18 is formed on the first oxide layer 14 including the storage node contact pads 16. Next, a bit line contact hole is formed by etching the second oxide film 18 using a contact hole forming mask. (Not shown) The bit line contact hole is filled with a polysilicon film, and then the poly A bit line contact is formed by etching the silicon film evenly parallel to the second oxide film 18 (not shown). Next, the bit line contact is electrically connected to the bit line contact on the second oxide film 18. Bit line 20 is formed.

A third oxide film 22, a nitride film 24, and a fourth oxide film 26 are sequentially formed on the second oxide film 18 including the bit line 20. The nitride film 24 is a film for preventing the bit line 20 from being oxidized by oxygen (O ₂ ) of the dielectric film when the capacitor dielectric film is formed in a subsequent process.

Referring to FIG. 1C, a fourth insulating film 26, a nitride film 24, a third insulating film 22, and a third insulating film are formed until the surface of the storage node contact pad 16 is exposed using a contact hole forming mask. The storage node contact holes 27 are formed by sequentially etching the two insulating layers 18.

In FIG. 1D, a polysilicon film is formed on the fourth insulating layer 26 including the storage node contact hole 27 to form a storage node. Thereafter, the polysilicon layer is patterned using a mask for forming a storage node to form a storage node 30 electrically connected to the storage node contact 28. The storage node 30 is formed to a thickness of more than 10000Å. The capacitor dielectric layer 32 and the capacitor upper electrode 34 are sequentially formed on the fourth insulating layer 26 including the storage node 30 to form a capacitor.

Here, even when the long-term alignment contacts are formed, as the devices become highly integrated, misalignment between the self-aligned contact pads, the storage node contacts, the storage node contacts, the storage nodes, the storage node contacts, the bit lines, the storage node contacts, and the gates (mis- align) margins are shrinking below 40nm. In addition, after the formation of the storage node, the step between the cell and the core becomes more than 10000 GPa in a subsequent metal wiring process, resulting in a problem that the process becomes difficult due to a small depth of focus (DOF) margin during the photo process.

The present invention has been proposed to solve the above-mentioned problems, and it is possible to secure a misalignment margin between the storage node and the storage node contact when forming the storage node and to form the storage node contact, and to reduce the step between the cell and the core. It is an object of the present invention to provide a capacitor and a method of manufacturing the same which can reduce the photo process margin in a subsequent wiring process.

1A to 1D are sequential flowcharts showing processes of a conventional capacitor and a method of manufacturing the same, and are cross-sectional views taken along a direction parallel to a word line;

2A to 2F are sequential flowcharts showing processes of the capacitor of the present invention and a method of manufacturing the same;

3A to 3F are sequential flowcharts showing processes of the capacitor of the present invention and a method of manufacturing the same, and are cross-sectional views cut in parallel with a word line;

4A and 4B are cross-sectional views after dry etching using a linear photoresist film pattern; And

5 is a cross-sectional view illustrating a step between a cell and a peripheral circuit according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: trench isolation

14, 108: first oxide film 106: gate electrode

16, 110, 110a; Contact pads 20, 116: beat line

124: storage node landing pad 28: storage node contact

30, 130: storage node 32, 132: capacitor dielectric film

34, 133: capacitor upper electrode

(Configuration)

According to the present invention for achieving the above object, the capacitor manufacturing method comprises the steps of simultaneously forming the first and second self-aligned contact pads that are electrically connected to the semiconductor substrate through the first insulating film formed on the semiconductor substrate; ; Forming a second insulating film on the first insulating film; Forming a bit line on the second insulating film, the upper material and both side walls of the insulating material having an etch selectivity with the second insulating film; Forming a landing pad electrically connected to the first self-aligned contact pad between the bit line and the bit line, wherein the landing pad is formed to be large within a range that is not electrically connected to the second self-aligned contact pad; ; Forming a third insulating film on the entire surface of the semiconductor substrate by a thickness sufficient to obtain a desired capacitance; Forming a storage node contact hole by etching the third insulating layer using the mask for forming the storage node contact hole until the upper surface of the landing pad is exposed; Forming a first conductive layer along a surface of the storage node contact hole; And sequentially forming a capacitor dielectric film and a second conductive film on the third insulating film and the first conductive film.

In a preferred embodiment of the method, the method may further include forming a material layer having an etch selectivity with the first insulating layer on the bit line and the first contact pad.

In example embodiments, the method may further include dry etching the first conductive layer to form a spacer before forming the dielectric layer.

According to the present invention for achieving the above object, a capacitor includes a semiconductor substrate; A gate electrode formed to be surrounded by an insulating material on the semiconductor substrate; First and second self-aligned contact pads formed between the gate electrodes to be electrically connected to the semiconductor substrate; A landing pad formed to overlap with the first self-aligned contact pad and a portion of the insulating material on the gate electrode; A storage node formed on both sidewalls of the insulating layer formed on the front surface of the semiconductor substrate to be electrically connected to the landing pad, wherein the landing pad is formed to be large in a range that is not electrically connected to the second self-aligned contact pad.

(Action)

Referring to FIG. 2E, in the novel capacitor and the method of manufacturing the same, a second insulating film is formed on the first insulating film including the first and second self-aligned contact pads. A bit line is formed on the second insulating layer to surround the upper side and both side walls of the insulating material having an etching selectivity with the second insulating layer. A landing pad is formed between the bit line and the bit line in electrical connection with the first self-aligned contact pad. In this case, the landing pad is largely formed within a range that is not electrically connected to the second self-aligned contact pad. After forming the third insulating film on the front surface of the semiconductor substrate to a thickness capable of obtaining a desired capacitance, the storage node contact is etched by using the storage node contact hole forming mask to etch the third insulating film until the upper surface of the landing pad is exposed. Holes are formed. After the first conductive layer is formed along the surface of the storage node contact hole, a capacitor dielectric layer and a second conductive layer are sequentially formed on the third insulating layer and the first conductive layer. By using such a capacitor and a method of manufacturing the same, it is possible to use a capacitor up to the thickness of an oxide film formed to form a storage node contact, thereby reducing the step difference between a cell and a core, thereby securing a photo process margin in a subsequent wiring forming process. By forming the storage node landing pads large, it is possible to prevent short-circuits of the storage node contacts and bit lines caused by misalignment when forming the storage node contacts, the storage node contacts and the gate electrodes, and the storage node and storage node landings. The margin of misalignment with the pad can be increased.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2F, 3A to 3F, 4A and 4B, and FIG. 5.

In the capacitor of the present invention, a gate electrode surrounded by an insulating material is formed on a semiconductor substrate. First and second contact pads are formed between the gate electrodes to be electrically connected to the semiconductor substrate. A third contact pad is formed to overlap with the first contact pad and a portion of the insulating material on the gate electrode. Storage nodes are formed on both sidewalls of the insulating layer formed on the front surface of the semiconductor substrate to be electrically connected to the third contact pads. In this case, the third contact pad is largely formed within a range that is not electrically connected to the second contact pad.

The manufacturing method of the capacitor is as follows.

2A through 2F are sectional views sequentially showing processes of a capacitor and a method of manufacturing the same according to an exemplary embodiment of the present invention, and are cross-sectional views taken along line with bit lines. 3A to 3F are flowcharts sequentially illustrating processes of a capacitor and a method of manufacturing the same according to an exemplary embodiment of the present invention, and are cross-sectional views taken along line with word lines. 4A and 4B are cross-sectional views after dry etching using a line-shaped photoresist film pattern, and FIG. 5 is a cross-sectional view showing a step between a cell and a peripheral circuit according to an embodiment of the present invention.

2A and 3A, in the capacitor manufacturing method of the present invention, a trench isolation 102 is first formed in the semiconductor substrate 100 to define an active region and an inactive region. Next, a gate electrode forming conductive film 104 is formed on the semiconductor substrate 100 with the gate oxide film 103 interposed therebetween. The conductive film 104 has a structure in which a polysilicon film and a silicide film are stacked, for example. A mask nitride film 105 is formed on the conductive film 104. Then, the gate nitride 106 is formed by sequentially etching the mask nitride film 105 and the conductive film 104 using a gate electrode forming mask.

Thereafter, a nitride film is formed on the semiconductor substrate 100 including the gate electrode 106. The gate electrode spacers 107 are formed on both sidewalls of the gate electrode by etching the entire surface of the nitride layer by an etch back process. The gate electrode spacer 107 is a film for insulating the conductive layer 104 from the self-aligned contact pad formed in a subsequent process.

A first oxide film 108 for interlayer insulation is formed on the semiconductor substrate 100 including the gate electrode 106. The pad forming contact hole is formed by etching the first oxide layer 108 using a self-aligning contact pad forming mask. Thereafter, a polysilicon film for pad formation is deposited on the first oxide film 108 including the contact hole. Next, the polysilicon film and the first oxide film 108 are etched evenly by a chemical mechanical polishing (CMP) process until the surface of the mask nitride film 105 is exposed, thereby being electrically connected to the semiconductor substrate 100. Self-aligned contact pads 110 and 110a are formed. The self-aligned contact pad 110a is a bit line self-aligned contact pad for electrically connecting the bit line with the semiconductor substrate 100.

2B and 3B, a second oxide film 112 is thinly formed on the entire surface of the semiconductor substrate 100 to insulate the self-aligned contact pad 110 from the bit line formed in a subsequent process. This is because after the bit line is etched in a subsequent process, the second oxide layer 112 may be separately etched to minimize the etching amount of the first oxide layer 108 during the additional etching of the second oxide layer 112. .

Next, a nitride film 113 is formed on the second oxide film 112. The nitride film 113 is formed to a thickness of about 100 GPa. A bit line contact hole is formed by sequentially etching the nitride film 113 and the second oxide film 112 until the surface of the self-aligned contact pad 110 is exposed using a bit line contact hole forming mask (Fig. Not shown).

The bit line forming conductive layer 114 and the mask nitride layer 115 are sequentially formed on the nitride layer 113 including the bit line contacts. The conductive film 114 is formed of, for example, a metal film such as tungsten (W). By using the bit line forming mask, the mask nitride film 115, the conductive film 114, and the nitride film 113 are anisotropically dry-etched in turn with the second oxide film 112 as an etch stop layer. An electrically connected bit line 116 is formed. Next, the second oxide film 112 is etched using the bit line forming mask until the surface of the self-aligned contact pad 110 is exposed.

Next, after removing the bit line forming mask, a nitride film is formed on the self-aligned contact pad 110 including the bit line 116. The nitride film spacer 117 is formed on both sidewalls of the bit line 116 and the second oxide film 112 by etching the entire surface of the nitride film through an etch back process.

Here, since the nitride film 113 has a small etching selectivity with tungsten, the conductive film 114, and a wet / dry etching selectivity with the second oxide film 112, the etching of the conductive film 114 is performed. At this time, the nitride film 115 is simultaneously etched, and the second oxide film 112 becomes an etch stop layer. The second oxide layer 112 may be etched during the wet etching of the oxide layer to form the landing pad contact hole, and the nitride layer 113 may have an etching selectivity of 100: 1 or more when wet etching with the second oxide layer 112. Therefore, the nitride layer 113 may prevent further etching to prevent a short circuit between the storage node landing pad and the bit line.

In addition, in a dry O ₂ annealing process performed in a subsequent Ta ₂ O ₅ capacitor dielectric film forming process, oxygen may pass through an oxide film to oxidize a metal film used as the bit line, wherein the mask nitride film ( Together with the 115 and the nitride film spacers 117, the penetration of oxygen can be prevented to effectively prevent oxidation of the bit line.

Next, a thin nitride film 118 is formed along the surfaces of the bit line 116 and the self-aligned contact pad 110. Thereafter, a third oxide film 120 is formed on the entire surface of the semiconductor substrate 100. The third oxide layer 120 is flatly etched to leave a thickness of about 700 μs on the bit line 116 by the CMP process. The thickness of the planarized third oxide film 120 is about 4000 kPa.

2C and 3C, a photoresist layer pattern 121 for forming a storage node landing pad is formed in a contact type by a photolithography process. An opening 122 is formed by anisotropic dry etching a portion of the third oxide layer 120 using the photoresist layer pattern 121 as a mask. 4A and 4B are cross-sectional views of the third oxide film 120 after partial anisotropic dry etching by patterning in a line shape.

The partial etching amount of the third oxide layer 120 is a storage node landing pad in consideration of the length that is etched and extended in the bit line direction and the pattern size patterned by photolithography during wet etching to form a subsequent storage node landing pad contact hole. The amount of etch must be taken into account to ensure that the wires are not electrically connected in the bit line direction.

For example, when the thickness of the third oxide layer 120 is about 4000 GPa and the cell unit pitch size is about 600 nm, the width of the photoresist layer pattern is patterned to about 150 nm, and the bridge of the storage node landing pad is formed. With a margin of around 50nm, you can make landing pads up to 550nm long. Therefore, it is possible to wet etch up to 200 nm in one direction except for the width of 150 nm of the photoresist film pattern.

Therefore, when dry etching to form the storage node landing pad, after etching 2000 Å or more, and wet etching about 2000 Å, the storage node landing pad having a length of 550 nm can be formed in a direction parallel to the word line.

2D and 3D, the landing pad contact hole is formed by isotropic wet etching the third oxide film 120 until the surface of the nitride film 118 is exposed using the landing pad contact hole forming mask 121. 123 is formed. As illustrated in FIG. 2D, the nitride layer 118 is a layer for preventing the first oxide layer 108 on both sides of the gate electrode 106 from being damaged during isotropic wet etching. Next, the nitride film 118 is entirely etched by an etch back process.

According to the method feature of the present invention, after the partial anisotropic dry etching of an appropriate amount of the third oxide film 120, the contact hole is extended by isotropic wet etching to form a contact hole 123 for forming a storage node landing pad. . At this time, since the isotropic etching is performed during the wet etching to form the storage node landing pad contact hole 123, a short circuit between the storage node landing pad and the bit line self-aligned contact pad 110a may be prevented.

2E and 3E, after removing the mask 121, a polysilicon film for pad formation is formed on the third oxide layer 120 including the storage node landing pad contact hole 123. Next, the polysilicon layer and the third oxide layer 120 are etched flatly by using the mask nitride layer 115 of the bit line as a etch stop layer by a CMP process, thereby electrically connecting the self-aligned contact pads 110. The storage node landing pad 124 is formed. The storage node landing pad 124 is separated in units of cells by the mask nitride layer 115 and the third oxide layer 120 on the bit line.

The fourth oxide film 125 is formed on the entire surface of the semiconductor substrate 100 by the height of the capacitor. By using the photoresist layer pattern 126 as a mask, the fourth oxide layer 125 is subjected to dry anisotropic etching until the surfaces of the storage node landing pad 124 and the bit line mask nitride layer 115 are exposed. 128) is formed.

2F and 3F, a polysilicon film 130 is formed on the fourth oxide film 125 and along both sidewalls and the bottom surface of the opening 128. Next, the polysilicon layer 130 on the fourth oxide layer 125 is removed, and the storage node, that is, the capacitor lower electrode 130 is etched by an etch back process in order to separate the storage node lower electrode in units of cells. Is formed. A capacitor dielectric layer 132 is formed on the fourth oxide layer 125 and along surfaces of the capacitor lower electrode 130 and the storage node landing pad 124. The capacitor dielectric layer 132 is formed of, for example, Ta ₂ O ₅ . Finally, a capacitor is formed by filling the opening 128 with a polysilicon film to form the capacitor upper electrode 133.

Here, since the lower electrode of the spacer type is formed in the oxide film, the storage node cross-sectional area which can be used is reduced compared to the conventional one, but by using the storage node landing pad, the thickness of the oxide film used to form the conventional storage node contact can be used as a capacitor. Surface area can be increased. In addition, the storage nodes are insulated with oxide layers to prevent short circuits between storage nodes.

When the upper electrode 133 is patterned by using a photoresist film pattern as a mask, the etching amount of the fourth oxide film 125 is set to 3000 kPa or less, thereby reducing the step h between the cell and the core. As shown in FIG. 5, the photo process margin is increased during the subsequent metal line 135 forming process.

According to the present invention, by using a capacitor up to the thickness of an oxide film formed to form a storage node contact, a step difference between a cell and a core can be reduced, thereby securing a photo process margin in a subsequent wiring forming process, and a storage node landing pad. By forming a larger value, the short circuit of the storage node contact and the bit line, the storage node contact and the gate electrode caused by the misalignment when forming the storage node contact can be prevented, and the misalignment margin between the storage node and the storage node landing pad is increased. It can be effected.

Claims (9)

Simultaneously forming first and second self-aligned contact pads which are formed in the semiconductor substrate and are electrically connected to the semiconductor substrate; Forming a second insulating film on the first insulating film; Forming a bit line on the second insulating film, the upper material and both side walls of the insulating material having an etch selectivity with the second insulating film; Forming a landing pad electrically connected to the first self-aligned contact pad between the bit line and the bit line, wherein the landing pad is formed to be large within a range that is not electrically connected to the second self-aligned contact pad; ; Forming a third insulating film on the entire surface of the semiconductor substrate by a thickness sufficient to obtain a desired capacitance; Forming a storage node contact hole by etching the third insulating layer using the mask for forming the storage node contact hole until the upper surface of the landing pad is exposed; Forming a first conductive layer along a surface of the storage node contact hole; And sequentially forming a capacitor dielectric film and a second conductive film on the third insulating film and the first conductive film. The method of claim 1, The first, second and third insulating films are oxide films, and the insulating material is a silicon nitride film. The method of claim 1, Wherein the first self-aligned contact pad is a storage node contact pad, the second self-aligned contact pad is a bit line contact pad, and the landing pad is a storage node landing pad. The method of claim 1, Forming a material layer having an etch selectivity with the first insulating layer on the bit line and the first self-aligned contact pad. The method of claim 4, wherein And the material layer is a silicon nitride film. The method of claim 1, The landing pad, Forming an insulating film on the entire surface of the semiconductor substrate; Anisotropic dry etching the thickness of the insulating layer using a contact hole forming mask; Isotropically wet etching the remaining thickness of the insulating layer until the surface of the material layer is exposed using the mask to form a contact hole; And The capacitor manufacturing method of filling the contact hole with a conductive film. The method of claim 1, When etching the third insulating film for forming the storage node contact hole, the third insulating film is etched to less than 3000Å thickness to reduce the step difference between the cell and the core to improve the subsequent photo process margins. The method of claim 1, And etching the first conductive layer to form a spacer before forming the dielectric layer. A semiconductor substrate; A gate electrode formed to be surrounded by an insulating material on the semiconductor substrate; First and second self-aligned contact pads formed between the gate electrodes to be electrically connected to the semiconductor substrate; A landing pad formed to overlap with the first self-aligned contact pad and a portion of the insulating material on the gate electrode; A storage node formed on both sidewalls of the insulating layer formed on the front surface of the semiconductor substrate to be electrically connected to the landing pad, And the landing pad is largely formed within a range that is not electrically connected to the second self-aligned contact pad.