KR100356776B1 - Method of forming self-aligned contact structure in semiconductor device - Google Patents

Abstract

A method of forming a self-aligned contact structure of a semiconductor device is provided. A first interlayer insulating film is formed on a semiconductor substrate having conductive pads, and a second interlayer insulating film having a low dielectric constant is formed on the first interlayer insulating film. A pair of wirings are formed in the second interlayer insulating film using a damascene process. On each wiring, a mask pattern is formed of an insulator film having a higher dielectric constant than the second interlayer insulating film. The width of each mask pattern is wider than the wiring below it. Using the mask patterns as an etching mask, the second interlayer insulating film and the first interlayer insulating film between the wirings are continuously etched to form a self-aligned contact hole exposing the conductive pads. A conductive film pattern is formed to fill the self-aligned contact hole. As a result, a second interlayer insulating film having a low dielectric constant is interposed between the conductive film pattern filling the self-aligned contact hole and the respective wirings, thereby reducing the coupling capacitance between the conductive film pattern and the wirings.

Description

A method of forming a self-aligned contact structure of a semiconductor device {METHOD OF FORMING SELF-ALIGNED CONTACT STRUCTURE IN SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a self-aligned contact structure.

As the degree of integration of semiconductor devices increases, the spacing between wirings becomes narrower. Accordingly, the probability of misalignment is gradually increased during the photolithography process for forming contact holes penetrating the interlayer insulating film between the parallel wires. In order to solve this misalignment, a technique for forming a self-aligned contact hole has recently been published.

Conventional techniques for forming self-aligned contact holes include forming a plurality of wirings on a semiconductor substrate whose sidewalls and top surfaces are covered with an insulator film, such as a silicon nitride film, and etching the silicon nitride film over the entire surface of the resultant. And forming a self-aligned contact hole for exposing the semiconductor substrate by etching the interlayer insulating film between the wirings with an insulating film having a selectivity, for example, a silicon oxide film. Here, even if the self-aligned contact hole is formed wider than the distance between adjacent wirings, the silicon nitride film surrounding the wirings has an etching selectivity with respect to the interlayer insulating film formed of the silicon oxide film, thereby preventing the wirings from being exposed. Can be. Therefore, the margin for misalignment may be increased during the photolithography process for defining the self-aligned contact hole.

However, the wirings are surrounded by a silicon nitride film having an etch selectivity with respect to an interlayer insulating film formed of a silicon oxide film. Therefore, a silicon nitride film having a larger dielectric constant than the silicon oxide film is interposed between the wirings and the conductive film filling the self-aligned contact hole in a subsequent process. As a result, the coupling capacitance between each wiring and the conductive film is increased to increase the delay time of the electrical signal applied to the wiring or the conductive film.

In addition, in the above-described prior art, the wirings may be formed of a metal film such as a tungsten film or a metal polyside film such as a tungsten polyside film in order to lower the resistance of the wirings. In this case, the wirings are formed by patterning the metal film or the metal polyside film. However, due to the surface morphology of the metal film, a bridge or the like may remain between the wires adjacent to each other during the photo / etching process for patterning the metal film or the metal polyside film. Accordingly, a problem may occur in which wires adjacent to each other are electrically connected to each other.

US Patent No. 5,614,765 discloses a multilevel interconnection structure manufactured through a dual damascene process. According to US Patent No. 5,614,765, an interlayer insulating film having a via hole exposing a predetermined area of the lower wiring and a groove etched to a depth shallower than the via hole is formed on the lower wiring, and the upper portion filling the via hole and the groove. Wiring is formed. Here, the via holes and grooves are formed through a single photographing process.

More specifically, the groove is formed on the interlayer insulating film to form a photoresist pattern defining a region in which the upper wiring is formed through a photolithography process, using the photoresist pattern as an etching mask thickness of the interlayer insulating film It is formed by etching to a shallower depth. Here, the groove is composed of a via portion and a conductive line portion. The width of the via portion should be wider than the width of the conductive line portion.

The via hole may form a conformal material film on the entire surface of the groove formed product, anisotropically etch the conformal material film to form a spacer on the sidewall of the groove area, and remove the residue of the interlayer insulating film exposed by the spacer. It is formed by etching to expose the lower wiring. Here, the conformal material film should be thinner than half of the width of the via portion and thicker than half of the width of the conductive line portion. Thus, after forming the spacer, the bottom of the groove of the via portion is exposed and the bottom of the groove of the conductive line portion is covered by the conformal material film.

As described above, according to US Pat. No. 5,614,765, the via hole is self-aligned with the upper wiring by a single photographic process. However, the via holes are not self-aligned with respect to the lower wiring. Accordingly, the U.S. Patent No. 5,614,765 is not suitable for forming a self-aligned contact hole penetrating an interlayer insulating film between adjacent lower interconnections.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a self-aligned contact structure capable of minimizing coupling capacitance between interconnections parallel to each other and a conductive layer pattern penetrating an interlayer insulating layer therebetween.

Another object of the present invention is to provide a method of forming a self-aligned contact structure capable of minimizing coupling capacitance between interconnections parallel to each other and a conductive film pattern penetrating an interlayer insulating film therebetween.

Another object of the present invention is to provide a method of forming a self-aligned contact structure that is easy to pattern wirings located on both sides of a conductive film pattern.

Another object of the present invention is to provide a method of forming a self-aligned contact structure capable of increasing the margin for transient etching while selectively etching an interlayer insulating film between parallel wires.

1 is a plan view of a typical DRAM cell.

FIG. 2 is a cross-sectional view for describing a contact structure according to the present invention according to I-I of FIG. 1.

3A to 3G are cross-sectional views illustrating a method of forming a self-aligned contact structure according to an embodiment of the present invention according to II of FIG. 1.

4A to 4C are cross-sectional views illustrating a method of forming a self-aligned contact structure according to another embodiment of the present invention according to I-I of FIG. 1.

In order to achieve the above technical problem, the self-aligned contact structure according to the present invention includes a conductive pad formed on a semiconductor substrate, a first interlayer insulating film covering the entire surface of the resultant product on which the conductive pad is formed, and the first interlayer insulating film. A pair of wirings, a mask pattern formed on each of the wirings, the width of which is wider than the width of each of the wirings, a region between the mask patterns, and the first interlayer insulating film, and electrically connected to the conductive pads. And a second interlayer insulating film interposed in a region between the conductive film pattern and the wirings.

The first interlayer insulating film and the second interlayer insulating film are preferably an insulator film having a low dielectric constant of 4 or less, preferably a silicon oxide film.

The mask pattern may include an etch stop layer pattern formed on each wiring line and first spacers formed on both sidewalls of the etch stop layer pattern. The mask pattern may be formed of an insulator film having an etch selectivity with respect to the first interlayer insulating film and the second interlayer insulating film, for example, a silicon nitride film. The mask pattern may have a "T" shape in which the width of the upper part is wider than the width of the lower part.

It is preferable that the wiring has a structure in which a barrier metal film and a wiring metal film are sequentially stacked. Here, the barrier metal film is preferably a titanium nitride film or a tantalum nitride film, and the wiring metal film is preferably a tungsten film.

A second spacer may be further provided between the mask pattern and the conductive film pattern. The second spacer is preferably formed of the same material film as the mask pattern, that is, a silicon nitride film.

In order to achieve the above and other technical problems, a method of forming a self-aligned contact structure according to the present invention comprises the steps of forming a conductive pad on a semiconductor substrate, and forming a first interlayer insulating film on the entire surface of the resultant product is formed; Forming first and second wirings parallel to each other on the first interlayer insulating film, forming a mask pattern having a width wider than the respective wirings on each of the wirings; Forming a conductive film pattern penetrating a region and the first interlayer insulating film and connected to the conductive pad.

The forming of the first and second wirings may include sequentially forming a first etch stop layer, a second interlayer insulating layer, a second etch stop layer, a third interlayer insulating layer, and a third etch stop layer on the first interlayer insulating layer. And successively patterning the third etch stop layer, the third interlayer insulating layer, and the second etch stop layer to form first and second recessed regions parallel to each other, and the first and second recessed regions. Forming a first spacer on sidewalls of the region, and continuously etching the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the first spacer as an etch mask to form first and second interconnections. Forming a groove and forming first and second wirings using a damascene process in the first and second wiring grooves, respectively.

The first to third interlayer insulating films may be formed of an insulator film having an etch selectivity with respect to the first to third etch stop films and the first spacers. In addition, the first to third interlayer insulating films may be formed. Is preferably formed of an insulator film having a lower dielectric constant than the first to third etch stop films and the first spacer. The third etch stop layer may be formed to a thickness thicker than the sum of the thickness of the first etch stop layer and the thickness of the second etch stop layer. Preferably, the first to third interlayer insulating layers are formed of silicon oxide, and the first to third etch stop layers are formed of silicon nitride. When manufacturing a high performance semiconductor device, the first and second wirings may be formed of a metal film.

The forming of the mask pattern may include forming a fourth etch stop layer that fills the first and second recessed regions on the entire surface of the first and second interconnections and exposes the third interlayer insulating layer. And continuously etching the fourth etch stop layer and the third etch stop layer until the fourth etch stop layer is formed in each recessed region. Here, the fourth etch stop layer pattern and the first spacers adjacent to both sides constitute a mask pattern. Therefore, the mask pattern has a width wider than the width of each wiring. The fourth etch stop layer may be formed of the same material layer as the third etch stop layer.

After the fourth etch stop layer pattern is formed, the exposed third interlayer dielectric layer is selectively removed to expose sidewalls of the first spacer and the second etch stop layer, and a second spacer is formed on the sidewalls of the first spacers. You may. In this case, after forming the second spacer, the second etch stop layer is continuously etched to expose the second interlayer insulating layer.

The forming of the conductive layer pattern may include anisotropic etching of the third interlayer insulating layer, the second etching blocking layer, the second interlayer insulating layer, the first etching blocking layer, and the first interlayer insulating layer using the mask patterns as an etching mask. Forming a contact hole exposing the conductive pad, and forming a conductive layer pattern in contact with the conductive pad in the contact hole.

As described above, according to the present invention, a conductive film pattern filling a contact hole formed by a self-aligning technique and a second interlayer insulating film having a low dielectric constant, such as a silicon oxide film, are interposed between the wirings and the wirings. It is possible to reduce the coupling capacitance of. In addition, it is easy to pattern the wirings by forming the wirings formed of the metal film by a damascene process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, the present invention is explained by taking a DRAM cell as an example, but the present invention is not limited to the DRAM cell but can be applied to all semiconductor devices.

First, the self-aligned contact structure according to the present invention will be described with reference to FIGS. 1 and 2.

1 is a plan view of a typical DRAM cell.

Referring to FIG. 1, an active region 1 is defined in a predetermined region of a P-type semiconductor substrate, and a pair of word lines 3a and 3b intersecting the active region 1 are disposed. An element isolation layer is formed around the active region 1. The active region 1 between the pair of word lines 3a and 3b corresponds to the common drain region D doped with N-type impurities. The pair of word lines 3a and 3b Among the active regions on both sides of the first word line 3a, the active region 1 facing the common drain region D corresponds to the first source region S1 doped with N-type impurities. In addition, the active region 1 facing the common drain region D among the active regions on both sides of the second word line 3b may be formed in the second source region S2 doped with N-type impurities. Corresponding.

A first storage node pad 17a electrically connected to the first source region S1 is disposed on the first source region S1, and the second source region S2 is disposed on the second source region S2. The second storage node pad 17b is electrically connected to the second storage node pad 17b. In addition, a bit line pad 17d electrically connected to the common drain region D is disposed on the common drain region D. FIG. The bit line pad 17d includes a protrusion extending toward one side of the common drain region D. FIG. First and second bit lines 35a and 35b are disposed on both sides of the active region 1 across the pair of word lines 3a and 3b, respectively. The first bit line 35a is electrically connected to the bit line pad 17d through a bit line contact hole 7 exposing a protrusion of the bit line pad 17d. Similarly, the second bit line 35b is electrically connected to another bit line pad (not shown).

2 is a cross-sectional view showing a self-aligned contact structure according to the present invention, a cross-sectional view according to I-1 of FIG.

Referring to FIG. 2, an isolation layer 13 defining an active region (1 in FIG. 1) is formed in a predetermined region of the semiconductor substrate 11. A second source region S2 doped with an impurity of a conductivity type different from that of the semiconductor substrate 11 is disposed in a predetermined region of the active region. The planarized insulator film 15 is formed on the resultant material on which the second source region S2 is formed. A conductive pad, that is, a second storage node pad 17b is disposed on the second source region S2. The second storage node pad 17b penetrates through a predetermined region of the planarized insulator film 15 and is electrically connected to the second source region S2. The first interlayer insulating layer 19 and the second interlayer insulating layer 23 are sequentially stacked on the entire surface of the resultant product on which the second storage node pad 17b is formed. The first and second interlayer insulating films 19 and 23 are preferably insulator films having low dielectric constants, that is, silicon oxide films.

A conductive layer pattern 45 penetrating the first and second interlayer insulating layers 19 and 23 is disposed on the second storage node pad 17b. In addition, first and second wirings 35a and 35b are positioned at both sides of the conductive film pattern 45, respectively. The first and second wirings 35a and 35b are formed in the first and second wiring grooves passing through the second interlayer insulating film 23, respectively, and are parallel to each other. Therefore, a second interlayer insulating film 23 is interposed between the conductive film pattern 45 and the first wiring 35a and the region between the conductive film pattern 45 and the second wiring 35b. The first and second wirings 35a and 35b are formed of a conductive film such as a metal film. More specifically, the first and second wirings 35a and 35b each include a barrier metal film and a wiring metal film that are sequentially stacked. A titanium nitride film or a tantalum nitride film is used as the barrier metal film, and a tungsten film is used as the wiring metal film.

A "T" type mask 38 is positioned on each of the wirings. The "T" type mask 38 includes an etch stop layer pattern 37a formed on each of the wirings and a first spacer 33 in contact with an upper side wall of the etch stop layer pattern 37a. Therefore, the upper width of the "T" type mask 38 is wider than the width of each wiring.

Meanwhile, the conductive layer pattern 45 extends to penetrate the regions between the “T” type masks 38. The second spacer 51 may be further provided on the sidewall of the first spacer 33. In this case, the second spacer 51 is interposed between the conductive film pattern 45 and each of the "T" type masks 38. The "T" type mask 38 and the second spacer 51 are formed of an insulator film having a high dielectric constant with respect to the first and second interlayer insulating films, preferably a silicon nitride film.

As described above, the self-aligned contact structure according to the present invention penetrates through the second interlayer insulating film between the wirings in which the conductive film patterns are parallel to each other. Therefore, a second interlayer insulating film formed of a silicon oxide film having a lower dielectric constant than the silicon nitride film is interposed between the conductive film pattern and each wiring. As a result, the coupling capacitance between the conductive film pattern and each wiring is reduced as compared with the prior art.

Next, a method of forming a self-aligned contact structure according to the present invention will be described.

3A to 3G are cross-sectional views illustrating a method of forming a self-aligned contact structure according to an embodiment of the present invention according to II of FIG. 1.

Referring to FIG. 3A, an isolation layer 13 for defining an active region in a predetermined region of the semiconductor substrate 11 is formed using a trench isolation process. The device isolation layer 13 may be formed using a local oxidation of silicon (LOCOS) process in addition to the trench device isolation process. A pair of word lines (3a and 3b of FIG. 1) are formed across the top of the active region. The second source region S2 is formed by implanting impurities of a different conductivity type from the semiconductor substrate 11 into the active region by using the pair of word lines as an ion implantation mask. At this time, the common drain region D and the first source region S1 of FIG. 1 are also formed at the same time.

The planarized insulator film 15 is formed on the entire surface of the resultant material in which the second source region S2 is formed. The planarized insulator film 15 is patterned to form a pad contact hole exposing the second source region S2. At this time, pad contact holes exposing the common drain region D and the first source region S1 shown in FIG. 1 are simultaneously formed. A conductive film, such as a doped polysilicon film, is formed on the entire surface of the resultant pad contact holes. The conductive layer is patterned to form conductive pads connected to the second source region S2, that is, second storage node pads 17b. In this case, a first storage node pad (17a of FIG. 1) connected to the first source region S1 and a bit line pad (17d of FIG. 1) connected to the common drain region D are simultaneously formed.

Referring to FIG. 3B, a first interlayer insulating layer 19, a first etch stop layer 21, a second interlayer insulating layer 23, and a second etch stop layer are formed on the entire surface of the resultant surface on which the second storage node pad 17b is formed. (25), the third interlayer insulating film 27, and the third etch stop film 29 are sequentially formed. The first to third interlayer insulating films 19, 23, and 27 may be formed of a silicon oxide film, and the first to third etch stop layers 21, 25, and 29 may be formed of the first to third interlayer insulating films. It is preferable to form an insulator film having an etching selectivity with respect to (19, 23, 27), for example, a silicon nitride film. In addition, the third etch stop layer 29 may be formed to a thickness thicker than the sum of the thickness of the first etch stop layer 21 and the thickness of the second etch stop layer 25. This is because a part of the third etch stop layer 29 must remain while forming a self-aligned contact hole penetrating the first and second etch stop layers 21 and 25 in a subsequent process. A first photoresist pattern 31 is formed on the third etch stop layer 29. The first photoresist pattern 31 exposes a predetermined region of the third etch stop layer 29. The exposed third etch stop layer 29 is positioned on both sides of the second storage node pad 17b.

Referring to FIG. 3C, the third etch stop layer 29, the third interlayer insulating layer 27, and the second etch stop layer 25 are continuously formed using the first photoresist pattern 31 as an etch mask. Etching is performed to form first and second recessed regions G1 and G2 parallel to each other. Next, the first photoresist pattern 31 is removed. A conformal insulator film having an etch selectivity with respect to the first and second interlayer insulating films 19 and 23 is formed on the entire surface of the resultant from which the first photoresist pattern 31 is removed, and then anisotropically etched. Spacers 33 are formed on sidewalls of the first and second recessed regions G1 and G2. The conformal insulator film is preferably formed of an insulator film having an etching selectivity with respect to the second interlayer insulating film 23, for example, a silicon nitride film. Alternatively, the first and second recessed regions G1 and G2 may be formed using the third etch stop layer 29 and the third interlayer insulating layer using the first photoresist pattern 31 as an etching mask. 27) may be formed by continuously etching. After the spacer 33 is formed, the second etch stop layer 25 is further etched to expose the second interlayer insulating layer 23.

Referring to FIG. 3D, the second interlayer insulating layer 23 and the first etch stop layer 21 are continuously etched using the third etch stop layer 29 and the spacer 33 as an etch mask to be parallel to each other. One first and second wiring grooves G1 'and G2' are formed. Next, although not shown in FIG. 3D, a predetermined region of the first interlayer insulating film 19 exposed by the first and second wiring grooves G1 ′ and G2 ′ is selectively etched to form a bit line pad (FIG. A bit line contact hole (7 in FIG. 1) that exposes 17d of 1 is formed.

Referring to FIG. 3E, a metal film filling at least the bit line contact hole and the wiring grooves G1 ′ and G2 ′ is formed on the entire surface of the resultant bit line contact hole. The metal film is preferably formed by laminating a barrier metal film and a wiring metal film in sequence. A titanium nitride film or a tantalum nitride film is widely used as the barrier metal film, and a tungsten film is widely used as the wiring metal film. The metal layer is etched back until the third etch stop layer 29 and the spacer 33 are completely exposed, and thus the first and second wiring grooves G1 ′ and G2 ′ are respectively etched in the first and second wiring grooves G1 ′ and G2 ′. 35a, 35b). In this case, as shown in FIG. 3E, the metal film may be etched back until the upper side walls of the first and second wiring grooves G1 ′ and G2 ′ are exposed.

As described above, the first and second wirings 35a and 35b are formed by a damascene process. Therefore, it is possible to fundamentally solve a phenomenon in which a bridge remains between the wirings adjacent to each other. In particular, when a metal film is directly patterned by a photo / etching process to form interconnects of a highly integrated semiconductor device, a bridge formed of metal residues may remain between the interconnections. This is because it is difficult to form a photoresist pattern having a desired profile by irregular reflection due to the rough surface of the metal film during the photolithography process. In addition, a recipe for etching a metal film generally exhibits a lower etching selectivity for a photoresist film used as an etching mask than a recipe for etching a non-metal film. Therefore, it is difficult to perform excessive etching to remove the bridge during the etching process for forming the metal wiring. As a result, according to the present invention, by forming the metal wiring in the damascene process, it is possible to fundamentally prevent the phenomenon that the bridge remains between the metal wirings.

A fourth etch stop layer 37 filling the first and second recessed regions G1 and G2 is formed on the entire surface of the resultant product on which the first and second interconnections 35a and 35b are formed. The fourth etch stop layer 37 may be formed of the same material layer as that of the first to third etch stop layers 21, 25, and 29, that is, a silicon nitride layer.

Referring to FIG. 3F, the fourth etch stop layer 37 is etched entirely until the upper surface of the third interlayer insulating layer 27 is exposed, so that the first and second recessed regions G1 and G2 are etched. A fourth etch stop layer pattern 37a is formed in the substrate. The fourth etch stop layer pattern 37a and the spacer 33 form a mask pattern 38. Here, when the upper surfaces of the first and second wirings 35a and 35b are lower than the upper surface of the second interlayer insulating film 23, the mask pattern 38 is "T" shaped. The width of each mask pattern 38 is wider than the width of each of the wirings 35a and 35b, as shown in FIG. 3F.

A fourth interlayer insulating layer 39 is formed on the entire surface of the resultant product in which the fourth etch stop layer pattern 37a is formed. The process of forming the fourth interlayer insulating film 39 may be omitted as necessary. The fourth interlayer insulating film 39 may be formed of the same material film as that of the first to third interlayer insulating films 19, 23, and 27, that is, a silicon oxide film.

A second photoresist pattern 41 is formed on the fourth interlayer insulating film 39. The second photoresist pattern 41 has an opening on the second storage node pad 17b. In this case, an opening of the second photoresist pattern 41 is formed wider than the width of the second storage node pad 17b to increase misalignment margin with respect to the second photoresist pattern 41.

Referring to FIG. 3G, the fourth interlayer dielectric layer 39, the third interlayer dielectric layer 27, and the second etch stop layer are formed using the second photoresist pattern 41 and the mask pattern 38 as an etch mask. 25, the contact hole 43 exposing the second storage node pad 17b by continuously etching the second interlayer insulating layer 23, the first etch stop layer 21, and the first interlayer insulating layer 19. Form. In this case, while the first and second etch stop layers 21 and 25 are etched, an upper portion of the mask pattern 38 around the contact hole 43 is also etched by the first depth T1.

Subsequently, the second photoresist pattern 41 is removed. A conductive film, such as a doped polysilicon film, is formed on the entire surface of the resultant product from which the second photoresist pattern 41 is removed, for example, the doped polysilicon film. The conductive layer is patterned to form a conductive layer pattern 45, ie, a second storage node electrode, electrically connected to the second storage node pad 17b in the contact hole 43. The conductive film may be patterned using a general photo / etch process or a chemical mechanical polishing process.

4A to 4C are cross-sectional views illustrating a method of forming a self-aligned contact structure according to another embodiment of the present invention according to II of FIG. 1. Here, parts denoted by the same reference numerals and symbols as those in FIGS. 3A to 3G denote the same members.

Referring to FIG. 4A, the second storage node pads 17b, the first and second wirings 35a and 35b, the spacers 33, and the fourth etch stop layer pattern are performed in the same manner as described with reference to FIGS. 3A to 3F. A 37a is formed to expose the third interlayer insulating film 23. The exposed third interlayer insulating layer 23 is selectively removed to expose the spacer 33, that is, sidewalls of the first spacer and the second etch stop layer 25. The third interlayer insulating layer 23 may be selectively removed using a wet etchant such as hydrofluoric acid solution (HF solution) or a buffered oxide etchant (BOE).

Referring to FIG. 4B, a conformal insulator film having an etch selectivity with respect to the first and second interlayer insulating films 19 and 23 on the entire surface of the resultant from which the third interlayer insulating film 23 is removed, preferably the The same material film as the first and second etch stop layers 21 and 25 is formed. The conformal insulator film is anisotropically etched to form second spacers 51 on sidewalls of the first spacers 33. In this case, the second etch stop layer 25 is also etched to expose the second interlayer insulating layer 23. The planarized interlayer insulating film 53 is formed on the entire surface of the resultant product on which the second spacers 51 are formed. The planarized interlayer insulating film 53 is formed of the same material film as that of the first to third interlayer insulating films, that is, a silicon oxide film. The process of forming the planarized interlayer insulating film 53 may be omitted as necessary.

Referring to FIG. 4C, the same photoresist pattern (not shown) is formed on the planarized interlayer insulating layer 53 as the second photoresist pattern 41 shown in FIG. 3F. The planarized interlayer dielectric layer 53, the second interlayer dielectric layer 23, the first etch stop layer 21 and the first layer may be formed using the photoresist pattern, the mask pattern 38, and the second spacer 51 as an etch mask. The first interlayer insulating layer 19 is continuously anisotropically etched to form a contact hole 55 exposing the second storage node pad 17b. In this case, while the first etch stop layer 21 is etched, an upper portion of the second spacer 51 and the mask pattern 38 around the contact hole 55 is also etched by a second depth T2. Therefore, the second depth T2 is shallower than the first depth T1 described in the embodiment of the present invention.

Subsequently, the photoresist pattern is removed. A conductive film filling the contact hole 55 is formed on the entire surface of the resultant from which the photoresist pattern is removed. The conductive layer is patterned in the same manner as in the exemplary embodiment of the present invention to form a conductive layer pattern 57 connected to the second storage node pad 17b, that is, a second storage node electrode.

As described above, according to the present invention, an insulator film having a low dielectric constant is interposed between the conductive film pattern filling the self-aligned contact hole and the wirings formed on both sides thereof. Therefore, the coupling capacitance between the conductive film pattern and each wiring can be reduced, so that the operating speed of the semiconductor device can be improved. In addition, by forming the first and second wirings parallel to each other using a damascene process, the patterning of the first and second wirings is easy. Therefore, when the first and second wirings are formed of a metal film, a phenomenon in which a bridge made of metal residue remains between the first and second wirings can be fundamentally solved.

Claims (18)

Forming a conductive pad on the semiconductor substrate; Forming a first interlayer insulating film on an entire surface of the resultant product on which the conductive pads are formed; Sequentially forming a first etch stop film, a second interlayer insulating film, a second etch stop film, a third interlayer insulating film, and a third etch stop film on the first interlayer insulating film; Successively patterning the third etch stop layer, the third interlayer insulating layer, and the second etch stop layer to form first and second recessed regions parallel to each other; Forming a first spacer on sidewalls of the first and second recessed regions; Continuously etching the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the first spacer as an etch mask to form first and second wiring grooves; Forming first and second wirings in the first and second wiring grooves using a damascene process, respectively; Forming a mask pattern on each of the wirings, the mask pattern having a wider width than the wirings and including the first spacers; And And forming a conductive film pattern penetrating the region between the mask patterns and the first interlayer insulating film and connected to the conductive pad. delete The method of claim 1, The first to third interlayer insulating films may be formed of an insulator film having an etch selectivity with respect to the first to third etch stop films and the first spacer. The method of claim 3, wherein The first to third interlayer insulating films may be formed of an insulator film having a lower dielectric constant than the first to third etch stop films and the first spacer. The method of claim 1, Forming the mask pattern is Forming a fourth etch stop layer on the entire surface of the resultant product on which the first and second wirings are formed to fill the first and second recessed regions; And The fourth etch stop layer and the fourth etch stop layer remain in the recessed regions by continuously etching the fourth etch stop layer and the third etch stop layer until the third interlayer insulating layer is exposed. Forming a mask pattern comprising the first spacers in contact with the sidewalls of the pattern. The method of claim 5, And the fourth etch stop layer is formed of the same material layer as that of the third etch stop layer. The method of claim 5, After forming the fourth etch stop layer pattern Removing the exposed third interlayer insulating layer to expose sidewalls of the first spacer and the second etch stop layer; Forming a second spacer on sidewalls of the first spacer; And And etching the second etch stop layer to expose the second interlayer dielectric layer. The method of claim 5, Forming the conductive film pattern The conductive pad may be formed by continuously anisotropically etching the third interlayer insulating layer, the second etch stop layer, the second interlayer insulating layer, the first etch stop layer, and the first interlayer insulating layer using the mask patterns as an etch mask. Forming a contact hole for exposing; Forming a conductive film filling the contact hole on the entire surface of the resultant product in which the contact hole is formed; And And patterning the conductive film. Forming a conductive pad on the semiconductor substrate; Sequentially forming a first interlayer insulating film, a first etch stop film, a second interlayer insulating film, a second etch stop film, a third interlayer insulating film, and a third etch stop film on the entire surface of the resultant product on which the conductive pad is formed; Continuously patterning the third etch stop layer, the third interlayer insulating layer, and the second etch stop layer to form first and second recessed regions on both sides of the upper portion of the conductive pad, respectively; Forming spacers on sidewalls of the first and second recessed regions; Continuously etching the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the spacer as an etch mask to form first and second wiring grooves; Forming first and second wirings in the first and second wiring grooves, respectively; Forming a fourth etch stop layer pattern that fills the first and second recessed regions and simultaneously removing the third etch stop layer; And The third interlayer insulating layer, the second etch blocking layer, the second interlayer insulating layer, the first etch blocking layer, and the first interlayer insulating layer are successively formed using the spacers and the fourth etch stop layer patterns as an etch mask. Forming an contact hole exposing the conductive pad by anisotropic etching. The method of claim 9, And the first to third interlayer insulating films are formed of a silicon oxide film. The method of claim 9, The first to third etch stop layer, the fourth etch stop layer pattern and the spacer is a silicon nitride film forming method, characterized in that formed in the silicon nitride film. The method of claim 9, And the third etch stop layer is formed to a thickness thicker than the sum of the thickness of the first etch stop layer and the thickness of the second etch stop layer. The method of claim 9, Forming the first and second wirings Forming a metal film filling at least the first and second wiring grooves on an entire surface of the resultant product in which the first and second wiring grooves are formed; And And etching back the metal layer until the third etch stop layer and the spacer are exposed. The method of claim 9, Forming the fourth etch stop layer pattern Forming a fourth etch stop layer on the entire surface of the resultant product on which the first and second wirings are formed to fill the first and second recessed regions; And And continuously etching the fourth etch stop layer and the third etch stop layer until the third interlayer insulating layer is exposed. Forming a conductive pad on the semiconductor substrate; Sequentially forming a first interlayer insulating film, a first etch stop film, a second interlayer insulating film, a second etch stop film, a third interlayer insulating film, and a third etch stop film on the entire surface of the resultant product on which the conductive pad is formed; Continuously patterning the third etch stop layer, the third interlayer insulating layer, and the second etch stop layer to form first and second recessed regions on both sides of the upper portion of the conductive pad, respectively; Forming a first spacer on sidewalls of the first and second recessed regions; Continuously etching the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the first spacer as an etch mask to form first and second wiring grooves; Forming first and second wirings in the first and second wiring grooves, respectively; Forming a fourth etch stop layer pattern that fills the first and second recessed regions and simultaneously removing the third etch stop layer; Removing the third interlayer insulating film to expose sidewalls of the first spacers; Forming a second spacer on sidewalls of the exposed first spacers; Etching the second etch stop layer exposed between the second spacers; And The conductive pad is continuously anisotropically etched from the second interlayer insulating layer, the first etch stop layer, and the first interlayer insulating layer using the fourth etch stop layer pattern, the first spacer, and the second spacer as an etch mask. Forming a contact hole for exposing the self-aligned contact structure. The method of claim 15, And the first to third interlayer insulating films are formed of a silicon oxide film. The method of claim 15, The first to third etch stop layer, the fourth etch stop layer pattern, the first spacer and the second spacer is a silicon nitride film forming method, characterized in that the formation. The method of claim 15, And the third etch stop layer is formed to a thickness thicker than the sum of the thickness of the first etch stop layer and the thickness of the second etch stop layer.