KR100498429B1 - Semiconductor memory device and method for fabricating thereof - Google Patents

Abstract

Disclosed are a semiconductor memory device and a method of manufacturing the same, which can solve a problem caused by misalignment between a storage electrode and a storage contact. The memory device includes a plurality of word lines arranged parallel to each other on a semiconductor substrate, a plurality of bit lines arranged to be orthogonal to the word lines, and separated from the word lines by an insulating film, and between the word lines. A first contact connecting the bit line with an active region of the semiconductor substrate of the semiconductor substrate, the bit line being parallel to the bit line, the bit line being separated by an insulating layer, and electrically adjacent to the adjacent cell. And a second contact formed to cross the center of the storage electrode and parallel to the word line, and to connect the storage electrode to an active region of the semiconductor substrate.

Description

Semiconductor memory device and method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a semiconductor memory device and a method for manufacturing the same, which can solve the problem caused by misalignment between the storage electrode and the storage contact.

In general, semiconductor memory devices, particularly DRAM (hereinafter, referred to as "DRAM"), have a sharp decrease in the area of a unit cell with an increase in the degree of integration. However, in order not to deteriorate the operating characteristics of the memory device, it is required to secure sufficient cell capacitor capacity. In order to obtain a capacity of a capacitor that does not degrade the operation characteristics of a memory device within the reduced cell area, a new material, that is, a method of using a high dielectric material, has been introduced. Three-dimensional structures such as a double stack structure, a fin structure, a spread stack structure, a box structure, and a cylindrical electrode structure are used. However, in addition to the introduction of such a new material and the method of increasing the surface area, various constraints that follow the pattern formation by the photo and etching process due to scaling down have been a problem.

1 is a plan view showing the layout of a typical stacked DRAM cell.

Reference numeral 100 denotes a mask pattern for forming an active region, 110 denotes a mask pattern for forming a word line, 120 denotes a mask pattern for forming a bit line, and 130 denotes a bit line and a semiconductor substrate. A mask pattern for forming a bit line contact to connect an active region of the mask, "140" is a mask pattern for forming a storage electrode, and "150" to form a storage contact connecting the storage electrode and the active region of the semiconductor substrate For each mask pattern.

2A to 2C are cross-sectional views illustrating a cross section in the AA ′ direction, that is, the word line direction of FIG. 1, according to a process sequence.

Referring to FIG. 2A, a device isolation film 4 is formed on the semiconductor substrate 2 for isolation between devices by a conventional method, for example, a shallow trench isolation (STI) method, followed by a conventional method. A transistor (not shown) having a gate insulating film, a gate electrode and a source / drain is formed in the semiconductor substrate 2. On the resultant formed transistors (not shown), an interlayer insulating film 6 is formed to insulate the transistors, and then a conductive film deposition and photolithography process is performed to carry out source / drain (not shown) of the transistors. The connected bit line 8 is formed. Next, an insulating film is deposited on the resultant formed bit line 8 to form an interlayer insulating film 10 for insulating the bit line.

Referring to FIG. 2B, a contact hole for connecting the storage electrodes and the source / drain of the transistor is formed by patterning the interlayer insulating layers 6 and 10 by a photolithography process using the mask pattern 150 for storage contact of FIG. 1. Form. A conductive material, for example, polysilicon doped with impurities is deposited on the entire surface of the resultant to form a conductive film 12a for a storage electrode.

Referring to FIG. 2C, the storage electrode 12 is connected to a source / drain (not shown) of the transistor by patterning the conductive layer for the storage electrode by a photolithography process using the mask pattern 140 for the storage electrode of FIG. 1. ).

At this time, if a misalignment occurs in the photolithography process for patterning the conductive film for the storage electrode, the side surface of the interlayer insulating film 10 formed to surround the bit line is exposed as shown in FIG. 2C. That is, when etching the conductive film for the storage electrode, overetch is typically performed for electrical separation between the storage electrodes of the adjacent cells, wherein a part of the polysilicon filled in the storage contact is etched. In addition, as a part of the interlayer insulating layer is removed by a subsequent cleaning process, a phenomenon in which the interlayer insulating layer 10 under the storage electrode is undercut may occur. As a result, the contact area between the storage electrode 12 and the storage contact becomes small to increase resistance, or the storage electrode 12 may fall. In addition, in the subsequent step of forming a dielectric film having an ONO (oxide film / nitride film) or NO (nitride film / oxide film) structure, when high temperature oxidation is performed to form an oxide film, the side surface of the interlayer insulating film 10 is exposed. A fatal problem may occur where oxygen penetrates and the bitline 8 is oxidized. This problem is exacerbated as the cell density increases and becomes unavoidable for devices of 1Giga DRAM or higher level.

Accordingly, an object of the present invention is to provide a semiconductor device having improved characteristics by preventing misalignment between a storage electrode and a storage contact.

Another object of the present invention is to provide a method of manufacturing the semiconductor device having improved characteristics by preventing misalignment between the storage electrode and the storage contact.

In order to achieve the above object, a semiconductor memory device according to the present invention includes a plurality of word lines arranged in parallel with each other on a semiconductor substrate, and orthogonal to the word lines and separated from the word lines by an insulating film. A bit line, a first contact connecting the active region of the semiconductor substrate and the bit line between the word lines, and a parallel portion between the bit lines and the bit line; A second electrode which is separated by the second electrode and is electrically separated from an adjacent cell, and is formed to cross the center of the storage electrode and parallel to the word line, and to connect the storage electrode to an active region of the semiconductor substrate. It is characterized by including.

The semiconductor device may further include an insulating film spacer formed to surround the word line to insulate the storage contact from the word line, or an insulating film spacer formed to surround the bit line and insulate the storage contact from the bit line. can do. A conductive pad may be further provided between the storage contact and the active region of the semiconductor substrate to connect the active region of the semiconductor substrate to the storage contact.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, including sequentially forming a first etch stop layer, an insulating layer, and a second etch stop layer on a semiconductor substrate, and forming a storage electrode. Etching the insulating layer and the second etch stop layer, filling a region from which the insulating layer and the second etch stop layer are removed with a first conductive layer, and forming the first conductive layer in the region where the storage contact is to be formed. Removing the layer and the first etch stop layer to expose the active region of the semiconductor substrate, and depositing and planarizing the second conductive layer on the entire surface of the resultant to form a storage electrode formed of the first and second conductive layers. And forming a dielectric film and a plate electrode on the resultant.

The first etch stop layer is preferably formed of a material having an excellent etching selectivity with respect to the insulating layer and the second etch stop layer for a predetermined etching process, in particular, the first etch stop layer is a polysilicon film, the insulation More preferably, the layer is formed of an oxide film, and the second etch stop layer is formed of a nitride film.

The step of filling the region from which the insulating layer and the second etch stop layer have been removed with the first conductive layer may include depositing a first conductive layer on a resultant from which the insulating layer and the second etch stop layer have been removed; Etching back the first conductive layer or chemically physical polyvinyl chloride (CMP).

The method may further include forming spacers on sidewalls of the insulating layer and the second etch stop layer after etching the insulating layer and the second etch stop layer in the region where the storage electrode is to be formed.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, the method including: (a) forming a transistor including a gate electrode and a source / drain on a semiconductor substrate; Forming a layer, (c) forming a bit line on the first insulating layer, the bit line being orthogonal to the gate electrode and connected to the drain, and (d) on a resultant on which the bit line is formed. Forming an insulating layer, (e) sequentially forming a first etch stop layer, a third insulating layer, and a second etch stop layer on the second insulating layer, and (f) a storage electrode to be formed. Etching the third insulating layer and the second etch stop layer in the region, (g) filling the region from which the third insulating layer and the second etch stop layer has been removed with the first conductive layer, and (h The first conductive layer, the first etch stop layer, and the etch stop layer in the region where the storage contact is to be formed Etching the second insulating layer and the first insulating layer in order to expose the source of the transistor, (i) depositing and planarizing a second conductive layer over the entire surface of the resultant, and (j) the second etch stop Forming a storage electrode consisting of the first and second conductive layers by etching the layer, the third insulating layer and the first etch stop layer, and (k) forming a dielectric film and a plate electrode on the resultant. Characterized in that.

The first etch stop layer may be formed of a material having an excellent etching selectivity with respect to the third and second etch stop layers for a predetermined etching process. In particular, the first to third insulating layers may be oxide films. The first etch stop layer may be formed of a polysilicon film, and the second etch stop layer may be formed of a nitride film.

The step (g) may include depositing a first conductive layer on a resultant from which the insulating layer and the second etch stop layer are removed, and etching back the first conductive layer or the insulating layer and the second layer. And depositing a first conductive layer on the resultant from which the etch stop layer is removed, and chemically physically polymerizing (CMP) the first conductive layer.

In the step (h), the first conductive layer and the first etch stop layer of the region where the storage contact is to be formed are sequentially etched, and then the patterned first conductive layer, the third insulating layer, the first and second etch stop are formed. Forming a spacer on sidewalls of the layer, and etching the second and first insulating layers using the second etch stop layer, the first conductive layer, and the spacer as a mask. In this case, the spacer is formed of the same material as the first and second conductive layers, but the spacer is preferably formed of a polysilicon film.

Between (a) and (b), the method may further include forming a spacer surrounding the gate electrode by depositing an insulating material on the semiconductor substrate on which the transistor is formed and then etching back. The method may further include forming a spacer surrounding the bit line by depositing an insulating material on the semiconductor substrate on which the bit line is formed and then etching back between the step (c) and the step (d). . In this case, the spacer may be formed of a material having excellent etching selectivity with respect to the first and second insulating layers for a predetermined etching process for etching the first and second insulating layers.

After the forming of the spacer, the method may further include forming a pad for connecting the source / drain and the storage contact on the semiconductor substrate on which the spacer is formed.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a layout diagram of a semiconductor memory device according to the present invention.

Reference numeral 200 denotes a mask pattern for forming an active region, 210 denotes a mask pattern for forming a word line, 220 denotes a mask pattern for forming a bit line, and 230 denotes a bit line and a semiconductor substrate. A mask pattern for forming a bit line contact to connect an active region of the mask, "240" is a mask pattern for forming a storage electrode, and "250" to form a storage contact for connecting the storage electrode and the active region of the semiconductor substrate For each mask pattern.

In comparison with the conventional layout shown in FIG. 1, the storage contact mask pattern 250 for connecting the storage electrode and the source / drain of the transistor is in a bar shape parallel to the mask pattern 210 for the word line. It can be seen that.

4A to 8A are cross-sectional views illustrating a cross section along the AA ′ direction of FIG. 3, that is, the word line direction, and FIGS. 4B to 8B are cross-sectional views illustrating the cross section along the B-B ′ direction, that is, the bit line direction, according to a process sequence.

Referring to FIGS. 4A and 4B, the device isolation film 34 is formed on the semiconductor substrate 32 by the conventional method, for example, shallow trench isolation (STI). A transistor including a gate insulating film 36, a gate electrode 38, and a source / drain (not shown) is formed in the semiconductor substrate 32 by a conventional method. On the resultant formed transistor, the first interlayer insulating film 40 is formed to insulate the transistor, and then a conductive film deposition and photolithography process is performed to connect the bit / source (not shown) of the transistor. Line 42 is formed. Next, an insulating film is deposited on the resultant bit line 42 to form a second interlayer insulating film 44 for insulating the bit line.

Next, a conductive film, for example, polysilicon 46 doped with impurities is deposited on the second interlayer insulating film 44 by several tens of nm, and then an oxide film 48 and a nitride film 50 are sequentially formed thereon. . The thickness of the oxide film 48 is determined according to the desired capacitance of the capacitor, the thickness of the conductive film for the storage electrode, that is, about the height of the capacitor, and the nitride film 50 is formed to a thickness of about several tens of nm.

Referring to FIGS. 5A and 5B, the polysilicon film of the region where the storage electrode is to be formed by anisotropically etching the nitride film 50 and the oxide film 48 in a photolithography process using the mask pattern 240 for the storage electrode of FIG. 3. Expose (46). When etching the oxide film 48, a photoresist pattern (not shown) used as a mask for patterning the nitride film may be used as a mask, or the patterned nitride film 50 may be used as a mask after removing the photoresist pattern. have. In this case, the polysilicon film 46 is used as an etch stop film in an etching process for patterning the oxide film.

Next, a conductive film for a storage electrode, for example, polysilicon 52 doped with impurities, is deposited on the entire surface of the resultant to fill the exposed area of the polysilicon, followed by chemical mechanical polishing (CMP). Or the etch back process is performed to planarize the polysilicon film 52. At this time, the nitride film 50 is used as an etching stopping layer of the planarization process.

6A and 6B, a photoresist pattern (not shown) is formed by applying a photoresist to the entire surface of the resultant, and then performing a mask exposure and development process using the mask pattern 250 for forming the storage contact of FIG. 3. Form. As shown in FIG. 3, the photoresist pattern is formed in a bar shape parallel to the word line 210 of FIG. 3. Using the photoresist pattern as a mask, the first and second polysilicon layers are sequentially anisotropically etched to expose the oxide layer in the region where the storage electrode is to be formed. In this process, polysilicon (52 in FIG. 5A) filled in the holes for forming the storage electrode is removed in the A-A 'direction, that is, the word line direction.

Next, after the photoresist pattern is removed, the second interlayer insulating film 44 and the first interlayer insulating film 40 are sequentially anisotropically etched using the nitride film 50 and the second polysilicon film 52 as an etching mask. A contact hole is formed that exposes the source / drain (not shown) of the transistor. Since the process of forming the contact hole is self-aligned by using the patterned nitride film and the second polysilicon film as a mask, the misaligned margin between the storage electrode and the storage electrode contact is sufficiently secured.

Referring to FIGS. 7A and 7B, after forming a conductive film for a storage electrode, for example, a third polysilicon film 54 doped with impurities, the nitride film 50 is used as an etch stop layer. Etch back or CMP is performed to planarize the surface of the third polysilicon film 54.

Referring to FIGS. 8A and 8B, the nitride and oxide films are sequentially anisotropically etched or wet-etched and removed using a third polysilicon film 54 as an etching mask, and then the final storage electrode is etched back by etching the first polysilicon film. Form 56.

Next, although not shown, a dielectric film and a conductive film are formed on the entire surface of the resultant in which the storage electrode 56 is formed, and then patterned to form the dielectric film and the plate electrode of the capacitor to complete the capacitor.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device in accordance with a second embodiment of the present invention, and is a cross-sectional view taken along the line AA ′ of FIG. 3.

If the size of the storage electrode is large, the size of the storage contact for connecting the storage electrode with the source / drain also increases. At this time, the storage contact and the bit line or the storage contact and the gate electrode may contact each other, which may cause a short circuit.

In this case, as shown in Fig. 9, the second polysilicon film (52 in Fig. 6B), the nitride film 50 and the oxide film 48 in the processes of Figs. 6A and 6B by the method of the first embodiment of the present invention. ) To form a polysilicon thin layer of about 5 to 30 nm on the entire surface of the resultant with the first polysilicon film 46 in the region where the storage contact is to be formed. A spacer 60 is formed on sidewalls of the second polysilicon layer (not shown), the nitride layer 50, the oxide layer 48, and the first polysilicon layer 46 that are etched back and patterned. Next, the spacer 60, the nitride film 50, and the second polysilicon film (52 in FIG. 6B) are used as an etching mask to form contact holes for storage contacts. By doing so, the misaligned margin between the storage contact and the lower film quality is increased by the thickness of the spacer 60 to prevent the risk of contact between the storage contact and the bit line or the storage contact and the gate electrode.

10A and 10B are cross-sectional views taken along the lines A-A 'and B-B' of FIG. 3 to explain the semiconductor memory device according to the third embodiment of the present invention.

The misalignment problem between the storage contact and the lower conductive layer (bit line or gate electrode) mentioned in the second embodiment of the present invention is etched with respect to the first or second interlayer insulating films 40 and 44 as shown. When the interlayer insulating layers 40 and 44 are formed of an oxide film, for example, a spacer 65 that surrounds the gate electrode 38 or the bit line 42 using a nitride film may be used. Can be solved. That is, in the state where the gate electrode 38 or the bit line 42 is formed, a nitride film is deposited on the entire surface of the resultant and then etched back to form spacers 65 and 70 on the sidewalls of the gate electrode 38 or the bit line 42. Form. In this case, since the bit line 42 and the gate electrode 38 are covered with an insulating material, even if a misalignment occurs in the process of forming a contact hole for a storage contact, the bit line and the gate electrode are not exposed and thus self-aligned. In general, a contact hole for a storage contact is formed.

FIG. 11 is a cross-sectional view taken along the line BB ′ of FIG. 3 to explain the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

Referring to FIG. 11, a transistor including a gate electrode 38 is formed on a semiconductor substrate 32, a spacer 65 is formed on sidewalls of the gate electrode, and then a conductive film, for example, is formed on the entire surface of the resultant substrate. Polysilicon doped with impurities is deposited and then the polysilicon film is patterned to form a pad 80 connected to the source / drain (not shown) of the transistor, as shown. The pad 80 is for intermediate connection between the source / drain of the transistor and the storage electrode. If the pad is formed in this way, then a storage contact is formed on the pad to prevent misalignment. The problem when forming a contact hole with a large aspect ratio can be prevented.

Although the embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and it is apparent that many modifications and improvements can be made by those skilled in the art within the technical idea to which the present invention pertains. .

According to the above-described semiconductor memory device and a method of manufacturing the same, a storage electrode pattern is first formed and then a photolithography process is performed to form a storage contact, and in particular, the storage contact is parallel to a word line. By forming in the shape, it is possible to fundamentally solve the misalignment between the storage electrode and the storage contact and the various problems caused by it.

1 is a plan view showing the layout of a typical stacked DRAM cell.

2A through 2C are cross-sectional views illustrating a cross section taken along the line AA ′ of FIG. 1 according to a process sequence.

3 is a layout diagram of a semiconductor memory device according to the present invention.

4A to 8B are cross-sectional views illustrating cross-sections in the A-A 'direction and the B-B' direction of FIG. 3 according to a process order to explain a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.

9 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device in accordance with a second embodiment of the present invention.

10A and 10B are cross-sectional views illustrating cross-sectional views taken along the lines A-A 'and B-B' of FIG. 3 to explain the semiconductor memory device according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line BB ′ of FIG. 3 to explain the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

32. Semiconductor board 34. Separator

36 .... gate insulating film 38 .... gate electrode

40, 44, 48 Insulation 42.Bitline

46, 50 .... etch stop 52, 54, 56, 60 ... conductor

65, 70 ... Spacer 80 ... Pad

Claims (22)

A plurality of word lines crossing the active region of the semiconductor substrate and arranged to be parallel to each other; A plurality of bit lines arranged to be orthogonal to the word lines and separated from the word lines by an insulating film; A first contact connecting the active region and the bit line between the word lines; A storage electrode formed on each of the active regions on both sides of the first contact, insulated from the bit line, and having a hole penetrating perpendicularly to the semiconductor substrate; And A second contact formed perpendicular to the semiconductor substrate, one end of which is connected to the active region and the other end of which fills the hole of the storage electrode, and has a second contact connecting the active region and the storage electrode; A semiconductor memory device, characterized in that. The semiconductor memory device of claim 1, further comprising an insulating layer spacer formed to surround the word line to insulate the storage contact from the word line. The semiconductor memory device of claim 1, further comprising an insulating layer spacer formed to surround the bit line to insulate the storage contact from the bit line. The semiconductor device of claim 1, between the storage contact and an active region of the semiconductor substrate. And a conductive pad connecting the active region of the semiconductor substrate to the storage contact. Sequentially forming a first etch stop layer, an insulating layer, and a second etch stop layer on the semiconductor substrate; Etching the insulating layer and the second etch stop layer in the region where the storage electrode is to be formed; Filling a region in which the insulating layer and the second etch stop layer are removed with a first conductive layer; Exposing an active region of a semiconductor substrate by removing the first conductive layer and the first etch stop layer of the region where the storage contact is to be formed; Forming a storage electrode formed of the first and second conductive layers by depositing and planarizing a second conductive layer on the entire surface of the resultant portion in which the active region is exposed; And And forming a dielectric film and a plate electrode on the resultant product on which the storage electrode is formed. The method of claim 5, wherein the first etch stop layer is formed of a material having an etch selectivity with respect to the insulating layer and the second etch stop layer for a predetermined etching process. The method of claim 6, wherein the first etch stop layer is formed of a polysilicon film, the insulating layer is formed of an oxide film, and the second etch stop layer is formed of a nitride film. The method of claim 5, wherein the filling of the region from which the insulating layer and the second etch stop layer are removed with the first conductive layer comprises: Depositing a first conductive layer on a resultant from which the insulating layer and the second etch stop layer are removed; And etching back the first conductive layer. The method of claim 5, wherein the filling of the region from which the insulating layer and the second etch stop layer are removed with the first conductive layer comprises: Depositing a first conductive layer on a resultant from which the insulating layer and the second etch stop layer are removed; And chemically polymerizing (CMP) the first conductive layer. The method of claim 5, wherein after etching the insulating layer and the second etch stop layer in the region where the storage electrode is to be formed: And forming a spacer on sidewalls of the insulating layer and the second etch stop layer. (a) forming a transistor including a gate electrode and a source / drain on a semiconductor substrate; (b) forming a first insulating layer on the resultant; (c) forming a bit line on the first insulating layer, the bit line being orthogonal to the gate electrode and connected to the drain; (d) forming a second insulating layer on the resultant bit line; (e) sequentially forming a first etch stop layer, a third insulating layer, and a second etch stop layer on the second insulating layer; (f) etching the third insulating layer and the second etch stop layer in the region where the storage electrode is to be formed; (g) filling the region from which the third insulating layer and the second etch stop layer is removed with the first conductive layer; (h) etching the first conductive layer, the first etch stop layer, the second insulating layer, and the first insulating layer in the region where the storage contact is to be formed to expose the source of the transistor; (i) depositing and planarizing a second conductive layer over the entire surface of the resultant product; (j) forming a storage electrode comprising first and second conductive layers by etching the second etch stop layer, the third insulating layer and the first etch stop layer; And (k) forming a dielectric film and a plate electrode on the resultant. The method of claim 11, wherein the first etch stop layer is formed of a material having an etch selectivity with respect to the third insulating layer and the second etch stop layer for a predetermined etching process. . The method of claim 12, wherein the first to third insulating layer is formed of an oxide film, The first etch stop layer is formed of a polysilicon film, And the second etch stop layer is formed of a nitride film, respectively. The method of claim 11, wherein step (g) is Depositing a first conductive layer on a resultant from which the insulating layer and the second etch stop layer are removed; And etching back the first conductive layer. The method of claim 11, wherein step (g) is Depositing a first conductive layer on a resultant from which the insulating layer and the second etch stop layer are removed; And chemically polymerizing (CMP) the first conductive layer. The method of claim 11, wherein (h) comprises: After sequentially etching the first conductive layer and the first etch stop layer of the region where the storage contact is to be formed, spacers are formed on sidewalls of the patterned first conductive layer, the third insulating layer, and the first and second etch stop layer. Forming step, And etching the second and first insulating layers by using the second etch stop layer, the first conductive layer, and the spacer as a mask. The method of claim 16, wherein the spacer, And forming the same material as the first and second conductive layers. The method of claim 16, wherein the spacer, A method of manufacturing a semiconductor memory device, characterized in that it is formed of a polysilicon film. The method of claim 11, wherein between (a) and (b), And depositing an insulating material on the semiconductor substrate on which the transistor is formed to etch back to form a spacer surrounding the gate electrode. The method of claim 11, wherein, between step (c) and step (d), And depositing an insulating material on the semiconductor substrate on which the bit line is formed, and then etching back to form a spacer surrounding the bit line. The method according to claim 19 or 20, wherein the spacer, And forming a material having an etch selectivity with respect to the first and second etch stop layers for a predetermined etching process for etching the first and second insulating layers. 20. The method of claim 19, wherein after forming the spacer: And forming a pad made of a third conductive layer for connecting the source / drain and the storage contact on the semiconductor substrate on which the spacer is formed.