KR20020051154A - Method for forming self-aligned contact plug of semiconductor device - Google Patents

Abstract

PURPOSE: A formation method of a self-alignment contact plug of semiconductor devices is provided to solve an etching stopped problem according to an increase of a polymer production by forming contact plugs self-aligned through gate electrodes regardless of considering an etching selectivity between an interlayer dielectric and a nitride spacer. CONSTITUTION: A number of gate electrodes(20) are formed on a semiconductor substrate(10). At this time, the upper surfaces and both sidewalls of the gate electrodes(20) are respectively enclosed with insulating layers made of nitride capping layers(32) and nitride spacers(34). Conductive pattern(50) self-aligned by the gate electrodes(20) are formed on the regions between the gate electrodes(20).

Description

Method for forming self-aligned contact plug of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of forming a contact plug self-aligned by a gate electrode.

As the semiconductor device is highly integrated, the distance between the contact hole connecting the lower wiring layer and the upper wiring layer and the peripheral wiring thereof decreases, and the aspect ratio of the contact hole increases. Therefore, accurate and stringent process conditions are required in forming a contact hole using a lithography process in a highly integrated semiconductor device employing a multi-layered wiring structure, and in particular, a device having a design rule of 0.25 μm or less is manufactured. Current lithography techniques have limitations in reproducing the desired process reproducibly.

Accordingly, in order to overcome the limitations of the lithography process when forming contact holes, a technique for forming contact holes by a self-aligning method has been developed. As one of such self-aligned contact hole forming methods, there is a method of using a nitride film spacer as an etching barrier layer.

In a conventional method for forming a self-aligned contact hole using a nitride film spacer as an etching barrier layer, first, a conductive layer such as a gate electrode is formed on a semiconductor substrate by a patterning method using a conventional photolithography process, and then the resultant After forming a nitride film on the entire surface, it is etched back to form a nitride film spacer on the sidewall of the conductive layer, and then an interlayer insulating film made of an oxide film is sequentially formed. Thereafter, a photoresist pattern is formed to expose the interlayer insulating film over the predetermined portion to the contact hole region, the exposed interlayer insulating film is etched to form a self-aligning contact hole, and then a conductive material is filled in the self-aligning contact hole. Form a contact plug.

In the method of forming a self-aligned contact plug according to the related art as described above, a contact hole is formed by etching the interlayer insulating layer under a condition where the etching selectivity difference between the interlayer insulating layer and the nitride spacer is large. To increase, carbon rich carbon fluoride gases, for example C ₄ F ₈ , C ₅ F _8, etc., which generate a large amount of polymer, are used.

Therefore, when the etching process is performed under the condition of increasing the etching selectivity, the amount of polymer production increases, which causes the problem that the etching is stopped before the contact hole is formed.

On the other hand, if the difference in etching selectivity between the interlayer insulating film and the nitride film spacer is small, the problem of stopping the etching before forming the contact hole does not occur, but the nitride film spacer may be consumed when the interlayer insulating film is etched. Therefore, it is difficult to secure the required insulation length on the sidewall of the conductive layer with the nitride film spacer remaining after the etching. As a result, a short circuit is likely to occur between the self-aligned contact formed in the contact hole and the conductive layer.

In particular, in the manufacturing process of a highly integrated semiconductor device having a design rule of 0.25 μm or less, in the case of forming a self-aligned contact hole on a gate electrode covered with an etching barrier layer such as a nitride film, between the conductive layer and the self-aligned contact formed thereon There is a lack of margin of insulation thickness to be secured. Therefore, when the etching process is performed under the condition that the etching selectivity difference between the interlayer insulating film and the etching barrier layer is small during the etching process for forming the self-aligned contact hole, the etching barrier layer is consumed or damaged, and thus the minimum insulation length is formed at the edge portion of the conductive layer. It is difficult to secure the edge portion, and the edge portion of the conductive layer is easily exposed to the inside of the contact hole.

Therefore, the process margin of the optimum process conditions when forming a self-aligned contact hole for manufacturing a highly integrated semiconductor device is not only low, the reproducibility of the device is reduced, but also the reliability of the device operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to eliminate the need to consider the etching selectivity between the interlayer insulating film and the nitride film spacer in a self-aligned contact plug forming process for fabricating highly integrated semiconductor devices. The present invention provides a method for forming a self-aligned contact plug of a semiconductor device capable of increasing a process margin so as to secure a required insulation length between a self-aligned contact plug and a self-aligned contact plug.

1 is a layout diagram illustrating some components of a semiconductor device that may be implemented in accordance with an embodiment of the present invention.

2A, 2B and 2C are cross sectional views taken along lines 2A-2A, 2B-2B and 2C-2C, respectively, and FIG. 2D is a cross sectional view of the device having the cross-sectional structure of FIGS. 2A, 2B and 2C. Partial perspective view.

3A, 3B, and 3C to 8A, 8B, and 8C are cross-sectional views illustrating a method of forming a self-aligned contact plug in a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

Reference Signs List 10 semiconductor substrate, 12 gate insulating film, 20 gate electrode, 32 capping layer, 34 spacer, 42 diffusion barrier film, 42a, 42b diffusion barrier film pattern, 44 third conductive layer, 44a third conductive layer Pattern 46: planarized fourth insulating layer, 46a: planarized fourth insulating layer pattern, 48: fifth insulating layer, 48a: planarized fifth insulating layer, 50: contact plug.

In order to achieve the above object, in the method for forming a self-aligned contact plug of a semiconductor device according to the present invention, a plurality of gate electrodes on which a top surface and sidewalls are covered with an insulating layer are formed on a semiconductor substrate. A conductive layer pattern self-aligned by the gate electrode is formed in an area between the gate electrodes. A flattened insulating layer is formed on the entire surface of the resultant product on which the conductive layer pattern is formed. The planarized insulating layer is patterned to form a planarized insulating layer pattern partially exposing the top surface of the conductive layer pattern. By removing the exposed portion of the conductive layer pattern by etching using the planarized insulating layer pattern as an etching mask, a contact plug including the remaining portion of the conductive layer pattern is formed.

Preferably, the conductive layer pattern is formed such that the height of the upper surface is lower than the height of the upper surface of the insulating layer covering the upper surface of the gate electrode.

Also preferably, the forming of the planarized insulating layer may include forming a lower insulating layer on the entire surface of the resultant layer on which the conductive layer pattern is formed, planarizing the lower insulating layer, and forming the lower insulating layer on the planarized lower insulating layer. Forming an upper insulating layer, and in forming the flattened insulating layer pattern, the upper insulating layer and the flattened lower insulating layer are patterned together.

According to the present invention, it is possible to form a contact plug that is self-aligned by the gate electrode without having to consider the etching selectivity between the interlayer insulating film and the nitride film spacer in the self-aligned contact plug forming process for manufacturing a highly integrated semiconductor device.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout diagram illustrating some components of a semiconductor device that may be implemented according to an exemplary embodiment of the present invention, and illustrates a case in which the present invention is applied to a flash memory cell.

In FIG. 1, a plurality of word lines W / L, each of which forms a gate electrode, extend in a predetermined direction, and between each word line W / L, between each word line W / L. A plurality of contacts CP are formed in a state where a predetermined insulation length is secured.

2A, 2B and 2C are cross sectional views taken along lines 2A-2A, 2B-2B and 2C-2C, respectively, and FIG. 2D is a cross sectional view of the device having the cross-sectional structure of FIGS. 2A, 2B and 2C. Partial perspective view.

2A to 2D, a gate electrode 20 formed by the word line W / L is formed on the gate insulating layer 12 on the semiconductor substrate 10. The gate electrode 20 has a structure in which the first conductive layer 22, the dielectric film 24, and the second conductive layers 26 and 28 are sequentially stacked. The first conductive layer 22 may be formed of, for example, a doped polysilicon layer or an amorphous silicon layer having a thickness of about 750 to 3500 GPa. For example, the dielectric film 24 may have a multilayer structure in which an oxide film having a thickness of about 30 to 100 GPa, a nitride film having a thickness of about 50 to 120 GPa, and an oxide film having a thickness of 0 to 100 GPa are sequentially stacked. The second conductive layers 26 and 28 have a structure in which second conductive layers 26 and 28 sequentially formed of, for example, a stacked structure of a doped polysilicon layer 26 and a metal silicide layer 28 are stacked. have.

An upper surface of the gate electrode 20 is covered with a capping layer 32 made of a nitride film, and sidewalls of the gate electrode 20 are covered with a spacer 34 made of a nitride film.

Contact plugs 50 constituting the contact CP are formed to be self-aligned by the gate electrode 20 in a predetermined region between the adjacent gate electrodes 20. A diffusion barrier 42 is interposed between the contact plug 50 and the semiconductor substrate 10 and between the contact plug 50 and the spacer 34.

3A, 3B, and 3C to 8A, 8B, and 8C are cross-sectional views illustrating a method of forming a self-aligned contact plug in a semiconductor device according to a preferred embodiment of the present invention. In these drawings, FIGS. 3A, 4A, ..., and 8A are views corresponding to the cross-sections of lines 2A-2A of FIG. 1, respectively, and FIGS. 3B, 4B, ..., and 8B are respectively shown in FIG. FIG. 3C, FIG. 4C,..., And FIG. 8C are views corresponding to the cross-section 2C-2C in FIG. 1.

First, referring to FIGS. 3A, 3B, and 3C, after a first insulating layer is grown on a semiconductor substrate 10, a doped polysilicon layer or an amorphous silicon layer having a thickness of about 750 to 3500 μs thereon, A polyside layer composed of a multilayer structure of an insulating film, a doped polysilicon layer and a metal silicide layer, in which an oxide film having a thickness of about 30 to 100 GPa, a nitride film having a thickness of about 50 to 120 GPa, and an oxide film having a thickness of 0 to 100 GPa are sequentially stacked; And a second insulating layer are sequentially stacked. Thereafter, the second insulating layer is patterned to form a capping layer 32 by a photolithography process, and then a lower layer of the stacked layers is patterned by a dry etching process using the capping layer 32 as an etching mask. A gate electrode 20 in which an oxide film, a first conductive layer 22, a dielectric film 24, and second conductive layers 26 and 28 are sequentially stacked is formed.

Thereafter, a third insulating layer, for example, a nitride film is deposited on the entire surface of the resultant product on which the gate electrode 20 and the capping layer 32 are formed, and then etched back to protect the vertical sidewall of the gate electrode 20. Spacers 34 are formed on sidewalls of the gate electrode 20 and the capping layer 32. At this time, in the regions other than the region where the capping layer 32 and the spacer 34 are formed, the nitride layer and the first insulating layer, which are the third insulating layer, are completely removed, and the sidewalls of the spacer 34 are covered with the sidewalls. The natural oxide film is not left on the surface 10a of the semiconductor substrate 10 exposed in the region between the gate electrodes 20.

4A, 4B and 4C, in order to reduce the resistance between the active region of the semiconductor substrate 10 and the third conductive layer 44 to be formed in a subsequent process and to prevent atomic diffusion therebetween. A diffusion barrier 42 is formed on the entire surface of the product on which the spacers 34 are formed, and a third conductive layer 44 is formed on the diffusion barrier 42.

Although not shown, before forming the diffusion barrier 42 and the third conductive layer 44, a metal silicide layer may be formed on the exposed surface 10a of the semiconductor substrate 10 through a self-alignment reaction. have.

Referring to FIGS. 5A, 5B, and 5C, the third conductive layer 44 and the diffusion barrier 42 may be etched entirely to self-align the third conductive layer pattern 44a by the gate electrode 20. And diffusion barrier film pattern 42a. At this time, the etching amount is adjusted such that the third conductive layer pattern 44a and the diffusion barrier layer pattern 42a have upper surfaces 44t and 42t having a lower height than the upper surface 32t of the capping layer 32, respectively. . In order to prevent damage to the gate electrode 20 due to excessive etching during the front surface etching process, sufficient etching selectivity between the capping layer 32, the spacer 34, and the third conductive layer 44 formed of a nitride film may be provided. Maintain the atmosphere given.

In the etching process, the upper surface 44t of the third conductive layer pattern 44a and the upper surface 42t of the diffusion barrier layer pattern 42a have a height lower than that of the upper surface 32t of the capping layer 32. The third conductive layer pattern 44a and the diffusion barrier layer pattern 42a may be completely isolated from the gate electrode 20, thereby preventing unwanted short circuits between the third conductive layer patterns 44a. can do.

6A, 6B, and 6C, a mask layer is formed on the resultant to pattern the third conductive layer pattern 44a and the diffusion barrier layer pattern 42a into a form suitable for a desired device structure. To this end, first, a fourth insulating layer is deposited on the entire surface of the resultant product on which the third conductive layer pattern 44a is formed, and then a planarization process is performed to form a flattened fourth insulating layer 46. Damage in the planarized fourth insulating layer 46 generated during the planarization process may cause a short circuit between the wirings in a subsequent wiring forming process, thereby causing deterioration of device characteristics. In order to prevent this, the planarized fourth insulating layer 46 is covered with a fifth insulating layer 48.

7A, 7B, and 7C, the fifth insulating layer 48 and the planarized fourth insulating layer 46 are patterned together using a conventional photolithography process to form the third conductive layer pattern. The planarized fourth insulating layer pattern 46a and the fifth insulating layer pattern 48a exposing the top surfaces 44t and 42t of the region to be removed, respectively, of the 44a and the diffusion barrier layer pattern 42a are formed. The planarized fourth insulating layer pattern 46a and the fifth insulating layer pattern 48a serve as an etch mask layer in patterning the third conductive layer pattern 44a and the diffusion barrier layer pattern 42a.

8A, 8B, and 8C, the third conductive layer pattern exposed using the mask layer including the planarized fourth insulating layer pattern 46a and the fifth insulating layer pattern 48a as an etching mask ( 44a) and the diffusion barrier layer pattern 42a are removed by etching so that the contact plug 50 and the diffusion barrier layer pattern 42b remain in a desired portion, and the semiconductor is not formed at the portion where the contact plug 50 does not need to be formed. The surface 10b of the substrate 10 is exposed.

When the etching process is performed to remove the exposed third conductive layer pattern 44a and the diffusion barrier layer pattern 42a, the materials forming the fourth insulating layer pattern 46a and the fifth insulating layer pattern 48a are formed. And the etching process is performed under a condition that a sufficient etching selectivity is provided between the third conductive layer pattern 44a and the material constituting the diffusion barrier film pattern 42a.

This completes the structure as described with reference to Figs. 2A to 2D.

According to the method for forming a self-aligned contact plug of a semiconductor device according to the present invention, in the self-aligned contact plug forming process for fabricating a highly integrated semiconductor device, the self-aligned contact gate is self-aligned by a gate electrode without having to consider the etching selectivity between the interlayer insulating film and the nitride spacer. It is possible to form contact plugs. Therefore, as in the prior art, there is no fear that the etching may be stopped due to the increase in the amount of polymer production, or the spacer may be consumed when the interlayer insulating layer is etched, thereby making it difficult to secure the required insulation length at the sidewall of the gate electrode.

The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

Claims (3)

Forming a plurality of gate electrodes on the semiconductor substrate, the top and sidewalls of which are covered with an insulating layer; Forming a conductive layer pattern self-aligned by the gate electrode in a region between the gate electrodes; Forming a planarization insulating layer on the entire surface of the resultant product on which the conductive layer pattern is formed; Patterning the planarized insulating layer to form a planarized insulating layer pattern partially exposing the top surface of the conductive layer pattern; Forming a contact plug formed of the remaining portion of the conductive layer pattern by removing the exposed portion of the conductive layer pattern by etching using the planarized insulating layer pattern as an etching mask. To form a self-aligned contact plug. The method of claim 1, wherein the upper surface of the conductive layer pattern is formed to be lower than the height of the upper surface of the insulating layer covering the upper surface of the gate electrode. The method of claim 1, wherein the forming of the planarized insulating layer is performed. Forming a lower insulating layer on the entire surface of the resultant product on which the conductive layer pattern is formed; Planarizing the lower insulating layer; Forming an upper insulating layer on the planarized lower insulating layer, The forming of the planarized insulating layer pattern may include patterning the upper insulating layer and the flattened lower insulating layer together.