KR100353830B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR100353830B1 KR100353830B1 KR1020000074145A KR20000074145A KR100353830B1 KR 100353830 B1 KR100353830 B1 KR 100353830B1 KR 1020000074145 A KR1020000074145 A KR 1020000074145A KR 20000074145 A KR20000074145 A KR 20000074145A KR 100353830 B1 KR100353830 B1 KR 100353830B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- usg
- bpsg
- forming
- bpsg film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
본 발명은 셀영역의 층간절연막을 손상시키지 않으면서 주변회로영역의 층간절연막을 효과적으로 제거하기 위한 반도체소자의 제조 방법에 관한 것으로, 셀영역과 주변회로영역이 정의된 반도체기판상에 다수의 도전층패턴을 형성하는 단계, 상기 도전층패턴상에 BPSG막을 형성하는 단계, 상기 BPSG막상에 USG막을 형성하는 단계, 상기 USG막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 상기 반도체기판의 주변회로영역을 노출시키는 마스크를 형성하는 단계, 및 상기 마스크를 이용하여 상기 USG막과 상기 BPSG막을 제거하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device for effectively removing an interlayer insulating film in a peripheral circuit region without damaging the interlayer insulating film in a cell region. Forming a pattern, forming a BPSG film on the conductive layer pattern, forming a USG film on the BPSG film, applying a photosensitive film on the USG film, and patterning the exposure circuit and the peripheral circuit region of the semiconductor substrate. Forming a mask to expose and removing the USG film and the BPSG film using the mask.
본 발명은 후속 노광공정에서 감광막과의 고착력을 BSPG막보다 개선하기 위하여 BPSG막 표면에 USG막을 형성하여 보론이나 인에 의하여 흡착되는 수분을 제거할 수 있다.The present invention can remove the water adsorbed by boron or phosphorus by forming a USG film on the surface of the BPSG film in order to improve the adhesion to the photosensitive film than the BSPG film in a subsequent exposure process.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 셀영역의 층간절연막을 손상시키지 않으면서 주변회로영역의 층간절연막을 효과적으로 제거하도록 한 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the interlayer insulating film in the peripheral circuit region is effectively removed without damaging the interlayer insulating film in the cell region.
최근에 반도체 소자의 고집적화에 따라 고단차의 좁은 간격의 패턴사이를 내부 공공없이 절연막으로 채우고, 상기 절연막의 매립에 따른 단차를 줄이는 평탄화기술은 반도체소자의 제조에 있어 중요한 기술 중 하나로 대두되고 있다.In recent years, as a result of high integration of semiconductor devices, planarization techniques, which fill gaps between patterns with high gaps with no gaps without internal voids and reduce the level difference caused by the filling of the insulating films, have emerged as one of the important technologies in the manufacture of semiconductor devices.
일반적으로 고단차의 좁은 패턴사이를 매립하기 위하여 BPSG(Boro Phosphorous Silicate Glass), 고밀도플라즈마 화학기상증착법(High Density Plasma Chemical Vapor Deposition; HDP CVD)을 이용한 산화막, SOG(Spin On Glass)를 사용한다.Generally, BPSG (Boro Phosphorous Silicate Glass), an oxide film using High Density Plasma Chemical Vapor Deposition (HDP CVD), and SOG (Spin On Glass) are used to fill the gaps between narrow patterns of high steps.
상기 BPSG막을 사용하는 경우, 막 안정성, 갭필 한계성 및 고온열처리에 의한 한계성이 있으며, 그리고 고밀도 플라즈마 화학기상증착법(HDP CVD)을 이용하여 좁은 패턴사이를 매립하고 화학적기계적연마공정(Chemical Mechanical Polishing; 이하 'CMP'라 약칭함)으로 연마하여 평탄화시키는 방법이 있으나, 이 역시 패턴매립특성의 한계성, 플라즈마 손실, 패턴모서리가 깍이는 문제점으로 패턴매립의 적용에는 한계점이 있다.In the case of using the BPSG film, there is a film stability, gap fill limitation, and limitations due to high temperature heat treatment, and a high density plasma chemical vapor deposition (HDP CVD) is used to fill in narrow patterns and chemical mechanical polishing (hereinafter referred to as chemical mechanical polishing). (CMP) abbreviated), but there is a method of polishing and flattening, but this also has limitations in the application of pattern embedding due to the limitations of pattern embedding characteristics, plasma loss, and pattern shaving.
상기 SOG를 이용하는 경우, 미세패턴 매립 특성이 우수하나 고온공정에서 크랙(Crack)이 발생되고, 작은 패턴크기에서는 평탄도와 절연막이 이루는 각도가 우수하나 현재 사용되고 있는 셀블록(Cell block)과 같은 넓은 패턴에서는 전체 단차를 낮추지 못하는 단점이 있다.When the SOG is used, the fine pattern embedding characteristics are excellent, but cracks are generated in a high temperature process, and in the small pattern size, the flatness and the angle formed by the insulating film are excellent, but a wide pattern such as a cell block currently used. Has the disadvantage of not lowering the overall step.
도 1은 종래기술에 따른 반도체소자의 제조 방법을 간략히 도시한 도면이다.1 is a view briefly showing a method of manufacturing a semiconductor device according to the prior art.
도 1에 도시된 바와 같이, 셀영역(A)과 주변회로영역(B)이 정의된 반도체기판(11)에 트랜지스터 제조 공정에 의해 다수의 스페이서를 구비한 워드라인(12), 소스/드레인인 불순물접합층(13)을 형성한다. 계속해서, 반도체기판(11)의 전면에 층간절연막으로서 BPSG막(14)을 형성 및 열처리한 후, 선택적으로 패터닝하여 플러그영역을 노출시킨다.As shown in FIG. 1, a word line 12 having a plurality of spacers and a source / drain in the semiconductor substrate 11 in which a cell region A and a peripheral circuit region B are defined by a transistor manufacturing process. The impurity junction layer 13 is formed. Subsequently, after forming and heat-treating the BPSG film 14 as an interlayer insulating film on the entire surface of the semiconductor substrate 11, it is selectively patterned to expose the plug region.
노출된 플러그영역, 즉 셀영역(A)의 워드라인(12) 사이의 불순물접합층(13)상에 에피택셜성장법을 이용하여 플러그로서 에피택셜실리콘층(15)을 형성한 후, 에피택셜실리콘층(15)을 화학적기계적연마(Chemical Mechanical Polishing; CMP)하여 서로 분리시킨 후, 반도체기판(11)의 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 셀영역(A)은 보호하고 주변회로영역(B)은 오픈시키는 마스크(16)를 형성한다. 마스크(16)를 이용하여 노출된 주변회로영역(B)의 BPSG막(14)을 습식식각하여 제거한다.After the epitaxial silicon layer 15 is formed as a plug on the exposed plug region, that is, the impurity bonding layer 13 between the word lines 12 of the cell region A by the epitaxial growth method, the epitaxial layer After the silicon layer 15 is separated from each other by chemical mechanical polishing (CMP), a photosensitive film is coated on the entire surface of the semiconductor substrate 11 and patterned by exposure and development to protect the cell region A and to surround the peripheral circuit. Region B forms a mask 16 that opens. The BPSG film 14 of the exposed peripheral circuit region B is wet-etched and removed using the mask 16.
여기서, 일반적으로 층간절연막으로 이용된 BPSG막(14)의 불순물(B, P)은 열처리후 대기 노출시 수분(H2O) 흡습성이 매우 크다고 알려져 있으며, 또한 화학적기계적연마 공정후 BPSG막이 슬러리에 의해 침윤당하게 되며 이 때 열처리 직후의 BPSG막보다 훨씬 많은 양의 수분이 BPSG막의 보론과 인에 의해 표면에 흡착되게 된다(도 2 참조). 이러한 수분층은 감광막과 BSPG막 사이에 미세한 틈을 형성하고,표면에 수분이 충분히 흡착된 상태에서 습식식각을 진행하게 되면 수직방향으로 습식용액이 BSPG막을 식각하는 속도보다 감광막과 BPSG막 사이로 습식용액이 침투하여 수평 방향으로 BPSG막을 식각하는 속도가 매우 커지게 된다(도 3 참조).Here, impurities (B, P) of the BPSG film 14, which is generally used as an interlayer insulating film, are known to have high moisture (H 2 O) hygroscopicity when exposed to air after heat treatment, and the BPSG film is deposited on the slurry after the chemical mechanical polishing process. In this case, much more water is adsorbed to the surface by the boron and phosphorus of the BPSG film immediately after the heat treatment (see FIG. 2). The water layer forms a fine gap between the photoresist film and the BSPG film, and when the wet etching is performed while the water is sufficiently adsorbed on the surface, the wet solution flows between the photoresist film and the BPSG film rather than the rate at which the wet solution etches the BSPG film in the vertical direction. The rate of penetration and etching of the BPSG film in the horizontal direction becomes very large (see FIG. 3).
이러한 경우, 주변회로영역의 BPSG막은 완전 습식식각되어지기 전에 워드라인과 주변회로영역에 설정된 감광막 하부로 습식용액이 침윤하여 셀영역내의 BPSG막까지 식각되는 문제점이 있다.In this case, the BPSG film in the peripheral circuit area is wetted to the bottom of the photoresist film set in the word line and the peripheral circuit area before being completely wet etched, so that the BPSG film is etched to the BPSG film in the cell area.
이를 해결하기 위해 노광공정후 잔류하는 감광막의 영역을 넓게 하는 방법에 제안되었으나, 이 방법은 BSPG막이 잔류하는 영역 또한 증가하게 되어 후속 접합 공정시 불량을 유발하는 문제점이 있다.In order to solve this problem, a method of widening the area of the photoresist film remaining after the exposure process has been proposed, but this method also increases the area in which the BSPG film remains, causing a problem in the subsequent bonding process.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 감광막과 BPSG막의 고착력 저하로 인해 주변회로영역상의 BPSG막을 제거하기 위한 습식식각시 셀영역의 BPSG막이 제거되는 것을 방지하는데 적합한 반도체소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, a semiconductor device suitable for preventing the removal of the BPSG film in the cell region during the wet etching to remove the BPSG film on the peripheral circuit region due to the decrease in adhesion of the photosensitive film and the BPSG film Its purpose is to provide a process for the preparation.
도 1은 종래기술에 따른 반도체 소자의 제조 방법을 개략적으로 도시한 도면,1 is a view schematically showing a method for manufacturing a semiconductor device according to the prior art;
도 2는 도 1의 BPSG막내의 보론(B)과 인(P)이 수분(H2O)에 흡착된 상태를 나타낸 도면,2 is a view showing a state in which boron (B) and phosphorus (P) in the BPSG film of FIG. 1 adsorbed to water (H 2 O),
도 3은 도 1의 BPSG막이 습식용액에 의해 침윤되는 현상을 나타낸 도면,3 is a view showing a phenomenon in which the BPSG film of FIG. 1 is infiltrated by a wet solution;
도 4a 내지 도 4b는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면.4A to 4B illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 워드라인21: semiconductor substrate 22: word line
23 : 불순물접합층 24 : BPSG막23 impurity bonding layer 24 BPSG film
25 : 에피택셜실리콘층 26 : USG막25: epitaxial silicon layer 26: USG film
27 : 마스크27: mask
상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 셀영역과 주변회로영역이 정의된 반도체기판상에 다수의 도전층패턴을 형성하는 단계, 상기 도전층패턴상에 BPSG막을 형성하는 단계, 상기 BPSG막상에 USG막을 형성하는 단계,상기 USG막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 상기 반도체기판의 주변회로영역을 노출시키는 마스크를 형성하는 단계, 및 상기 마스크를 이용하여 상기 USG막과 상기 BPSG막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of conductive layer patterns on a semiconductor substrate defined cell region and peripheral circuit region, forming a BPSG film on the conductive layer pattern, Forming a USG film on the BPSG film, applying a photoresist film on the USG film, and patterning the photoresist film by exposure and development to form a mask that exposes a peripheral circuit region of the semiconductor substrate, and the USG film using the mask. And removing the BPSG film.
바람직하게, 상기 USG막은 후속 노광 공정에서 감광막과의 고착력을 증가시키기 위하여 200Å∼500Å의 두께로 형성되며, 저압화학기상증착법 또는 플라즈마화학기상증착법 중 어느 한 방법으로 형성되는 것을 특징으로 한다.Preferably, the USG film is formed in a thickness of 200 kPa to 500 kPa in order to increase the adhesion with the photosensitive film in a subsequent exposure process, characterized in that formed by any one of low pressure chemical vapor deposition or plasma chemical vapor deposition.
바람직하게, 상기 USG막과 상기 BPSG막을 제거하는 단계에서 상기 USG막과 상기 BPSG막은 BOE 또는 HF 중 어느 한 습식용액을 이용하여 제거되거나, 상기 USG막은 건식식각으로 제거되고 상기 BPSG막은 습식식각으로 제거되는 것을 특징으로 한다.Preferably, in the step of removing the USG film and the BPSG film, the USG film and the BPSG film is removed using a wet solution of either BOE or HF, or the USG film is removed by dry etching and the BPSG film is removed by wet etching. It is characterized by.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 4a 내지 도 4b는 본 발명의 실시예에 따른 반도체소자의 층간절연막의 형성 방법을 도시한 도면이다.4A to 4B illustrate a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.
도 4a에 도시된 바와 같이, 셀영역(A)과 주변회로영역(B)이 정의된 반도체기판(21)에 트랜지스터 제조 공정에 의해 다수의 스페이서를 구비한 워드라인(22), 소스/드레인인 불순물접합층(23)을 형성한다. 계속해서, 반도체기판(21)의 전면에 층간절연막으로서 BPSG막(24)을 형성한후 열처리하고, BPSG막(24)을 선택적으로 패터닝하여 플러그영역을 노출시킨다.As shown in FIG. 4A, a word line 22 having a plurality of spacers and a source / drain in the semiconductor substrate 21 in which a cell region A and a peripheral circuit region B are defined by a transistor manufacturing process. The impurity junction layer 23 is formed. Subsequently, the BPSG film 24 is formed on the entire surface of the semiconductor substrate 21 as an interlayer insulating film, and then subjected to heat treatment. The BPSG film 24 is selectively patterned to expose the plug region.
노출된 플러그영역, 즉 셀영역(A)의 워드라인(22) 사이의 불순물접합층(23)상에 에피택셜성장법을 이용하여 플러그로서 에피택셜실리콘층(25)을 형성한 후, 에피택셜실리콘층(25)을 화학적기계적연마(Chemical Mechanical Polishing; CMP)하여 서로 분리시킨다.After the epitaxial silicon layer 25 is formed as a plug on the exposed plug region, that is, the impurity bonding layer 23 between the word lines 22 of the cell region A by using the epitaxial growth method, the epitaxial layer The silicon layers 25 are separated from each other by chemical mechanical polishing (CMP).
계속해서, 에피택셜실리콘층(25)이 형성된 반도체기판(21) 상부에 USG막(26)을 증착한다. 이 때, USG막(26)은 셀영역(A) 및 주변회로영역(B)의 전영역에 걸쳐서 증착된다.Subsequently, a USG film 26 is deposited on the semiconductor substrate 21 on which the epitaxial silicon layer 25 is formed. At this time, the USG film 26 is deposited over the entire area of the cell region A and the peripheral circuit region B. As shown in FIG.
이와 같이, 에피택셜실리콘층(25)의 화학적기계적연마후 USG막(26)을 증착하면, BPSG막(24)의 수분을 제거시킴과 동시에 USG막(26)은 수분흡착의 원인이 되는 보론(B)이나 인(P)과 같은 불순물이 없으므로 감광막과의 고착력을 증대시킨다.As such, when the USG film 26 is deposited after the chemical mechanical polishing of the epitaxial silicon layer 25, the water of the BPSG film 24 is removed, and the USG film 26 is a boron (caused to cause moisture adsorption). Since there are no impurities such as B) or phosphorus (P), adhesion to the photosensitive film is increased.
BPSG막(24)의 수분을 제거하는 다른 방법으로 USG막(26)을 증착하지 않고 고온 열처리를 통해 BPSG막(24) 표면의 수분을 제거할 수 있으나, 보론이나 인이 수분을 계속 흡착하는 한계가 있다.As another method of removing water from the BPSG film 24, the surface of the BPSG film 24 may be removed by high temperature heat treatment without depositing the USG film 26. There is.
감광막과의 고착력을 증대시키는 USG막(26)은 200Å∼500Å의 두께로 증착되는 것이 바람직하다. 한편, 너무 두껍게 증착되는 경우, USG막의 습식식각 속도가 느리기 때문에 하부의 BPSG막(24)은 제거되지만 상부에 USG막이 처마 모양으로 남아 있을 수 있다.It is preferable that the USG film 26 which increases the adhesion with the photosensitive film is deposited to a thickness of 200 kPa to 500 kPa. On the other hand, if the deposition is too thick, because the wet etching rate of the USG film is slow, the lower BPSG film 24 is removed, but the USG film may remain in the eaves on the top.
그리고, USG막(26)은 증착온도가 400℃ 이상인 저압화학기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD) 또는 플라즈마화학기상증착법(PlasmaEnhanced CVD; PECVD) 중 어느 한 방법으로 증착된다.The USG film 26 is deposited by any one of Low Pressure Chemical Vapor Deposition (LPCVD) and PlasmaEnhanced CVD (PECVD) having a deposition temperature of 400 ° C. or higher.
도 4b에 도시된 바와 같이, USG막(26)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 셀영역(A)은 보호하고 주변회로영역(B)은 오픈시키는 마스크(26)를 형성한다. 마스크(27)를 이용하여 노출된 주변회로영역(B)의 USG막(26) 및 BPSG막(24)을 습식식각한다. 이 때, USG막(26)을 건식식각 또는 습식식각 중 어느 한 식각공정을 진행할 수 있다.As shown in FIG. 4B, a photosensitive film is coated on the USG film 26 and patterned by exposure and development to form a mask 26 that protects the cell region A and opens the peripheral circuit region B. FIG. The USG film 26 and the BPSG film 24 of the exposed peripheral circuit region B are wet-etched using the mask 27. At this time, the USG film 26 may be subjected to any one of dry etching and wet etching.
먼저 건식식각은, USG막(26)이 BPSG막(24)에 비해 습식식각 속도가 매우 느리기 때문으로 500Å∼1000Å의 두께로 USG막(26)이 증착된 경우에 공정 마진을 확보하기 위해 실시한다. 한편, 두껍게 증착된 USG막(26)을 습식식각하는 경우, 습식시간이 길어져서 셀영역내로 USG막(26)이 습식식각되어 들어가는 현상을 억제할 수 있다. 이러한 건식식각을 추가하므로써 습식식각시 수직방향으로의 식각속도를 증가시킬 수 있다.First, dry etching is performed in order to secure a process margin when the USG film 26 is deposited at a thickness of 500 kPa to 1000 kPa because the USG film 26 has a very slow wet etching rate compared to the BPSG film 24. . On the other hand, when wet etching the thickly deposited USG film 26, the wet time is long, it is possible to suppress the phenomenon that the wet etching of the USG film 26 into the cell region. By adding such dry etching, the etching speed in the vertical direction during wet etching can be increased.
상술한 USG막(26) 및 BPSG막(24)의 습식식각은 HF 또는 BOE(Buffer Oxide Etcahnat) 중 어느 한 습식용액을 이용한다.The wet etching of the USG film 26 and the BPSG film 24 described above uses a wet solution of either HF or BOE (Buffer Oxide Etcahnat).
상술한 본 발명의 실시예에서는 에피택셜실리콘층을 플러그로 이용하는 반도체소자의 제조 방법에 대해 설명하였지만, 본 발명은 BPSG막을 층간절연막으로 이용하는 모든 반도체소자의 제조 방법에 적용할 수 있다.In the above-described embodiment of the present invention, a method for manufacturing a semiconductor device using an epitaxial silicon layer as a plug has been described, but the present invention can be applied to a method for manufacturing all semiconductor devices using a BPSG film as an interlayer insulating film.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체소자의 제조 방법은 후속 노광공정에서 감광막과의 고착력을 BSPG막보다 개선하기 위하여 BPSG막 표면에 USG막을 형성하여 보론이나 인에 의하여 흡착되는 수분을 제거하므로써 반도체소자의 제조 공정을 안정화시킬 수 있는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention as described above, the USG film is formed on the surface of the BPSG film to remove the moisture adsorbed by boron or phosphorus in order to improve the adhesion to the photosensitive film than the BSPG film in the subsequent exposure process. There is an effect that can stabilize the manufacturing process of.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000074145A KR100353830B1 (en) | 2000-12-07 | 2000-12-07 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000074145A KR100353830B1 (en) | 2000-12-07 | 2000-12-07 | Method for fabricating semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020044894A KR20020044894A (en) | 2002-06-19 |
| KR100353830B1 true KR100353830B1 (en) | 2002-09-28 |
Family
ID=27680207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000074145A KR100353830B1 (en) | 2000-12-07 | 2000-12-07 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100353830B1 (en) |
-
2000
- 2000-12-07 KR KR1020000074145A patent/KR100353830B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020044894A (en) | 2002-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8426969B2 (en) | Semiconductor device having active region and dummy wirings | |
| KR20010036818A (en) | Method for forming a T-shaped trench isolation | |
| KR100353830B1 (en) | Method for fabricating semiconductor device | |
| KR20020085390A (en) | Trench isolation method | |
| KR101032115B1 (en) | Method for forming plug of semiconductor device | |
| KR100588647B1 (en) | Method For Manufacturing Semiconductor Devices | |
| KR100476371B1 (en) | Method of forming flattening insulating film between metal layers | |
| KR100422959B1 (en) | Method for forming isolation layer of semiconductor device | |
| KR20020043908A (en) | Method for forming isolation layer in semiconductor device | |
| KR20080084293A (en) | Method for manufacturing semiconductor device | |
| KR100477827B1 (en) | Fabricating method of reducing capacitance between gate electrode and plug in semiconductor device | |
| KR100492790B1 (en) | Device isolation insulating film formation method of semiconductor device | |
| KR20080029565A (en) | Method for forming contact plug in semiconductor device | |
| KR100630780B1 (en) | A method for fabricating semiconductor device using inorganic SOG | |
| KR100513798B1 (en) | Fabricating method of semiconductor device with good planarization of flow dielectrics | |
| KR100333378B1 (en) | Method of manufacturing semiconductor device | |
| KR0176201B1 (en) | Isolation method of semiconductor device and flating method therefor | |
| KR100235960B1 (en) | Method of forming conducting line in semiconductor device | |
| KR100437541B1 (en) | Method for forming isolation layer of semiconductor device using two-step gap filling processes | |
| KR20010058980A (en) | Method for manufacturing capacitor in semiconductor device | |
| KR101033981B1 (en) | Method for fabricating semiconductor device | |
| KR100480625B1 (en) | Method for forming trench isolation and semiconductor device comprising the same | |
| KR19990006018A (en) | Method of forming device isolation film of semiconductor device | |
| KR20030000489A (en) | Manufacturing method for semiconductor device | |
| KR100576462B1 (en) | Manufacturing method for contact hole of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |