KR101033981B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR101033981B1
KR101033981B1 KR1020040036412A KR20040036412A KR101033981B1 KR 101033981 B1 KR101033981 B1 KR 101033981B1 KR 1020040036412 A KR1020040036412 A KR 1020040036412A KR 20040036412 A KR20040036412 A KR 20040036412A KR 101033981 B1 KR101033981 B1 KR 101033981B1
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forming
semiconductor device
interlayer insulating
nitride film
insulating film
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KR20050111199A (en
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은병수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자의 형성 방법에 관한 것으로써, 반도체 소자에서 게이트 패턴을 형성한 후 ILD(Inter Layer Dielectric)로 이용되는 BPSG(Boron Phosphorus Silicate Glass) 층간절연막을 형성하는 단계에서 보이드(Void)가 발생되는 문제를 방지하기 위하여, BPSG 층간절연막과 같은 옥사이드(Oxide) 계열의 얇은 절연막을 게이트 패턴에 형성시킴으로써 층간절연막의 유동성과 갭 필(Gap Fill)능력을 향상시키는 반도체 소자의 형성 방법 이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device. In order to prevent a problem from occurring, a method of forming a semiconductor device improves the fluidity and gap fill capability of an interlayer insulating layer by forming an oxide-based thin insulating layer such as a BPSG interlayer insulating layer in a gate pattern.

Description

반도체 소자의 형성 방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Method of forming a semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1b는 종래 기술에 따른 반도체 소자의 형성 방법을 도시한 사시도들.1A to 1B are perspective views illustrating a method of forming a semiconductor device according to the prior art.

도 2는 종래 기술에 의한 반도체 소자의 LPC 폴리 플러그가 제대로 형성되지 못한 평면 사진.2 is a planar photograph of the LPC poly plug of the semiconductor device according to the prior art not properly formed.

도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들.3A to 3D are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

< 도면의 주요부분에 대한 부호의 설명 >Description of the Related Art

10, 100 : 반도체 기판 20, 200 : 게이트 패턴(라인)10, 100: semiconductor substrate 20, 200: gate pattern (line)

30, 180 : BPSG 층간절연막 40 : 감광막 패턴30, 180: BPSG interlayer insulating film 40: Photosensitive film pattern

45 : 보이드(Void) 50 : LPC에 남아있는 BPSG 45: void 50: remaining BPSG in the LPC

60 : LPC 폴리실리콘 플러그 70 : 브릿지 모양 결함60: LPC polysilicon plug 70: Bridge shape defect

110 : 게이트 산화막 120 : 게이트 폴리실리콘층110: gate oxide film 120: gate polysilicon layer

130 : 게이트용 도전층 140 : 하드마스크 질화막130: conductive layer for gate 140: hard mask nitride film

150 : 스페이서 질화막 160 : O2 플라즈마150 spacer nitride film 160 O 2 plasma

170 : 산화막 170: oxide film

본 발명은 반도체 소자의 형성 방법에 대한 것으로써, 특히 게이트 패턴을 형성한 후 ILD(Inter Layer Dielectric)로 이용되는 BPSG(Boron Phosphorus Silicate Glass) 층간절연막을 형성하는 단계에서 O2 플라즈마 처리 공정을 수행하여 보이드(Void)가 발생되는 문제를 방지하는 반도체 소자의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and in particular, an O 2 plasma treatment process is performed in a step of forming a boron phosphorus silicate glass (BPSG) interlayer insulating film used as an inter layer dielectric (ILD) after forming a gate pattern. The present invention relates to a method of forming a semiconductor device that prevents a problem of voids.

반도체 소자가 고집적화 되고 회로의 선폭이 좁아지면서 게이트 패턴 사이를 매립하는 ILD(Inter Layer Dielectric)로 이용되는 층간절연막을 형성하는 공정이 문제가 되고 있다. 상기 절연막으로는 BPSG(Boron Phosphorus Silicate Glass)를 이용하며, 상압 CVD(APCVD)방법으로 820℃ 정도의 온도에서 H2/O2를 주입하면서 열처리하는 공정을 통하여 BPSG를 리플로우하여 게이트 패턴 사이를 매립시킨다. 이때, 게이트 패턴 사이에 보이드(Void)를 발생시키지 않으면서 매립시키는 기술은 반도체 소자의 수율과 신뢰성 향상에 있어서 중요한 역할을 한다. 게이트 패턴을 형성한 후 층간절연막을 형성하고 랜딩 플러그 콘택(Landing Plug Contact : 이하LPC)을 형성하는 공정에 있어서, 게이트 패턴 사이의 층간절연막 내에 보이드(Void)가 형성되어 있는 경우 LPC 형성을 위한 셀프 얼라인 콘택(Self Align Contact: 이하 SAC)공정이 제대로 수행되지 못한다. 따라서, LPC를 매립하는 폴리 실리콘 플러그를 형성하는 단계에서 폴리실리콘 플러그가 LPC 내에 형성되지 못하거나 게이트 패턴 상부에 형성되면서 LPC 간에 브릿지(Bridge)현상을 유발시킨다.As semiconductor devices become highly integrated and line widths of circuits become narrower, a process of forming an interlayer insulating film used as an inter layer dielectric (ILD) which fills between gate patterns has become a problem. BPSG (Boron Phosphorus Silicate Glass) is used as the insulating layer, and BPSG is reflowed through annealing by injecting H 2 / O 2 at a temperature of about 820 ° C by atmospheric pressure CVD (APCVD) to form a gap between gate patterns. Landfill. In this case, the technology of filling the gate patterns without generating voids plays an important role in improving the yield and reliability of the semiconductor device. In the process of forming an interlayer insulating film after forming the gate pattern and forming a landing plug contact (LPC), when a void is formed in the interlayer insulating film between the gate patterns, a self for forming the LPC is formed. Self Align Contact (SAC) process is not performed properly. Therefore, the polysilicon plug may not be formed in the LPC or may be formed on the gate pattern at the step of forming the polysilicon plug to fill the LPC, thereby causing a bridge phenomenon between the LPCs.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 형성 방법을 도시한 사시도들이다.1A and 1B are perspective views illustrating a method of forming a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체 기판(10) 상에 게이트 패턴(20)이 형성되고, BPSG 층간절연막(30)을 형성한다. 다음에는 LPC 형성을 위한 감광막 패턴(40)을 형성한다. 이때, BPSG 층간절연막(30) 형성 과정에서 보이드(Void)(45)가 발생한 것을 볼 수 있다.Referring to FIG. 1A, a gate pattern 20 is formed on a semiconductor substrate 10, and a BPSG interlayer insulating film 30 is formed. Next, the photosensitive film pattern 40 for forming the LPC is formed. In this case, it can be seen that voids 45 are generated in the process of forming the BPSG interlayer insulating film 30.

도 1b를 참조하면, BPSG 층간절연막(30)을 식각하여 LPC 를 형성한다. 이때, 보이드에 의해 SAC 공정이 제대로 수행되지 못하고, BPSG 층간절연막이 남아 있는 것(50)을 볼 수 있다.Referring to FIG. 1B, the BPSG interlayer insulating film 30 is etched to form an LPC. At this time, it can be seen that the SAC process is not properly performed by the voids, and the BPSG interlayer insulating film remains (50).

도 2는 종래 기술에 의한 반도체 소자의 LPC 폴리 플러그가 제대로 형성되지 못한 사진을 도시한 것이다.2 illustrates a photograph in which the LPC poly plug of the semiconductor device according to the prior art is not properly formed.

게이트 라인(20) 사이에 검정색 부분이 BPSG 층간절연막(30)을 나타내며, 점선으로 나타낸 부분은 LPC 콘택 패턴의 모양이고, 폴리실리콘 플러그(60)를 나타낸다. 사진 상의 타원형 실선은 LPC 형성 전의 보이드(Void)에 의한 영향으로 LPC가 형성되지 못한 브릿지(bridge)모양의 결함(70)이 형성되는 문제를 보여준다.The black portion between the gate lines 20 represents the BPSG interlayer insulating film 30, and the portion indicated by the dotted line is in the shape of an LPC contact pattern, and represents the polysilicon plug 60. The elliptical solid line on the picture shows a problem that a bridge-like defect 70 in which the LPC is not formed due to the void before the LPC formation is formed.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 반도체 소자에서 게이트 패턴을 형성한 후 ILD(Inter Layer Dielectric)로 이용되 는 BPSG 층간절연막을 형성하는 단계에서 보이드(Void)가 발생되는 문제를 방지하기 위하여, BPSG 층간절연막과 같은 옥사이드(Oxide) 계열의 얇은 절연막을 게이트 패턴에 형성시킴으로써 층간절연막의 유동성과 갭 필(Gap Fill)능력을 향상시키는 반도체 소자의 형성 방법을 제공함에 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form voids in a step of forming a BPSG interlayer insulating film used as an inter layer dielectric (ILD) after forming a gate pattern in a semiconductor device. In order to prevent the problem caused by forming a thin oxide-based insulating film, such as BPSG interlayer insulating film in the gate pattern to provide a method of forming a semiconductor device to improve the fluidity and gap fill capacity of the interlayer insulating film. have.

본 발명은 상기와 같은 목적을 달성하기 위한 것으로서, 반도체 기판 상에 하드마스크 질화막을 구비한 게이트 패턴을 형성하는 단계와, 상기 게이트 패턴 측벽에 스페이서 질화막을 형성하는 단계와, O2 플라즈마 처리 공정을 수용하여 상기 하드마스크 및 스페이서 질화막의 표면을 산화시켜 산화막을 형성하는 단계 및 상기 반도체 기판 전체 표면에 BPSG 층간절연막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention is to achieve the above object, the step of forming a gate pattern having a hard mask nitride film on a semiconductor substrate, forming a spacer nitride film on the sidewall of the gate pattern, O 2 plasma treatment process Receiving and oxidizing the surfaces of the hard mask and the spacer nitride film to form an oxide film, and forming a BPSG interlayer insulating film on the entire surface of the semiconductor substrate.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들이다.3A to 3D are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

도 3a를 참조하면, 반도체 기판(100) 상에 게이트 산화막(110), 게이트 폴리실리콘층(120), 게이트용 도전층(130) 및 하드마스크 질화막(140)의 적층 구조로 이루어진 게이트 패턴(200)을 형성한다.Referring to FIG. 3A, a gate pattern 200 having a stacked structure of a gate oxide layer 110, a gate polysilicon layer 120, a gate conductive layer 130, and a hard mask nitride layer 140 on a semiconductor substrate 100 may be used. ).

도 3b를 참조하면, 게이트 패턴(200) 측벽에 스페이서 질화막(150)을 형성 한다.Referring to FIG. 3B, a spacer nitride layer 150 is formed on sidewalls of the gate pattern 200.

도 3c를 참조하면, 반도체 기판(100) 상에 O2 플라즈마 처리 공정을 수행하여 하드마스크(140) 및 스페이서 질화막(150)의 표면을 산화시켜 산화막(170)을 형성한다. 이때, O2 플라즈마 처리 공정은 1.2 내지 1.6 Torr의 압력 하에서 450 내지 550W의 RF파워를 유지하고, O2 가스는 3000 내지 4000 sccm 및 N2 가스는 1000 내지 2000 sccm의 유량으로 주입하여 15 내지 25분간 수행함으로써 산화막(170)을 하드마스크(140) 및 스페이서 질화막(160)의 표면에 15 내지 25Å만큼 산화시키는 것이 바람직하다.Referring to FIG. 3C, an oxide film 170 is formed by oxidizing surfaces of the hard mask 140 and the spacer nitride film 150 by performing an O 2 plasma treatment process on the semiconductor substrate 100. At this time, the O 2 plasma treatment process maintains an RF power of 450 to 550 W under a pressure of 1.2 to 1.6 Torr, injects O 2 gas at a flow rate of 3000 to 4000 sccm and N 2 gas at a flow rate of 1000 to 2000 sccm 15 to 25 It is preferable to oxidize the oxide film 170 by 15 to 25 kPa on the surfaces of the hard mask 140 and the spacer nitride film 160 by performing for a minute.

도 3d를 참조하면, 반도체 기판(100) 전체 표면에 BPSG 층간절연막(180)을 형성한다. 이때, 산화막(170)은 BPSG 층간절연막(180)과 같은 옥사이드(Oxide) 계열이기 때문에 유동성과 갭 필(Gap Fill)능력이 향상된다. 따라서, 게이트 패턴 사이의 매립특성이 향상되어, 보이드가 발생하지 않은 것을 볼 수 있다.Referring to FIG. 3D, a BPSG interlayer insulating layer 180 is formed on the entire surface of the semiconductor substrate 100. At this time, since the oxide film 170 is the same oxide layer as the BPSG interlayer insulating film 180, the fluidity and the gap fill ability are improved. Therefore, the buried characteristic between the gate patterns is improved, and it can be seen that no void is generated.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 게이트 패턴을 매립하는 층간절연막 형성시 보이드가 발생하는 것을 방지하기 위하여 BPSG 층간절연막과 같은 옥사이드(Oxide) 계열의 얇은 절연막을 게이트 패턴에 형성시킴으로써, 층간절연막의 유동성과 갭 필(Gap Fill)능력을 향상시킴으로 게이트 패턴 사이의 매립특성을 높이고, 반도체 소자 공정의 수율 및 작업 시간을 단축시킬 수 있는 효과가 있다.As described above, in order to prevent voids from being formed when forming the interlayer insulating film filling the gate pattern of the semiconductor device according to the present invention, an oxide-based thin insulating film such as a BPSG interlayer insulating film is formed in the gate pattern, By improving the fluidity and the gap fill capability of the interlayer insulating layer, it is possible to increase the buried characteristics between the gate patterns and to shorten the yield and the working time of the semiconductor device process.

Claims (3)

반도체 기판 상에 하드마스크 질화막을 구비한 게이트 패턴을 형성하는 단계;Forming a gate pattern having a hard mask nitride film on the semiconductor substrate; 상기 게이트 패턴 측벽에 스페이서 질화막을 형성하는 단계;Forming a spacer nitride film on sidewalls of the gate pattern; O2 플라즈마 처리 공정을 수행하여 상기 하드마스크 질화막 및 스페이서 질화막의 표면만을 산화시켜 산화막을 형성하는 단계; 및Performing an O 2 plasma treatment process to oxidize only surfaces of the hard mask nitride film and the spacer nitride film to form an oxide film; And 상기 반도체 기판 전체 표면에 BPSG 층간절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 형성 방법.Forming a BPSG interlayer insulating film on the entire surface of the semiconductor substrate. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1항에 있어서,The method of claim 1, 상기 O2 플라즈마 처리 공정은 1.2 내지 1.6 Torr의 압력 하에서 450 내지 550W의 RF파워를 유지하고, O2 가스는 3000 내지 4000 sccm 및 N2 가스는 1000 내지 2000 sccm의 유량으로 주입하여 15 내지 25분간 실시하는 것을 특징으로 하는 반도체 소자의 형성 방법.The O 2 plasma treatment process maintains an RF power of 450 to 550 W under a pressure of 1.2 to 1.6 Torr, injects O 2 gas at 3000 to 4000 sccm and N 2 gas at a flow rate of 1000 to 2000 sccm for 15 to 25 minutes. A method of forming a semiconductor device, characterized by the above-mentioned. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제 1항에 있어서,The method of claim 1, 상기 산화막은 하드마스크 및 스페이서 질화막 표면에 15 내지 25Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The oxide film is a method of forming a semiconductor device, characterized in that formed on the surface of the hard mask and the spacer nitride film having a thickness of 15 to 25 GPa.
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US20020132397A1 (en) * 2001-03-15 2002-09-19 Weimer Ronald A. Use of atomic oxygen process for improved barrier layer
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US20020132397A1 (en) * 2001-03-15 2002-09-19 Weimer Ronald A. Use of atomic oxygen process for improved barrier layer
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