KR100492790B1 - Device isolation insulating film formation method of semiconductor device - Google Patents

Device isolation insulating film formation method of semiconductor device Download PDF

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KR100492790B1
KR100492790B1 KR1019970028704A KR19970028704A KR100492790B1 KR 100492790 B1 KR100492790 B1 KR 100492790B1 KR 1019970028704 A KR1019970028704 A KR 1019970028704A KR 19970028704 A KR19970028704 A KR 19970028704A KR 100492790 B1 KR100492790 B1 KR 100492790B1
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insulating film
forming
trench
film
semiconductor device
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KR19990004577A (en
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김시범
송정규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
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Abstract

본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 반도체기판 상부에 트렌치를 형성하고, 상기 구조의 상부에 질화막 또는 산질화막을 증착한 다음, 상기 트렌치를 매립하는 절연막을 형성함으로써 상기 반도체기판과 트렌치의 경계부분의 상기 절연막이 손실되는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.The present invention relates to a method of forming a device isolation insulating film for a semiconductor device, wherein the semiconductor substrate is formed by forming a trench on the semiconductor substrate, depositing a nitride film or an oxynitride film on the structure, and then forming an insulating film filling the trench. It is a technique for preventing the loss of the insulating film at the boundary between the trench and the trench and thereby improving the characteristics and reliability of the semiconductor device.

Description

반도체소자의 소자분리절연막 형성방법Device isolation insulating film formation method of semiconductor device

본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 소자분리막 형성시 트렌치 코너부위에서의 식각속도를 감소시켜 후속 식각공정시 유발되는 절연막의 손실을 감소시킴으로써 소자의 절연특성을 향상시키고 그에 따른 반도체소자의 수율 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and in particular, by reducing the etching rate at the trench corners when forming the device isolation film to reduce the loss of the insulating film caused in the subsequent etching process to improve the insulating properties of the device The present invention relates to a technique for improving yield and reliability of semiconductor devices.

고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.

일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.

그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅 현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.

또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1 ㎛.

이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 나타내는 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.

먼저, 반도체기판(11) 상부에 제1절연막(12)을 형성한다.First, the first insulating layer 12 is formed on the semiconductor substrate 11.

다음, 상기 제1절연막(12) 상부에 제2절연막(13)을 형성한다.Next, a second insulating layer 13 is formed on the first insulating layer 12.

이때, 상기 제1,2절연막은 각각 산화막(12)과 질화막(13)으로 형성한 것이다. In this case, the first and second insulating films are formed of an oxide film 12 and a nitride film 13, respectively.

그 다음, 상기 제2절연막(13) 상부에 감광막(도시안됨)을 도포한 다음, 소자분리용 노광마스크를 이용한 노광 및 식각공정을 실시하여 감광막 패턴(도시안됨)을 형성한다.Next, a photoresist (not shown) is coated on the second insulating layer 13, and then an exposure and etching process using an exposure mask for device isolation is performed to form a photoresist pattern (not shown).

그 다음, 상기 감광막 패턴을 식각마스크로 하여 상기 제1,2절연막(12,13) 및 소정깊이의 반도체기판(11)을 식각하여 트렌치(도시안됨)를 형성한다.Next, the first and second insulating layers 12 and 13 and the semiconductor substrate 11 having a predetermined depth are etched using the photoresist pattern as an etching mask to form trenches (not shown).

그리고, 제1차 열산화공정을 실시하여 제1열산화막을 성장시킨 후 습식식각을 통해 상기 제1열산화막을 제거함으로써 상기 트렌치 형성공정시 발생된 상기 트렌치 표면의 결함을 제거한다.After the first thermal oxidation process is performed to grow the first thermal oxide layer, the first thermal oxide layer is removed by wet etching to remove defects on the trench surface generated during the trench formation process.

그 후, 제2차 열산화공정으로 제2열산화막(도시안됨)을 성장시켜 표면을 친수화되게 한 다음, 상기 트렌치를 매립하는 제3절연막(14)을 형성한다.Thereafter, a second thermal oxide film (not shown) is grown in the second thermal oxidation process to make the surface hydrophilic, and then a third insulating film 14 filling the trench is formed.

이때, 상기 제3절연막(14)은 저압화학기상증착 ( low pressure chemical vapor deposition, 이하 LPCVD 라 함 ) 산화막, 오존-테오스 (O3-tetra ethyl ortho silicate glass, 이하 O3-TEOS 라 함 ) 또는 고밀도플라즈마화학기상증착 ( high density plasma chemical vapor deposition, 이하 HDP CVD 라 함 ) 산화막 등으로 증착한 것이다. (도 1a)At this time, the third insulating layer 14 is a low pressure chemical vapor deposition (hereinafter referred to as LPCVD) oxide film, ozone-theos (O 3 -tetra ethyl ortho silicate glass, hereinafter referred to as O 3 -TEOS) Or by high density plasma chemical vapor deposition (hereinafter referred to as HDP CVD) oxide film. (FIG. 1A)

그리고, 후속 열처리공정을 실시하여 상기 제3절연막(14)을 치밀화시킨 다음, CMP 공정을 실시하여 두껍게 증착된 산화막을 제거하여 평탄화시킨다.Subsequently, a third heat treatment process is performed to densify the third insulating layer 14, and then a CMP process is performed to remove the planarized oxide film.

그런데, 상기 CMP 공정을 진행한 후, 후속공정인 세정공정에서 사용되는 HF 를 포함하는 용액에 의해서 상기 트렌치를 매립하는 제3절연막(14)이 손실되는 현상이 발생한다.However, after the CMP process, the third insulating film 14 filling the trench is lost by the solution containing HF used in the subsequent cleaning process.

특히, 상기 반도체기판(11)과 제3절연막(14)이 인접하는 부분의 손실이 가장 커 턱짐현상 ( moat )(15)이 유발된다. (도 1b)In particular, the loss of the portion where the semiconductor substrate 11 and the third insulating layer 14 are adjacent to each other is greatest, causing a moat 15. (FIG. 1B)

상기한 바와 같은 얕은 트렌치 소자분리막 형성방법은, CMP 공정 후의 세정공정에 사용되는 HF 를 함유하는 용액에 의하여 턱짐현상이 유발되고, 그로 인하여 후속 공정인 게이트전극 형성공정시 실시되는 다결정실리콘의 패터닝 공정시 잔류물이 남게 되어 반도체소자의 불량을 초래하고, 상기 절연막이 손실된 부분에서는 전기장이 집중되어 모스펫 ( MOSFET ) 의 스윙 ( swing ) 특성을 열화시키는 문제점이 있다.In the method of forming a shallow trench isolation layer as described above, a crushing phenomenon is caused by a solution containing HF used in the cleaning process after the CMP process, and thus a polycrystalline silicon patterning process is performed in the subsequent gate electrode forming process. When the residue remains, it causes a defect of the semiconductor device, and the electric field is concentrated at the portion where the insulating film is lost, thereby degrading the swing characteristic of the MOSFET.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치의 코너부위에서의 식각속도를 감소시킴으로써 후속공정을 용이하게 하고 그에 따른 반도체소자의 공정수율 및 신뢰성을 향상시키는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, the device isolation insulating film is formed to reduce the etching speed at the corners of the trenches, thereby facilitating subsequent processes and thereby improving the process yield and reliability of the semiconductor devices. The purpose is to provide a method.

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,Method for forming a device isolation insulating film of a semiconductor device according to the present invention for achieving the above object,

반도체기판 상부에 트렌치를 형성하는 공정과,Forming a trench on the semiconductor substrate;

상기 트렌치 표면에 열산화막을 형성하는 공정과,Forming a thermal oxide film on the trench surface;

전체표면상부에 일정두께의 제1절연막을 형성하는 공정과,Forming a first insulating film having a predetermined thickness over the entire surface;

상기 트렌치를 매립하는 제2절연막을 전체표면상부에 형성하는 공정과,Forming a second insulating film filling the trench over the entire surface;

상기 제2절연막을 열처리하고, 평탄화식각하는 공정을 포함하는 것을 특징으로 한다.And heat-treating and planarizing etching the second insulating layer.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성공정을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a device isolation insulating film forming process of a semiconductor device according to an embodiment of the present invention.

먼저, 반도체기판(21) 상부에 제1절연막(22)인 패드산화막을 형성한다.First, a pad oxide film, which is the first insulating film 22, is formed on the semiconductor substrate 21.

그리고, 전체표면상부에 제2절연막(23)인 질화막을 일정두께로 형성한다.A nitride film, which is the second insulating film 23, is formed on the entire surface at a constant thickness.

그 다음에, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 제2절연막(23), 제1절연막(22) 및 소정깊이의 반도체기판(21)을 식각하여 트렌치(25)를 형성한다.Next, the trench 25 is formed by etching the second insulating layer 23, the first insulating layer 22, and the semiconductor substrate 21 having a predetermined depth by an etching process using an element isolation mask (not shown).

상기 트렌치(25) 표면에 제1열산화막(도시안됨)을 형성하는 제1차 산화공정을 실시한다.A first oxidation process is performed to form a first thermal oxide film (not shown) on the trench 25.

그리고, 상기 제1열산화막을 습식식각으로 제거한다.Then, the first thermal oxide film is removed by wet etching.

이때, 제1차 산화공정과 이로 인해 형성된 제1열산화막의 제거공정은 상기 트렌치(25)형성공정시 발생된 트렌치(25) 표면의 결함을 제거하기 위한 것이다.At this time, the first oxidation process and the removal process of the first thermal oxide film formed thereon are for removing defects on the surface of the trench 25 generated during the trench 25 formation process.

그 다음, 제2차 산화공정으로 트렌치(25) 표면에 제2열산화막(24)을 형성한다. (도 2a)Next, a second thermal oxide film 24 is formed on the surface of the trench 25 by a second oxidation process. (FIG. 2A)

그 후, 상기 구조 전표면에 제3절연막(26)을 증착한다.Thereafter, a third insulating film 26 is deposited on the entire surface of the structure.

이때, 상기 제3절연막(26)은 산질화막 또는 질화막을 사용하여 증착한다.In this case, the third insulating layer 26 is deposited using an oxynitride layer or a nitride layer.

여기서, 상기 제3절연막(26)을 산질화막으로 사용할 경우 질소와 산소의 비 N/O이 0.5 이상인 SiH4/NH3 /N2O/N2 가스를 반응기체로 사용하여 PECVD 방법으로 50 ∼ 300 Å 정도 두께 증착한다.In this case, when the third insulating layer 26 is used as an oxynitride layer, the SiH 4 / NH 3 / N 2 O / N 2 gas having a nitrogen / oxygen ratio of N / O of 0.5 or more is used as a reactor and 50 to PECVD. Deposit 300 mm thick.

또한, 상기 제3절연막(26)을 질화막으로 사용할 경우 SiH4/NH3/N2 가스를 반응기체로 사용하여 LPCVD 또는 PECVD 방법으로 50 ∼ 300 Å 정도 두께 증착한다. (도 2b)In addition, when the third insulating film 26 is used as a nitride film, SiH 4 / NH 3 / N 2 gas is used as a reactor to deposit about 50 to 300 kW thick by LPCVD or PECVD. (FIG. 2B)

그 다음, 상기 제3절연막(26) 상부에 상기 트렌치(25)를 매립하는 제4절연막(27)을 증착한다.Next, a fourth insulating layer 27 filling the trench 25 is deposited on the third insulating layer 26.

이때, 상기 제4절연막(27)은 O3-TEOS으로 대기압화학기상증착 ( atmospheric pressure chemical vapor deposition, 이하 APCVD 라 함 ) 방법으로 유.에스.지. ( undoped silicate glass, 이하 USG 라 함 ) 를 증착한다. 상기 USG 막은 HDP-CVD 방법으로 증착할 수도 있다.In this case, the fourth insulating layer 27 is an O 3 -TEOS by atmospheric pressure chemical vapor deposition (APCVD) method. (undoped silicate glass, hereinafter USG) is deposited. The USG film may be deposited by the HDP-CVD method.

또한, 상기 O3-TEOS USG 는 4 ~ 5.5 % 정도의 O3 농도로 450 ~ 550 ℃의 온도에서 6000 ~ 10000 Å 정도 두께로 형성하여 상기 O3-TEOS USG 특유의 하지의존성을 제거한다.In addition, the O 3 -TEOS USG is formed with a thickness of about 6000 ~ 10000 kPa at a temperature of 450 ~ 550 ℃ at an O 3 concentration of about 4 ~ 5.5% to remove the underlying dependence peculiar to the O 3 -TEOS USG.

그 다음, 상기 제4절연막(27)을 950 ~ 1100 ℃정도의 질소분위기에서 30 분 내지 2 시간 동안 열처리함으로써 상기 제3절연막(26)의 질소성분이 확산되어 인접한 산화막이 질화처리되게 한다.Thereafter, the fourth insulating layer 27 is heat-treated in a nitrogen atmosphere at about 950 to 1100 ° C. for 30 minutes to 2 hours so that nitrogen components of the third insulating layer 26 are diffused so that the adjacent oxide layer is nitrided.

이때, 상기 열처리공정은 상기 제4절연막(27)에 비하여 상기 산질화막 또는 질화막의 습식식각 선택비가 20 : 1 이상으로 작기 때문에 후속 습식식각공정시 상기 도 1b에서 도시한 바와 같이 트렌치 코너부위에서의 습식식각속도를 저하시키기 위한 것이다. (도 2c)In this case, since the wet etching selectivity of the oxynitride layer or the nitride layer is smaller than 20: 1 compared to the fourth insulating layer 27, the heat treatment process may be performed at the trench corner portion as shown in FIG. 1B during the subsequent wet etching process. This is to reduce the wet etching rate. (FIG. 2C)

그 다음에, 후속 CMP 공정을 실시하여 평탄화시키고, 상기 제2절연막(23)인 질화막을 제거하여 얕은 트렌치 소자분리막 형성공정을 완료한다. (도 2d)Subsequently, a subsequent CMP process is performed to planarize, and the nitride layer, which is the second insulating layer 23, is removed to complete the process of forming a shallow trench isolation layer. (FIG. 2D)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, 반도체기판 상부에 트렌치를 형성하고, 상기 구조의 상부에 질화막 또는 산질화막을 증착한 다음, 상기 트렌치를 매립하는 절연막을 형성함으로써 상기 반도체기판과 트렌치의 경계부분의 상기 절연막이 손실되는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of forming a device isolation insulating film of the semiconductor device according to the present invention, a trench is formed over the semiconductor substrate, a nitride film or an oxynitride film is deposited over the structure, and an insulating film for filling the trench is formed. As a result, the insulating film at the boundary between the semiconductor substrate and the trench is prevented from being lost, and thus the characteristics and reliability of the semiconductor device are improved.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.

도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the present invention.

〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>

11, 21 : 반도체기판 12, 22 : 제1절연막11, 21: semiconductor substrate 12, 22: first insulating film

13, 23 : 제2절연막 14, 26 : 제3절연막13, 23: second insulating film 14, 26: third insulating film

15 : 턱짐현상 24 : 제2열산화막15: jaw phenomenon 24: second thermal oxide film

25 : 트렌치 27 : 제4절연막25 trench 27 fourth insulating film

Claims (7)

반도체기판 상부에 트렌치를 형성하는 공정과,Forming a trench on the semiconductor substrate; 상기 트렌치 표면에 열산화막을 형성하는 공정과,Forming a thermal oxide film on the trench surface; 전체표면상부에 일정두께의 제1절연막을 형성하는 공정과,Forming a first insulating film having a predetermined thickness over the entire surface; 상기 트렌치를 매립하는 제2절연막을 전체표면상부에 형성하는 공정과,Forming a second insulating film filling the trench over the entire surface; 상기 제2절연막을 열처리하되, 950 ~ 1100 ℃ 온도의 질소분위기에서 30 분 내지 2 시간 동안 실시하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.A method of forming a device isolation insulating film of a semiconductor device, characterized in that the step of heat-treating the second insulating film, the process for 30 minutes to 2 hours in a nitrogen atmosphere of 950 ~ 1100 ℃ temperature. 청구항 1 에 있어서,The method according to claim 1, 상기 제1절연막은 산질화막 또는 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.And the first insulating film is formed of an oxynitride film or a nitride film. 청구항 1 에 있어서,The method according to claim 1, 상기 제1절연막으로 산질화막을 사용하는 경우는 질소와 산소의 비 N/O 이 0.5 이상인 SiH4/NH3 /N2O/N2 가스를 반응기체로 사용하여 PECVD 방법으로 50 ∼ 300 Å 정도 두께 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.In the case of using the oxynitride film as the first insulating film, about 50 to 300 kPa by PECVD method using SiH 4 / NH 3 / N 2 O / N 2 gas having a nitrogen / oxygen ratio N / O of 0.5 or more as a reactive gas. A method of forming a device isolation insulating film of a semiconductor device, characterized in that the deposition on the thickness. 청구항 1 에 있어서,The method according to claim 1, 상기 제1절연막으로 질화막을 사용하는 경우는 SiH4/NH3/N2 가스를 반응기체로 사용하여 PECVD 또는 LPCVD 방법으로 50 ∼ 300 Å 정도 두께 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.In the case of using a nitride film as the first insulating film, a device isolation insulating film is formed in a thickness of about 50 to 300 mW using PECVD or LPCVD method using SiH 4 / NH 3 / N 2 gas as a reactor. Way. 청구항 1 에 있어서,The method according to claim 1, 상기 제2절연막은 APCVD 방법으로 증착된 O3-TEOS USG 또는 APCVD 방법으로 증착된 HDP-CVD USG 로 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The second insulating layer is an APCVD method O 3 -TEOS element isolation insulating film formation method of a semiconductor device characterized in that the USG or APCVD deposition method in the HDP-USG deposited by CVD deposition. 청구항 5 에 있어서,The method according to claim 5, 상기 O3-TEOS USG 는 4 ∼ 5.5% 농도의 O3 를 이용하여 450 ∼ 550 ℃ 의 온도에서 6000 ∼ 10000 Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The method for forming a device isolation insulating film of a semiconductor device, characterized in that the O 3 -TEOS USG is formed in a thickness of 6000 to 10000 kPa at a temperature of 450 ~ 550 ℃ using O 3 of 4 to 5.5% concentration. 청구항 5 에 있어서,The method according to claim 5, 상기 HDP-CVD USG는 6000 ∼ 10000 Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The HDP-CVD USG is a method of forming a device isolation insulating film of a semiconductor device, characterized in that formed in the thickness of 6000 to 10000 Å.
KR1019970028704A 1997-06-28 1997-06-28 Device isolation insulating film formation method of semiconductor device KR100492790B1 (en)

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KR850003068A (en) * 1983-10-14 1985-05-28 미쓰다 가쓰시게 Semiconductor integrated circuit and manufacturing method thereof
JPH02296352A (en) * 1989-05-11 1990-12-06 Nec Corp Semiconductor device
KR940012574A (en) * 1992-11-02 1994-06-23 김주용 Method of forming insulating film for device isolation
KR950021402A (en) * 1993-12-31 1995-07-26 김주용 Trench type isolation film formation method
KR100297171B1 (en) * 1994-12-29 2001-10-24 박종섭 Method for forming isolation layer of semiconductor device

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KR850003068A (en) * 1983-10-14 1985-05-28 미쓰다 가쓰시게 Semiconductor integrated circuit and manufacturing method thereof
JPH02296352A (en) * 1989-05-11 1990-12-06 Nec Corp Semiconductor device
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KR950021402A (en) * 1993-12-31 1995-07-26 김주용 Trench type isolation film formation method
KR100297171B1 (en) * 1994-12-29 2001-10-24 박종섭 Method for forming isolation layer of semiconductor device

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