KR20010045420A - Method for forming interlayer insulating layer of semiconductor device - Google Patents
Method for forming interlayer insulating layer of semiconductor device Download PDFInfo
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- KR20010045420A KR20010045420A KR1019990048709A KR19990048709A KR20010045420A KR 20010045420 A KR20010045420 A KR 20010045420A KR 1019990048709 A KR1019990048709 A KR 1019990048709A KR 19990048709 A KR19990048709 A KR 19990048709A KR 20010045420 A KR20010045420 A KR 20010045420A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 반도체 소자의 층간절연막 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for forming an interlayer insulating film of a semiconductor device.
반도체 소자의 고집적화에 따라 캐패시터의 단차는 높아지고, 콘택의 깊이가 깊어지면서 공정상 많은 문제점이 대두되고 있다. 일반적으로 고단차의 패턴을 매립하기 위하여 종래와 같이 BPSG(borophospho silicate glass)를 사용하는 경우는 고온 열처리 공정이 수반되어야 하기 때문에 BPSG막 하부의 캐패시터의 특성이 저하된다.As the integration of semiconductor devices increases, the steps of the capacitors increase and the depth of the contacts deepens, causing many problems in the process. In general, when BPSG (borophospho silicate glass) is used in order to fill a pattern of high steps, the characteristics of the capacitor under the BPSG film are deteriorated because a high temperature heat treatment process must be involved.
최근에 주목받기 시작한 고밀도 플라즈마 화학기상증착법(high density plasma chemical vapor deposition, 이하 HDP CVD라 함)으로 산화막을 형성하여 패턴 사이를 매립하고 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함) 공정을 실시하여 평탄화시키는 방법이 있으나 이러한 방법은 콘택의 깊이를 보다 깊게 하고 플라즈마 손상(plasma damage)의 문제점을 갖고 있을 뿐만 아니라 부분적인 평탄화(partial planar)시 셀블럭(cell block)의 중심부가 높아지면서 전체 단차가 증가하는 문제점이 있다.An oxide film is formed by high density plasma chemical vapor deposition (HDP CVD), which has recently been attracting attention, and is buried between patterns, and a chemical mechanical polishing (CMP) process is performed. Planarization, but this method not only deepens the depth of contact and has the problem of plasma damage, but also increases the center of the cell block during partial planarization. There is a problem that increases.
또한, SiH4, H2O2, H2O, O2의 반응소스를 이용하여 -10 ℃ 내지 50 ℃ 사이의 저온에서 패턴 사이를 매립하고 언도프트(undoped) 층간절연막을 형성하는 방법이 제시되었다. 이러한 반응소스를 이용하여 저온 산화막을 형성할 경우, 평탄화 특성에 의해 고단차의 패턴을 매립하면서 전체 단차를 줄여 후속 공정에 제약을 주는 각도를 매우 완만하게 할 수 있다. 그러나 패턴의 밀도에 따른 절연막의 두께가 영역별로 차이가 나고, 두께가 얇아 전체 단차를 줄이는데 한계가 있기 때문에 소자 적용에는 제약이 있다. 즉, SiH4, H2O2, O2의 반응소스를 이용 저온, 저압에서 화학기상증착 방식으로 만든 산화막을 DRAM 소자 등의 층간절연막으로 이용할 경우, 셀블럭(cell block)과 센스 증폭기(sense amplifier), 디코더(decoder), 테스트 패턴(test pattern) 영역에서 발생하는 단차는 매우 크고, 패턴 밀도가 일부에 치우쳐 높기 때문에 완전한 평탄화가 이루어지기 힘들다.In addition, a method of embedding an undoped interlayer insulating film and embedding the pattern at a low temperature between -10 ° C and 50 ° C using a reaction source of SiH 4 , H 2 O 2 , H 2 O, O 2 is presented. It became. When the low-temperature oxide film is formed using such a reaction source, the flattening characteristics may fill the pattern of the high step and reduce the overall step so that the angle limiting the subsequent process may be very gentle. However, there is a limitation in the application of the device because the thickness of the insulating layer according to the density of the pattern is different for each region, and the thickness is so thin that there is a limit in reducing the overall step. That is, when an oxide film made by chemical vapor deposition at low temperature and low pressure using a reaction source of SiH 4 , H 2 O 2 , and O 2 is used as an interlayer insulating film such as a DRAM device, a cell block and a sense amplifier are used. The level difference in the amplifier, decoder, and test pattern areas is very large, and because the pattern density is partially biased, it is difficult to achieve perfect planarization.
첨부된 도면 도1은 종래 기술에 따른 층간절연막 형성 후 디코더(D), 셀블럭 중심부(C), 센스 증폭기(S/A) 영역을 보이는 SEM 사진이다.1 is a SEM photograph showing a decoder (D), a cell block center (C), and a sense amplifier (S / A) after forming an interlayer insulating film according to the prior art.
자체 유동성을 갖는 산화막의 특성상 셀블럭 위의 산화막이 흘러내리면서 전체 단차가 줄어들고 각도가 완만하게 되지만 패턴이 밀접한 센스증폭기 지역의 절연막 두께는 디코더나 테스트 패턴 영역 보다 매우 높게 된다.As the oxide film on the cell block flows down the oxide film on the cell block, the overall step is reduced and the angle becomes smooth. However, the thickness of the insulating film in the sense amplifier region where the pattern is close is much higher than that of the decoder or test pattern region.
셀블럭 영역만 노출시켜 산화막을 제거함으로서 전체 단차를 줄이는 셀 리세스(cell recess)공정이 있다.There is a cell recess process that reduces the overall step by removing the oxide layer by exposing only the cell block region.
도2a 내지 도2c를 참조하여 종래의 셀 리세스 공정을 상세히 설명한다.2A to 2C, a conventional cell recess process will be described in detail.
도2a는 캐패시터 등과 같은 소정의 하부구조(21) 형성이 완료된 반도체 기판(20) 상에 층간절연막(22)을 형성하고, 셀블럭 영역을 오픈시키는 식각마스크로서 감광막 패턴(PR)을 형성한 상태를 보이고 있다. 도면부호 'T'는 테스트 패턴 영역, 'D'는 디코더 영역, 'C'는 셀블럭 영역, 'S/A'는 센스증폭기 영역을 나타낸다.2A shows a state in which an interlayer insulating film 22 is formed on a semiconductor substrate 20 on which a predetermined substructure 21, such as a capacitor, is formed, and a photoresist pattern PR is formed as an etching mask for opening a cell block region. Is showing. Reference numeral 'T' denotes a test pattern region, 'D' denotes a decoder region, 'C' denotes a cell block region, and 'S / A' denotes a sense amplifier region.
도2b는 셀블럭 영역의 층간절연막(22)일부를 제거한 후 감광막 패턴을 제거한 것을 나타내고 있다.FIG. 2B shows that the photoresist pattern is removed after removing a portion of the interlayer insulating film 22 in the cell block region.
도2c는 도2b의 과정까지 완료된 반도체 기판(20) 전면을 CMP하여 평탄화시킨 상태를 보이고 있다.FIG. 2C shows a state where the entire surface of the semiconductor substrate 20 completed by the process of FIG. 2B is planarized by CMP.
도3a는 종래 기술에 따른 층간절연막 형성 후 테스트 패턴 영역과 셀블럭의 단차를 비교하여 보이는 그래프이고, 도3b는 종래 기술에 따른 층간절연막 형성 후 디코더 영역과 셀블럭의 단차를 비교하여 보이는 그래프이다.FIG. 3A is a graph showing a comparison between the test pattern region and the cell block step after forming the interlayer insulating film according to the prior art, and FIG. 3B is a graph comparing the step between the decoder region and the cell block after forming the interlayer insulating film according to the prior art. .
도3a와 도3b는 층간절연막 증착 전, 후의 단차를 서로 비교하여 나타낸 것이다. 도3a의 그래프에 나타난 바와 같이 층간절연막 형성 전 10500 Å이던 셀블럭 중심부(C)의 단차는, SiH4, H2O2, H2O, O2의 반응소스를 이용하여 저온, 저압하에서 패턴 사이를 매립하는 언도프트 층간절연막을 증착한 후에는 9000 Å으로 낮아져 1500 Å으로 전체 단차가 줄어들었지만, 센스 증폭기 영역(S/A)은 층간절연막 형성후 테스트 패턴 영역(T)과 비교하여 3000 Å 정도 새로운 단차가 형성됨을 보이고 있고, 도3b는 층간절연막 형성으로 디코더 영역(D)과 비교하여 센스증폭기 영역(S/A)의 단차가 증가하는 것을 보이고 있다. 도3a 및 도3b 각각에서 도면부호 'd1'은 센스증폭기 영역(S/A)과 테스트 패턴 영역(T)간의 단차(약 3000 Å)를 나타내고, 'd2'는 센스증폭기 영역(S/A)과 디코더 영역(D)간의 단차(약 3000 Å)를 나타낸다.3A and 3B show the difference between the steps before and after the deposition of the interlayer insulating film. As shown in the graph of FIG. 3A, the step difference of the center of the cell block C, which was 10500 mW before the formation of the interlayer insulating film, was obtained by using a reaction source of SiH 4 , H 2 O 2 , H 2 O, and O 2 . After the deposition of the undoped interlayer insulating film filling the gap, the total step was reduced to 9000 Å and 1500 Å, but the sense amplifier area (S / A) was 3000 Å compared to the test pattern area (T) after the interlayer insulation film was formed. 3B shows that a new step is formed, and FIG. 3B shows that the step difference between the sense amplifier area S / A is increased compared to the decoder area D due to the formation of an interlayer insulating film. 3A and 3B, reference numeral 'd 1 ' denotes a step (about 3000 mV) between the sense amplifier region S / A and the test pattern region T, and 'd 2 ' denotes the sense amplifier region S /. The step (about 3000 mW) between A) and the decoder area D is shown.
전술한 바와 같은 셀 리세스 공정 후에 셀블럭 영역(C)을 제외한 테스트 패턴 영역(T), 디코더 영역(D) 및 센스 증폭기 영역(S/A)에는 약 6000 Å 두께의 금속배선 등이 형성되는데, 이에 따라 셀블럭 영역(C)과 테스트 패턴 영역(T), 디코더 영역(D) 및 센스 증폭기 영역(S/A) 간에 다시 단차가 발생하는 문제점이 있다.After the cell recess process as described above, a metal wiring having a thickness of about 6000 kHz is formed in the test pattern region T, the decoder region D, and the sense amplifier region S / A except the cell block region C. Accordingly, there is a problem that a step occurs again between the cell block region C, the test pattern region T, the decoder region D, and the sense amplifier region S / A.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 층간절연막 형성 후 센스 증폭기 영역의 단차가 증가하는 것을 방지할 수 있으며, 금속 배선 형성 이후 셀블럭 영역과 테스트 패턴 영역, 디코더 영역 및 센스 증폭기 영역 간에 다시 단차가 커지는 문제점을 해결할 수 있는, 반도체 소자의 층간절연막 형성 방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention can prevent the step difference of the sense amplifier region from increasing after the formation of the interlayer insulating film. Another object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device, which can solve the problem of increasing the level difference.
도1은 종래 기술에 따른 층간절연막 형성 후 디코더, 셀블럭 중심부, 센스 증폭기 영역을 보이는 SEM 사진,1 is a SEM photograph showing a decoder, a center of a cell block, and a sense amplifier after forming an interlayer dielectric layer according to the prior art;
도2a 내지 도2c는 종래 기술에 따른 셀 리세스 공정 단면도,2A-2C are cross-sectional views of a cell recess process according to the prior art;
도3a는 종래 기술에 따른 층간절연막 형성 후 테스트 패턴 영역과 셀블럭의 단차를 비교하여 보이는 그래프,Figure 3a is a graph showing the comparison between the test pattern region and the step of the cell block after the interlayer insulating film is formed according to the prior art,
도3b는 종래 기술에 따른 층간절연막 형성 후 디코더 영역과 셀블럭의 단차를 비교하여 보이는 그래프,FIG. 3B is a graph showing a comparison between the decoder region and the cell block after forming the interlayer dielectric layer according to the prior art; FIG.
도4a 내지 도4c는 본 발명의 일실시예에 따른 층간절연막 형성 공정 단면도,4A to 4C are cross-sectional views of an interlayer insulating film forming process according to an embodiment of the present invention;
도5a는 본 발명의 일실시에 따른 층간절연막 형성 후 테스트 패턴 영역과 셀블럭의 단차를 비교하여 보이는 그래프,FIG. 5A is a graph illustrating a comparison between a test pattern region and a step of a cell block after formation of an interlayer dielectric layer according to an embodiment of the present invention; FIG.
도5b는 본 발명의 일실시예에 따른 층간절연막 형성 후 디코더 영역과 셀블럭의 단차를 비교하여 보이는 그래프.FIG. 5B is a graph illustrating a comparison between the decoder region and the cell block after forming the interlayer dielectric layer according to the exemplary embodiment of the present invention. FIG.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
40: 반도체 기판 41: 하부구조40: semiconductor substrate 41: substructure
42, 44: 보호막 43: SiOxHy산화막42, 44: protective film 43: SiO x H y oxide film
상기와 같은 목적을 달성하기 위한 본 발명은 화학기상증착 장치에서 하부구조 형성이 완료된 반도체 기판 상부에 제1 보호막을 형성하는 제1 단계; SiH4, H2O2, H2O, O2의 반응소스를 이용하여 -10 ℃ 내지 50 ℃ 사이의 온도 및100 Torr 보다 낮은 압력 조건에서, 층간절연막으로서 SiOxHy산화막을 형성하는 제2 단계; 상기 SiOxHy산화막 상에 제2 보호막을 형성하는 제3 단계; 상기 제2 보호막 상에 셀블럭 영역과 센스증폭기 영역을 오픈하는 식각마스크를 형성하는 제4 단계; 상기 셀블럭 영역 및 상기 센스증폭기 영역의 상기 SiOxHy산화막 일부를 제거하는 제5 단계; 상기 식각마스크를 제거하여 상기 식각마스크가 형성되었던 경계부위의 첨점을 노출시키는 제6 단계; 및 상기 첨점을 제거하여 평탄화시키는 제7 단계를 포함하는 반도체 소자 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a first protective film on the upper surface of the semiconductor substrate in which the bottom structure is formed in the chemical vapor deposition apparatus; A method of forming a SiO x H y oxide film as an interlayer insulating film using a reaction source of SiH 4 , H 2 O 2 , H 2 O, O 2 at a temperature between -10 ° C. and 50 ° C. and a pressure lower than 100 Torr. Two steps; Forming a second passivation layer on the SiO x H y oxide layer; Forming an etch mask on the second passivation layer to open a cell block region and a sense amplifier region; Removing a portion of the SiO x H y oxide layer in the cell block region and the sense amplifier region; A sixth step of removing the etching mask to expose the peaks at the boundary where the etching mask is formed; And a seventh step of removing and removing planarization and planarization.
본 발명은 셀블럭의 단차를 감소시키고, 센스 증폭기와 디코더, 테스트 패턴 영역의 단차도 줄이기 위해 먼저 산화막을 증착함으로써 셀블럭 가장자리(cell block edge)의 각도를 줄일 수 있고 이후 셀블럭 영역과 센스 증폭기 영역만 오픈 한 후 센스 증폭기와 디코더 영역 단차만큼 산화막을 제거함으로써 전체 단차를 감소시키는데 특징이 있다.The present invention can reduce the angle of the cell block edge by first depositing an oxide layer in order to reduce the step difference of the cell block, and also to reduce the step difference of the sense amplifier, the decoder, and the test pattern area, and then the cell block area and the sense amplifier. After opening only the area, the oxide film is removed by the sense amplifier and decoder area steps to reduce the overall step.
이하, 첨부된 도면 도4a 내지 도4c를 참조하여 본 발명의 일실시에 따른 층간절연막 형성 방법을 상세히 설명한다.Hereinafter, an interlayer insulating film forming method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도4a에 도시한 바와 같이 먼저, 캐패시터 등과 같은 하부구조(41) 형성이 완료된 반도체 기판(40) 상의 자연산화막 또는 불순물을 제거한다. 이때, 상기 자연산화막 또는 불순물을 제거하기 위하여 식각액과 완충액의 비가 50:1 이상인 BOE(buffered oxide etchant) 용액을 이용하거나, H2SO4와 H2O2수용액을 2:1 내지 5:1 부피 비율로 섞어 상온 내지 150 ℃ 온도에서 세정을 실시한다. 또한, NH4OH, H2O2및 H2O가 혼합된 SC-1 용액, HCl, H2O2및 H2O가 혼합된 SC-2 용액 또는 50:1로 희석된 HF 용액을 이용하여 묽은 습식식각 세정을 실시할 수도 있다.As shown in FIG. 4A, first, the native oxide film or impurities are removed on the semiconductor substrate 40 on which the substructure 41, such as a capacitor, is formed. In this case, in order to remove the natural oxide film or impurities, a buffered oxide etchant (BOE) solution having an ratio of an etchant and a buffer solution of 50: 1 or more is used, or an aqueous solution of H 2 SO 4 and H 2 O 2 is 2: 1 to 5: 1 volume. Mix in a ratio and wash at room temperature to 150 ℃ temperature. In addition, using SC-1 solution mixed with NH 4 OH, H 2 O 2 and H 2 O, SC-2 solution mixed with HCl, H 2 O 2 and H 2 O or HF solution diluted to 50: 1 Thin wet etching may be performed.
이어서, 화학기상증착(chemical vapor deposition, 이하 CVD라 함) 장치에서 일정 압력, 일정 온도 조건으로 수분의 침투를 억제하기 위한 제1 보호막(42)을 증착한다. 상기 제1 보호막(42)은 200 ℃ 내지 800 ℃ 온도, 1 mTorr 내지 700 Torr 압력에서 SiH4, TEOS(tetraethyl orthosilicate), O2, O3, N2O 등의 반응가스를 이용하여 100 Å 이상의 산화막으로 형성하거나, SiH4, N2, N2O, NH3가스를 이용하여 질화막 또는 질화산화막으로 형성한다.Subsequently, in the chemical vapor deposition (hereinafter referred to as CVD) apparatus, the first protective film 42 for suppressing the penetration of moisture at a constant pressure and a constant temperature condition is deposited. The first passivation layer 42 may be formed using a reaction gas such as SiH 4 , tetraethyl orthosilicate (TEOS), O 2 , O 3 , or N 2 O at a temperature of 200 ° C. to 800 ° C. and a pressure of 1 mTorr to 700 Torr. It is formed of an oxide film or a nitride film or an oxide nitride film using SiH 4 , N 2 , N 2 O, or NH 3 gas.
다음으로, 접착력 및 평탄화 향상을 위하여 N2O, H2O, H2O2, NH3또는 O2가스를 사용하여, 100 W 이상의 전력으로 200 ℃ 내지 500 ℃에서 10초 이상 플라즈마 처리를 실시한다.Next, plasma treatment is performed for 10 seconds or more at 200 ° C. to 500 ° C. with a power of 100 W or more using N 2 O, H 2 O, H 2 O 2 , NH 3 or O 2 gas to improve adhesion and planarization. do.
이어서, 자체 유동특성을 나타내는 SiH4, H2O2, H2O, O2의 반응소스를 이용하여 -10 ℃ 내지 50 ℃ 사이의 저온, 100 Torr 이하의 저압하에서 패턴 사이를 매립하는 언도프트(undoped) SiOxHy산화막(43)을 500 Å 이상의 두께로 형성하여 전체 단차를 완화시킨다. 자체 유동성을 갖는 SiOxHy산화막(43)의 특성상 셀블럭 위의 산화막이 흘러내리면서 전체 단차가 줄어들고 각도가 완만하게 되지만 패턴이 밀접한 셀블럭 영역의 절연막 두께는 디코더나 테스트 패턴 영역 보다 매우 높아진다.Subsequently, an undoped layer is embedded between the patterns at low temperatures of -10 ° C. to 50 ° C. and at a low pressure of 100 Torr or less using reaction sources of SiH 4 , H 2 O 2 , H 2 O, and O 2 exhibiting self-flow characteristics. An (undoped) SiO x H y oxide film 43 is formed to a thickness of 500 kPa or more to alleviate the overall step. Due to the characteristics of the SiO x H y oxide film 43 having self-flowability, as the oxide film on the cell block flows down, the overall step is reduced and the angle becomes smooth, but the thickness of the insulating film in the cell block region where the pattern is close is much higher than that of the decoder or test pattern region. .
SiOxHy산화막(43)은 막중에 다량의 수분을 함유하고 있기 때문에 후속 열공정시 부피 수축에 따라 SiOxHy산화막(43)이 깨어지는 것을 방지하고 치밀화시키기 위해 1차 열처리를 실시한다. 상기 1차 열처리는 200 ℃ 내지 500 ℃ 온도로 저압에서 10초 이상 열처리를 실시하거나, 100 Torr 이하의 압력에서 N2, N2O, NH3가스를 이용한 플라즈마로 10초 이상 실시할 수도 있고, 또한 O2, N2, O3, N2O 또는 H2와 O2의 혼합가스 분위기에서 300 ℃ 내지 850 ℃ 온도로 저압에서 5분 이상 실시할 수도 있다.Since the SiO x H y oxide film 43 contains a large amount of water in the film, a primary heat treatment is performed to prevent the SiO x H y oxide film 43 from breaking down due to volume shrinkage during subsequent thermal processes and to densify it. The first heat treatment may be performed for 10 seconds or more at low pressure at a temperature of 200 ℃ to 500 ℃, or 10 seconds or more with a plasma using N 2 , N 2 O, NH 3 gas at a pressure of 100 Torr or less, In addition, it may be performed at low pressure for 5 minutes or more at a temperature of 300 ° C. to 850 ° C. in a mixed gas atmosphere of O 2 , N 2 , O 3 , N 2 O or H 2 and O 2 .
상기 1차 열처리 후, SiH4, N2O, NH3, O2가스를 사용하여 200 ℃ 내지 500 ℃ 온도에서 플라즈마 방법으로 SiOxHy산화막(43) 상에 500 Å 이상 두께의 플라즈마 산화막을 제2 보호막(44)으로서 형성한다.After the first heat treatment, a plasma oxide film having a thickness of 500 kPa or more on the SiO x H y oxide film 43 by the plasma method at a temperature of 200 ℃ to 500 ℃ using SiH 4 , N 2 O, NH 3 , O 2 gas. It is formed as a second protective film 44.
이어서, 패턴 사이의 막질 치밀화와 후속 공정의 안정화를 위해 350 ℃ 내지 850 ℃에서 H2와 O2의 혼합가스, O2, N2,O3,N2O가스 또는 불활성 가스 분위기에서 2차 열처리를 실시한다.Subsequently, secondary heat treatment in a mixed gas of H 2 and O 2 , O 2 , N 2 , O 3 , N 2 O gas or an inert gas atmosphere at 350 ° C. to 850 ° C. for densification of film quality between patterns and stabilization of subsequent processes. Is carried out.
이후, 감광막을 도포, 노광 및 현상하여 셀블럭 영역(C)과 센스증폭기 영역(S/A)을 오픈하는 감광막 패턴(PR)을 형성한다.Thereafter, the photoresist layer is coated, exposed, and developed to form a photoresist pattern PR for opening the cell block region C and the sense amplifier region S / A.
다음으로, 도4b에 도시한 바와 같이 셀블럭 영역(C) 및 센스증폭기 영역(S/A)의 제2 보호막(44) 및 SiOxHy산화막(43) 일부를 건식 또는 습식식각하여 제거한다. 이때, 셀블럭 영역(C)과 센스 증폭기 영역(S/A)을 오픈한 상태에서 O2, CFxHy계열, NF3, SF6의 반응가스를 이용하여 플라즈마 방식으로 SiOxHy산화막을 제거하는 건식식각 방법을 이용하거나, 순수(Deionized water)와 HF를 일정 비율로 혼합한 식각용액 또는 NH4F 등의 완충제(buffering agent)를 섞은 BOE 용액을 이용하는 습식식각 방식으로 SiOxHy산화막을 제거한다.Next, as shown in FIG. 4B, a part of the second passivation layer 44 and the SiO x H y oxide layer 43 in the cell block region C and the sense amplifier region S / A are removed by dry or wet etching. . At this time, the SiO x H y oxide film is formed in a plasma manner using the reaction gas of O 2 , CF x H y series, NF 3 , SF 6 with the cell block region C and the sense amplifier region S / A open. SiO x H y using a dry etching method that removes or a wet etching method using a BOE solution mixed with a deionized water and HF in a ratio or a buffering agent such as NH 4 F. Remove the oxide film.
이어서, 상기 감광막 패턴을 제거한다. 이때, 감광막 패턴이 형성되었던 경계부 위의 첨점(A)이 첨점이 노출된다.Next, the photoresist pattern is removed. At this time, the peak point A on the boundary where the photoresist pattern is formed is exposed.
다음으로, 도4c에 도시한 바와 같이 짧은 시간 동안 CMP를 실시하는, 터치 CMP(touch CMP) 방법으로 첨점(A)을 제거한다.Next, as shown in Fig. 4C, the peak A is removed by the touch CMP method, which performs CMP for a short time.
이와 같은 과정에 따라, 전체 단차가 감소될 뿐만 아니라 센스 증폭기와 디코더 영역의 단차도 줄어들게 된다.This process not only reduces the overall step, but also reduces the step of the sense amplifier and decoder regions.
이후, 추가적인 보호막이나 콘택을 형성한 다음, 센스 증폭기 영역(S/A) 또는 디코더 영역(D) 등에 배선을 형성할 경우 이에 따라 셀블럭 영역(C)과 테스트 패턴 영역(T), 디코더 영역(D) 및 센스 증폭기 영역(S/A) 간에 다시 단차가 심하게 발생하는 것을 방지할 수 있다.Subsequently, when an additional passivation layer or contact is formed, and wiring is formed in the sense amplifier region S / A or the decoder region D, the cell block region C, the test pattern region T, and the decoder region ( It is possible to prevent a serious step again between D) and the sense amplifier region S / A.
도5a는 본 발명의 일실시에 따른 층간절연막 형성 후 테스트 패턴 영역과 셀블럭의 단차를 비교하여 보이는 그래프이고, 도5b는 본 발명의 일실시예에 따른 층간절연막 형성 후 디코더 영역과 셀블럭의 단차를 비교하여 보이는 그래프로서, 전술한 본 발명에 따라 저온, 저압 조건에서 SiOxHy산화막을 형성하여 패턴을 매립한 후 셀블럭 영역과 S/A 영역을 오픈한 후 SiOxHy산화막을 3000 Å 정도 제거한 경우, SiOxHy산화막 형성 전후의 단차를 비교하여 나타내고 있다. 도5a 및 도5b의 결과로부터 SiOxHy산화막 형성 후 셀블럭의 영역은 6000 Å의 단차를 갖게되고, 센스 증폭기 영역, 디코더 영역, 테스트 패턴 영역에는 단차가 발생하지 않는 것을 알 수 있다.5A is a graph illustrating a comparison between a test pattern region and a cell block after forming an interlayer dielectric layer according to an embodiment of the present invention, and FIG. 5B illustrates a decoder region and cell block after an interlayer dielectric layer is formed according to an embodiment of the present invention. a graph illustrating by comparing the level difference, by opening the low temperature, SiO x H y after forming an oxide film buried patterns cell block area and the S / a region in a low-pressure condition in accordance with the present invention described above after the SiO x H y oxide when approximately 3000 Å removed, there is shown by comparing the level difference before and after the SiO x H y oxide film formation. It can be seen from the results of FIGS. 5A and 5B that after the SiO x H y oxide film formation, the cell block region has a step of 6000 mW, and no step occurs in the sense amplifier region, the decoder region, and the test pattern region.
셀블럭과 다른 영역간 발생하는 단차는 후속 금속공정에서 셀블럭을 제외하고 배선이 형성되기 때문에 공정을 진행하면서 전체적으로는 완전한 평탄화가 이루어지는 층간절연막을 형성할 수 있다.The step difference generated between the cell block and other regions is formed in the subsequent metal process except for the cell block, so that the interlayer insulating film can be formed as a whole during the process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 패턴 사이에 단차가 있는 패턴 사이에 층간절연막을 평탄하게 형성함으로써 단차 감소에 따라 후속 공정 여유도를 증가시킬 수 있다.According to the present invention as described above, by forming the interlayer insulating film evenly between the patterns having the step difference between the patterns, the subsequent process margin can be increased as the step difference is reduced.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100547243B1 (en) * | 1999-12-17 | 2006-02-01 | 주식회사 하이닉스반도체 | Method for manufacturing inter-dielectric layer in semiconductor device |
| CN110349855A (en) * | 2018-04-03 | 2019-10-18 | 华邦电子股份有限公司 | The manufacturing method of semiconductor device |
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| KR100547243B1 (en) * | 1999-12-17 | 2006-02-01 | 주식회사 하이닉스반도체 | Method for manufacturing inter-dielectric layer in semiconductor device |
| CN110349855A (en) * | 2018-04-03 | 2019-10-18 | 华邦电子股份有限公司 | The manufacturing method of semiconductor device |
| CN110349855B (en) * | 2018-04-03 | 2021-11-26 | 华邦电子股份有限公司 | Method for manufacturing semiconductor device |
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