KR100242385B1 - Method of forming an element isolation region in a semiconductor device - Google Patents

Method of forming an element isolation region in a semiconductor device Download PDF

Info

Publication number
KR100242385B1
KR100242385B1 KR1019970033067A KR19970033067A KR100242385B1 KR 100242385 B1 KR100242385 B1 KR 100242385B1 KR 1019970033067 A KR1019970033067 A KR 1019970033067A KR 19970033067 A KR19970033067 A KR 19970033067A KR 100242385 B1 KR100242385 B1 KR 100242385B1
Authority
KR
South Korea
Prior art keywords
trench
forming
device isolation
insulating layer
semiconductor substrate
Prior art date
Application number
KR1019970033067A
Other languages
Korean (ko)
Other versions
KR19990010307A (en
Inventor
이창재
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970033067A priority Critical patent/KR100242385B1/en
Publication of KR19990010307A publication Critical patent/KR19990010307A/en
Application granted granted Critical
Publication of KR100242385B1 publication Critical patent/KR100242385B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체장치의 소자격리방법에 관한 것으로서 반도체기판 상의 소정 부분을 덮는 마스크층을 형성하여 소자격리영역과 활성영역을 한정하는 공정과, 상기 반도체기판의 소자격리영역을 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내에 확산방지층을 형성하는 공정과, 상기 마스크층 상에 상기 트렌치를 채우도록 USG(Undopd Silicate Glass)를 저온에서 증착하고 고온에서 열처리한 후 상기 마스크층이 노출되도록 에치백하여 필드산화막을 형성하는 공정을 구비한다. 따라서, 작은 트렌치 내의 절연층에 경계면이 형성되어 있지 않으므로 에치백 또는 세정 공정시 과도 시각되지 않으므로 이 후에 게이트 형성시 필드산화막 상에 도전성 물질이 잔류되는 것을 방지할 수 있다.The present invention relates to a device isolation method of a semiconductor device, comprising: forming a mask layer covering a predetermined portion on a semiconductor substrate to define a device isolation region and an active region; and etching a device isolation region of the semiconductor substrate to form a trench. Forming a diffusion barrier layer in the trench, depositing an undoped silica glass (USG) at a low temperature to heat the trench on the mask layer, and heat treating at a high temperature, and then etching back to expose the mask layer. A step of forming an oxide film is provided. Therefore, since the interface is not formed in the insulating layer in the small trench, it is not over-visible during the etch back or cleaning process, so that the conductive material can be prevented from remaining on the field oxide film during the gate formation.

Description

반도체장치의 소자격리방법Device isolation method of semiconductor device

본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 트렌치(trench)를 이용한 반도체장치의 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor device, and more particularly, to a device isolation method for a semiconductor device using a trench.

반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자 격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, the development of technology to reduce the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자 격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, the development of technology to reduce the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

일반적으로 바도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 격리하였다. LOCOS 방법은 활성영역을 한정하는 산화마스크인 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 패드화막(pad oxide)을 형성하고 산화시켜 소자격리영역으로 이용되는 필드산화막을 형성한다. 상기에서 필드산화막은 반도체기판의 수직 방향으로 성장할 뿐만 아니라 산화체(Oxidant : 02)가 패드산화막을 따라 수평 방향으로도 확산되므로 질화막의 패턴 엣지(edage) 밑으로 성장되게 되는 특징을 갖는다.In general, the semiconductor device is used to isolate the device by LOCOS (Local Oxidation of Silicon) method. The LOCOS method is a device isolation region by forming and oxidizing a pad oxide film between the nitride film and the semiconductor substrate in order to solve the stress caused by the different thermal properties of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed. The field oxide film is grown not only in the vertical direction of the semiconductor substrate but also in the oxidizer (Oxidant: 0 2 ) in the horizontal direction along the pad oxide film, so that the field oxide film is grown under the pattern edge of the nitride film.

이와같이 필드산화막이 활성 영역을 잠식하는 현상을 그 형상이 새의 부리 모양과 유사하여 버즈 비크(Bird's Beak)이라 한다. 이러한 버드 비크의 길이는 필드 산화막 두께의 1/2이나 된다. 그러므로, 활성 영역의 크기기가 감소되는 것을 줄이기 위하여는 버즈 비크의 길이를 최소화 하여야 한다.The phenomenon in which the field oxide film encroaches on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. The length of such bird beak is half the thickness of the field oxide film. Therefore, in order to reduce the size reduction of the active region, the length of the buzz beak should be minimized.

버즈 비크의 길이를 줄이기 위한 방법으로 필드산화막의 두께를 감소시키는 방식이 도입되었으나 16M DRAM급 이상에서 필드산화막의 두께를 감소시키면 배선과 반도체기판 사이의 정전 용량이 증가되어 신호전달 속도가 저하되는 문제가 발생된다. 또한, 소자의 게이트로 사용되는 배선에 의해 소자 사이의 격리영역에 형성되는 기생 트랜지스터의 문턱전압(Vt)이 저하되어 소자 사이의 격리특성이 저하되는 문제점이 있다.In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate increases and the signal transmission speed decreases. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.

따라서, 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법이 개발되었다. 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법으로는 스트레스 완충용 패드산화막의 두께를 낮추고 반도체기판과 질화막 사이에 다결정실리콘층을 개입시킨 PBLOCOS(Poly Si Buffered LOCOS), 패드산화막의 측벽을 질화막으로 보호하는 SILO(Sealed Interface LOCOS), 그리고, 반도체기판 내에 필드산화막을 형성시키는 리세스(Recessed) LOCOS 기술들이 있다.Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the pad buffer oxide film is reduced and the polysilicon buffered polysilicon layer (PBLOCOS) between the semiconductor substrate and the nitride film and the sidewall of the pad oxide film are nitrided. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.

그러나, 상기 기술들은 격리 영역 표면의 평탄도와 정밀한 디자인 룰(Design Rule) 등의 이유로 256M DRAM급 이상의 집적도를 갖는 차세대 소자의 소자격리기술로 적합하지 않게 되었다.However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.

따라서, 기존의 여러 소자격리기술들의 문제점을 극복할 수 있는 BOX (buride oxide)형 트렌치 소자분리 (trench isolation) 기술이 개발되었다. BOX형 소자격리 기술 반도체기판에 트렌치를 형성하고 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 불순물이 도핑되지 않은 다결정실리콘을 매립한 구조를 갖는다. 그러므로, 버즈 비크가 발생되지 않아 활성영역의 손실이 전혀 없으며, 또한, 산화막을 메립하고 에치 백(etch back)하여 평탄한 표면을 얻을 수 있다.Therefore, a BOX (buride oxide) trench trench isolation technology has been developed to overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed in a semiconductor substrate and has a structure in which silicon oxide or polycrystalline silicon which is not doped with impurities is embedded by chemical vapor deposition (hereinafter referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

도 1a 내지 도 1c는 종래 기술에 따른 소자격리방법을 도시하는 공정도이다.1A to 1C are process diagrams illustrating a device isolation method according to the prior art.

도 1a를 참조하면, 반도체기판(11) 상에 열산화 방법으로 버퍼산화막(13)을 형성하고, 이 버퍼산화막(13) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(15)을 형성한다. 그리고, 포토리쏘그래피(photolithography) 방법으로 반도체기판(11)의 소자격리영역이 노출되도록 마스크층(15) 및 버퍼산화막(13)을 선택적으로 제거하여 소자격리영역과 활성영역을 한정한다.Referring to FIG. 1A, a buffer oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 13. Silicon nitride is deposited to form a mask layer 15. The device isolation region and the active region are defined by selectively removing the mask layer 15 and the buffer oxide layer 13 so that the device isolation region of the semiconductor substrate 11 is exposed by photolithography.

도 1b를 참조하면, 반도체기판(11)의 노출된 소자격리영역을 건식 식각 방법으로 소정 깊이로 식각하여 트렌치(17)를 형성한다. 그리고, 상술한 구조의 전 표면에 산화실리콘을 CVD 방법으로 트렌치(17)가 채워지도록 증착하여 절연층(19)을 형성한다. 이때, 작은 영역의 트렌치(17)에서 절연층(19)의 측면으로부터 각각 증착되므로 표면이 접촉하게 되어 경계면(seam)이 나타나게 된다. 또한, 절연층(19)은 넓은 영역의 트렌치(17)에서 표면을 따라 증착되므로 오목하게 형성된다. 그리고, 절연층(19)의 표면에 감광막 또는 SOG(Spin On Glass) 등을 도포하여 평탄화층(21)을 형성한다.Referring to FIG. 1B, the trench 17 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth by a dry etching method. Then, silicon oxide is deposited on the entire surface of the structure described above to fill the trench 17 by CVD to form an insulating layer 19. At this time, since the trench 17 in the small region is deposited from the side surface of the insulating layer 19, the surfaces are in contact with each other, and a boundary surface appears. In addition, the insulating layer 19 is formed concave since it is deposited along the surface in the trench 17 in a wide area. The planarization layer 21 is formed by applying a photosensitive film or SOG (Spin On Glass) to the surface of the insulating layer 19.

도 1c를 참조하면 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법이나 화학-기계적연마(Chemical Mechanical Polishing : 이하, CMP라 칭함) 방법으로 평탄화층(21)과 절연층(19)의 식각 속도가 같도록 에치 백한다. 이 때, 트렌치(17) 내에 잔류하는 절연층(19)은 필드산화막이 된다. 그리고, 마스크층(15) 및 패드산화막(13)을 순차적으로 제거하여 반도체기판(11)의 활성영역을 노출시킨다.Referring to FIG. 1C, the planarization layer 21 and the insulating layer 19 may be formed by a reactive ion etching (hereinafter referred to as RIE) method or a chemical mechanical polishing (hereinafter referred to as CMP) method. Etch back so that the etching speed is the same. At this time, the insulating layer 19 remaining in the trench 17 becomes a field oxide film. The mask layer 15 and the pad oxide film 13 are sequentially removed to expose the active region of the semiconductor substrate 11.

그러나, 상술한 종래의 반도체장치의 소자격리방법은 에치 백 또는 세정 공정시 작은 트렌치 내의 절연층에 형성된 경계면을 따라 쉽게 손상되어 홈이 형성되는데, 이러한 홈은 이 후 공정인 게이트 형성시 도전성 물질이 잔류하게 되는 문제점이 있었다.However, the device isolation method of the conventional semiconductor device described above is easily damaged along the interface formed in the insulating layer in the small trench during the etch back or cleaning process to form a groove, which is a conductive material in the subsequent gate formation. There was a problem of remaining.

따라서, 본 발명의 목적은 게이트 형성시 필드산화막 상에 도전성 물질이 잔류되는 것을 방지할 수 있는 반도체장치의 소자격리방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a device isolation method for a semiconductor device which can prevent the conductive material from remaining on the field oxide film during the gate formation.

상기 목적을 달성하기 위해 본 발명에 따른 반도체장치의 소자격리방법은 반도체기판 상의 소정 부분을 덮는 마스크층을 형성하여 소자격리영역과 활성영역을 한정하는 공정과, 상기 반도체기판의 소자격리영역을 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내에 확산방지층을 형성하는 공정과, 상기 마스크층 상에 상기 트렌치를 채우도록 USG(Undopd Silicate Glass)를 저온에서 증착하고 고온에서 열처리한 후 상기 마스크층이 노출되도록 에치백하여 필드산화막을 형성하는 공정을 구비한다.In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes forming a mask layer covering a predetermined portion on a semiconductor substrate to define a device isolation region and an active region, and etching the device isolation region of the semiconductor substrate. Forming trenches, forming a diffusion barrier layer in the trenches, and depositing Undopd Silicate Glass (USG) at low temperature and heat-treating at high temperature to fill the trenches on the mask layer, and then exposing the mask layer. And forming a field oxide film by etching back as much as possible.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 1a도 내지 제 1c도는 종래 기술에 따른 반도체장치의 소자격리방법을 도시하는 공정도.1A to 1C are process diagrams showing a device isolation method for a semiconductor device according to the prior art.

제 2a도 내지 제 2d도는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정도2A to 2D are process drawings showing a device isolation method for a semiconductor device according to the present invention.

도 2a 내지 도 2도는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정도이다.2A to 2 are process charts showing the device isolation method of the semiconductor device according to the present invention.

도 2a를 참조하면, 반도체기판(31) 상에 열산화 방법에 의해 버퍼산화막(33)을 형성하고, 이 버퍼산화막(33) 상에 CVD 방법에 의해 질화실리콘을 증착하여 마스크층(35)을 형성한다. 그리고, 마스크층(35) 및 버퍼산화막(33)을 반도체기판(31)의 소자격리영역이 노출되도록 포토리쏘그래피 방법으로 패터닝하여 소자격리영역과 활성영역을 한정한다.Referring to FIG. 2A, a buffer oxide film 33 is formed on a semiconductor substrate 31 by a thermal oxidation method, and silicon nitride is deposited on the buffer oxide film 33 by a CVD method to form a mask layer 35. Form. The mask layer 35 and the buffer oxide film 33 are patterned by photolithography to expose the device isolation region of the semiconductor substrate 31 to define the device isolation region and the active region.

도 2b를 참조하면, 반도체기판(31)의 노출된 소자격리영역을 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 등의 이방성 식각 방법으로 소정 깊이로 식각하여 트렌치(37)를 형성한다. 이 때, 반도체기판(31)의 활성영역은 마스크층(35)에 의해 식각되지 않는다. 그리고, N2O, NO 또는 NO2등의 질소(N2)와 산소(O2)가 함유된 화합물 가스나, NH3와 O2의 혼합 가스 상태에서 열을 가하여 트렌치(37) 내부 표면에 질화실리콘막(Si3N4) 또는 산화질화실리콘막(SiOXNY)을 성장시켜 확산방지층(39)을 형성한다. 또한, 확산방지층(39)을 CVD 방법으로 질화실리콘막(Si3N4) 또는 산화질화실리콘막(SiOXNY)을 증착하여 형성할 수 있다.Referring to FIG. 2B, the trench 37 is formed by etching the exposed device isolation region of the semiconductor substrate 31 to a predetermined depth by an anisotropic etching method such as reactive ion etching (hereinafter referred to as RIE). . At this time, the active region of the semiconductor substrate 31 is not etched by the mask layer 35. Then, heat is applied to the inner surface of the trench 37 by applying heat in a compound gas containing nitrogen (N 2 ) and oxygen (O 2 ) such as N 2 O, NO or NO 2 , or a mixed gas of NH 3 and O 2 . A diffusion barrier layer 39 is formed by growing a silicon nitride film (Si 3 N 4 ) or a silicon oxynitride film (SiO X N Y ). In addition, the diffusion barrier layer 39 may be formed by depositing a silicon nitride film (Si 3 N 4 ) or a silicon oxynitride film (SiO X N Y ) by a CVD method.

도 2c를 참조하면, 마스크층(35) 상에 트렌치(37)를 채우도록 USG(Undopd Silicate Glass)를 증착하여 절연층(41)을 형성한다. 상기에서 절연층(41)은 O3와 TEOS(tetraethyl orthosilicate)를 상압에서 350∼450℃의 온도로 반응시켜 USG를 증착한 후, 증착된 USG를 H2/O2분위기에서 750∼850℃의 온도로 1∼5시간 동안 열처리하여 조밀화(densification)시킨다. 이 때, 절연층(41)을 이루는 USG가 유동성이 양호하므로 증착시 표면에서 흐름이 발생되므로 표면이 평탄해지며 작은 영역의 트렌치(37)에서 절연층(41) 내에 경계면이 형성되는 것을 방지할 수 있다. 또한, 절연층(41) 내에 함유된 불순물은 열처리시 확산되어 대부분 반도체기판(31)의 외부로 배출되어 절연층(41) 내에 잔류 량이 감소된다. 이 때, 불순물은 고온에서 장시간 동안 열처리하므로 반도체기판(31) 쪽으로도 확산되는 데, 확산방지층(39)은 불순물이 반도체기판(31) 내로 확산되는 것을 방지한다.Referring to FIG. 2C, an insulating layer 41 is formed by depositing USG (Undopd Silicate Glass) to fill the trench 37 on the mask layer 35. In the insulating layer 41 is reacted with O 3 and TEOS (tetraethyl orthosilicate) at a temperature of 350 ~ 450 ℃ at atmospheric pressure to deposit USG, the deposited USG in H 2 / O 2 atmosphere of 750 ~ 850 ℃ Densification is performed by heat treatment at a temperature of 1 to 5 hours. At this time, since the USG constituting the insulating layer 41 has good fluidity, flow is generated at the surface during deposition, so that the surface becomes flat and the formation of an interface in the insulating layer 41 in the trench 37 in a small area is prevented. Can be. In addition, impurities contained in the insulating layer 41 are diffused during the heat treatment, and are mostly discharged to the outside of the semiconductor substrate 31 to reduce the residual amount in the insulating layer 41. At this time, since the impurities are heat-treated at a high temperature for a long time, they are also diffused toward the semiconductor substrate 31. The diffusion barrier layer 39 prevents the impurities from diffusing into the semiconductor substrate 31.

도 2d를 참조하면, 절연층(41)을 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법이나 화학-기계적연마(Chemical Mechanical Polishing : 이하, CMP라 칭함) 방법으로 마스크층(35)이 노출되도록 에치 백한다. 상기에서 트렌치(37)내에 잔류하는 절연층(41)은 필드산화막이 된다. 이 때, 작은 트렌치(37)내의 절연층(41)에 경계면이 형성되어 있지 않으므로 홈이 형성되는 것이 방지된다. 그리고, 마스크층(35) 및 버퍼산화막(33)을 순차적으로 제거하여 반도체기판(31)의 활성영역을 노출시킨다.Referring to FIG. 2D, the mask layer 35 may be formed by the method of reactive ion etching (hereinafter referred to as RIE) or chemical mechanical polishing (hereinafter referred to as CMP). Etch back so that it is exposed. In the above, the insulating layer 41 remaining in the trench 37 becomes a field oxide film. At this time, since no interface is formed in the insulating layer 41 in the small trench 37, the formation of grooves is prevented. The mask layer 35 and the buffer oxide film 33 are sequentially removed to expose the active region of the semiconductor substrate 31.

따라서, 본 발명은 작은 트렌치 내의 절연층에 경계면이 형성되어 있지 않으므로 에치백 또는 세정 공정시 과도 식각되지 않으므로 이 후에 게이트 형성시 필드 산화막 상에 도전성 물질이 잔류되는 것을 방지할 수 있는 잇점이 있다.Therefore, the present invention is advantageous in that the conductive material is not prevented from remaining on the field oxide layer during the gate formation since the interface is not formed in the insulating layer in the small trench and thus is not excessively etched during the etch back or cleaning process.

Claims (6)

반도체기판 상의 소정 부분을 덮는 마스크층을 형성하여 소자격리영역과 활성영역을 한정하는 공정과,Forming a mask layer covering a predetermined portion on the semiconductor substrate to define the device isolation region and the active region; 상기 반도체기판의 소자격리영역을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the device isolation region of the semiconductor substrate; 상기 트렌치 내에 확산방지층을 형성하는 공정과,Forming a diffusion barrier layer in the trench; 상기 마스크층 상에 상기 트렌치를 채우도록 USG(Undopd Silicate Glass)를 저온에서 증착하여 절연층을 형성하는 공정과,Forming an insulating layer by depositing Undopd Silicate Glass (USG) at a low temperature to fill the trench on the mask layer; 상기 절연층을 고온에서 열처리하는 공정과,Heat-treating the insulating layer at a high temperature; 상기 마스크층이 노출되도록 상기 절연층을 에치백하여 필드산화막을 형성하는 공정을 구비하는 반도체장치의 소자격리방법Forming a field oxide film by etching back the insulating layer so that the mask layer is exposed. 청구항 1에 있어서,The method according to claim 1, 상기 확산방지층을 질화실리콘막(Si3N4) 또는 산화질화실리콘막(SiOXNY)으로 형성하는 반도체장치의 소자격리방법.A method for isolating a semiconductor device, wherein the diffusion barrier layer is formed of a silicon nitride film (Si 3 N 4 ) or a silicon oxynitride film (SiO X N Y ). 청구항 2에 있어서,The method according to claim 2, 상기 확산방지층을 N2O, NO 또는 NO2의 화합물 가스 상태에서, 또는, NH3와 O2의 혼합 가스 상태에서 열을 가하여 형성하는 반도체장치의 소자격리방법.And the diffusion barrier layer is formed by applying heat in a compound gas state of N 2 O, NO, or NO 2 or in a mixed gas state of NH 3 and O 2 . 청구항 2에 있어서,The method according to claim 2, 상기 확산방지층을 질화실리콘막(Si3N4) 또는 산화질화실리콘막(SiOXNY)을 CVD방법으로 증착하여 형성하는 반도체장치의 소자격리방법.And the diffusion barrier layer is formed by depositing a silicon nitride film (Si 3 N 4 ) or a silicon oxynitride film (SiO X N Y ) by a CVD method. 청구항 1에 있어서,The method according to claim 1, 상기 절연층을 O3와 TEOS(tetraethyl orthosilicate)를 상압에서 350∼450℃의 온도로 반응시켜 형성하는 반도체장치의 소자격리방법.The insulating layer is formed by reacting O 3 and TEOS (tetraethyl orthosilicate) at a temperature of 350 ~ 450 ℃ at normal pressure. 청구항 5에 있어서,The method according to claim 5, 상기 절연층을 H2/O2분위기에서 750∼850℃의 온도로 1∼5시간 열처리하는 반도체장치의 소자격리방법.A method for isolating a semiconductor device, in which the insulating layer is heat-treated at a temperature of 750 to 850 캜 for 1 to 5 hours in an H 2 / O 2 atmosphere.
KR1019970033067A 1997-07-16 1997-07-16 Method of forming an element isolation region in a semiconductor device KR100242385B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970033067A KR100242385B1 (en) 1997-07-16 1997-07-16 Method of forming an element isolation region in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970033067A KR100242385B1 (en) 1997-07-16 1997-07-16 Method of forming an element isolation region in a semiconductor device

Publications (2)

Publication Number Publication Date
KR19990010307A KR19990010307A (en) 1999-02-18
KR100242385B1 true KR100242385B1 (en) 2000-03-02

Family

ID=19514629

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970033067A KR100242385B1 (en) 1997-07-16 1997-07-16 Method of forming an element isolation region in a semiconductor device

Country Status (1)

Country Link
KR (1) KR100242385B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100564988B1 (en) * 1999-12-22 2006-03-28 주식회사 하이닉스반도체 Method of forming a shallow trench isolation film in a semiconductor device
KR100671155B1 (en) * 2001-06-26 2007-01-17 매그나칩 반도체 유한회사 Method for manufacturing an isolation layer in a semiconductor device
KR100461330B1 (en) * 2002-07-19 2004-12-14 주식회사 하이닉스반도체 Method for forming Shallow Trench Isolation of semiconductor device
KR100753104B1 (en) * 2006-06-29 2007-08-31 주식회사 하이닉스반도체 Method for manufacturing isolation in semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142432A (en) * 1991-11-29 1995-06-02 Sony Corp Fabrication of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142432A (en) * 1991-11-29 1995-06-02 Sony Corp Fabrication of semiconductor device

Also Published As

Publication number Publication date
KR19990010307A (en) 1999-02-18

Similar Documents

Publication Publication Date Title
KR100280107B1 (en) How to form trench isolation
US6069057A (en) Method for fabricating trench-isolation structure
US6110800A (en) Method for fabricating a trench isolation
KR100243302B1 (en) Trench isolation method of semiconductor device
US6544861B2 (en) Method for forming isolation trench
KR20000013397A (en) Manufacturing method of trench isolation
KR100242385B1 (en) Method of forming an element isolation region in a semiconductor device
KR100568259B1 (en) Trench isolation type semiconductor device and fabrication method for the same
KR100226501B1 (en) Method of forming a device isolation film of semiconductor device
KR100242526B1 (en) Method for isolating semiconductor device
KR100492790B1 (en) Device isolation insulating film formation method of semiconductor device
KR100226500B1 (en) Isolation method in semiconductor device
KR100344765B1 (en) Method for isolating semiconductor devices
KR19990010247A (en) Device isolation method of semiconductor device
KR20000015298A (en) Isolation method of semiconductor device
KR100246198B1 (en) Method for isolating semiconductor device
KR100474588B1 (en) Device isolation method of semiconductor device
KR19990070373A (en) Device isolation method of semiconductor device
KR19990038190A (en) Device isolation method of semiconductor device
KR100361520B1 (en) A method of device isolation in semiconductor device
KR19990048786A (en) Method of forming device isolation film of semiconductor device
KR100242523B1 (en) Method for isolating semiconductor device
KR19990039742A (en) Device isolation method of semiconductor device
KR19990000764A (en) Device isolation method of semiconductor device
KR20000019068A (en) Method for isolating semiconductor devices

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20071025

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee