KR19990038190A - Device isolation method of semiconductor device - Google Patents
Device isolation method of semiconductor device Download PDFInfo
- Publication number
- KR19990038190A KR19990038190A KR1019970057842A KR19970057842A KR19990038190A KR 19990038190 A KR19990038190 A KR 19990038190A KR 1019970057842 A KR1019970057842 A KR 1019970057842A KR 19970057842 A KR19970057842 A KR 19970057842A KR 19990038190 A KR19990038190 A KR 19990038190A
- Authority
- KR
- South Korea
- Prior art keywords
- gas
- trench
- oxide film
- forming
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
Landscapes
- Element Separation (AREA)
Abstract
본 발명은 반도체장치의 소자격리방법에 관한 것으로서 반도체기판 상에 버퍼산화막 및 식각정지층을 형성하고 상기 마스크층 상에 소정 부분을 노출시키는 포토레지스트 패턴을 형성하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 반도체기판이 노출되도록 식각정지층과 버퍼산화막을 패터닝하여 소자격리영역과 활성영역을 한정하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 반도체기판의 소자격리영역을 이방성 식각 특성을 갖는 가스와 등방성 식각 특성을 갖는 가스를 혼합량을 변화시키면서 다 단계 식각하여 항아리 형상의 트렌치를 형성하는 공정과, 상기 포토레지스트 패턴을 제거하고 상기 트렌치 내에 필드산화막을 형성하는 공정을 구비한다. 따라서, 트렌치를 깊게 형성하지 않고도 소자들을 효과적으로 격리할 수 있다.The present invention relates to a device isolation method of a semiconductor device, comprising: forming a buffer oxide film and an etch stop layer on a semiconductor substrate and forming a photoresist pattern exposing a predetermined portion on the mask layer; Patterning the etch stop layer and the buffer oxide layer to expose the semiconductor substrate using the photoresist layer to define the device isolation region and the active region, and anisotropic etching characteristics of the device isolation region of the semiconductor substrate using the photoresist pattern as a mask. And forming a jar-shaped trench by multi-step etching the gas having an isotropic etching property and the gas having an isotropic etching characteristic, and removing the photoresist pattern and forming a field oxide film in the trench. Thus, it is possible to effectively isolate devices without deeply forming trenches.
Description
본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 트렌치(trench)를 이용한 반도체장치의 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor device, and more particularly, to a device isolation method for a semiconductor device using a trench.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.
일반적으로 반도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 격리하였다. LOCOS 방법은 활성영역을 한정하는 산화마스크인 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 패드산화막(pad oxide)을 형성하고 산화시켜 소자격리영역으로 이용되는 필드산화막를 형성한다. 상기에서 필드산화막은 반도체기판의 수직 방향으로 성장할 뿐만 아니라 산화체(Oxidant : 02)가 패드산화막을 따라 수평 방향으로도 확산되므로 질화막의 패턴 엣지(edage)밑으로 성장되게 되는 특징을 갖는다.In general, semiconductor devices have isolated devices by a local oxide of silicon (LOCOS) method. The LOCOS method is a device isolation region by forming and oxidizing a pad oxide film between the nitride film and the semiconductor substrate in order to solve the stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed. The field oxide film is grown not only in the vertical direction of the semiconductor substrate but also in the oxidizer (Oxidant: 0 2 ) in the horizontal direction along the pad oxide film, so that the field oxide film is grown under the pattern edge of the nitride film.
이와같이 필드산화막이 활성 영역을 잠식하는 현상을 그 형상이 새의 부리 모양과 유사하여 버즈 비크(Bird's Beak)이라 한다. 이러한 버드 비크의 길이는 필드산화막 두께의 1/2이나 된다. 그러므로, 활성 영역의 크기가 감소되는 것을 줄이기 위하여는 버즈 비크의 길이를 최소화 하여야 한다.The phenomenon in which the field oxide film encroaches on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This bird beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized to reduce the size of the active area.
버즈 비크의 길이를 줄이기 위한 방법으로 필드산화막의 두께를 감소시키는 방식이 도입되었으나 16M DRAM급 이상에서 필드산화막의 두께를 감소시키면 배선과 반도체기판 사이의 정전 용량이 증가되어 신호전달 속도가 저하되는 문제가 발생된다. 또한, 소자의 게이트로 사용되는 배선에 의해 소자 사이의 격리영역에 형성되는 기생 트랜지스터의 문턱전압(Vt)이 저하되어 소자 사이의 격리특성이 저하되는 문제점이 있다.In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate increases and the signal transmission speed decreases. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.
따라서, 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법이 개발되었다. 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법으로는 스트레스 완충용 패드산화막의 두께를 낮추고 반도체기판과 질화막 사이에 다결정실리콘층을 개입시킨 PBLOCOS(Poly Si Buffered LOCOS), 패드산화막의 측벽을 질화막으로 보호하는 SILO(Sealed Interface LOCOS), 그리고, 반도체기판 내에 필드산화막을 형성시키는 리세스(Recessed) LOCOS 기술들이 있다.Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the pad buffer oxide film is reduced and the polysilicon buffered polysilicon layer (PBLOCOS) between the semiconductor substrate and the nitride film and the sidewall of the pad oxide film are nitrided. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.
그러나, 상기 기술들은 격리 영역 표면의 평탄도와 정밀한 디자인 룰(Design Rule) 등의 이유로 256M DRAM급 이상의 집적도를 갖는 차세대 소자의 소자격리기술로 적합하지 않게 되었다.However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.
따라서, 기존의 여러 소자격리기술들의 문제점을 극복할 수 있는 BOX (buried oxide)형 트렌치 소자분리(trench isolation) 기술이 개발되었다. BOX형 소자격리기술 반도체기판에 트렌치를 형성하고 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 불순물이 도핑되지 않은 다결정실리콘을 매립한 구조를 갖는다. 그러므로, 버즈 비크가 발생되지 않아 활성영역의 손실이 전혀 없으며, 또한, 산화막을 메립하고 에치 백(etch back)하여 평탄한 표면을 얻을 수 있다.Therefore, a buried oxide (BOX) trench trench isolation technology has been developed to overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed on a semiconductor substrate and has a structure in which silicon oxide or polycrystalline silicon which is not doped with impurities is embedded by chemical vapor deposition (hereinafter referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.
도 1a 내지 도 1d는 종래 기술에 따른 소자격리방법을 도시하는 공정도이다.1A to 1D are process diagrams illustrating a device isolation method according to the prior art.
도 1a를 참조하면, 반도체기판(11) 상에 열산화 방법으로 버퍼산화막(13)을 형성하고, 이 버퍼산화막(13) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 식각정지층(15)을 형성한다. 그리고, 식각정지층(15) 상에 포토레지스트를 도포한 후 노광 및 현상하여 포토레지스트 패턴(16)을 형성한다. 그 다음, 포토레지스트 패턴(16)을 마스크로 사용하여 반도체기판(11)의 소정 부분이 노출되도록 식각정지층(15) 및 버퍼산화막(13)을 선택적으로 제거하여 소자격리영역과 활성영역을 한정한다.Referring to FIG. 1A, a buffer oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 13. Silicon nitride is deposited to form an etch stop layer 15. The photoresist is applied on the etch stop layer 15, and then exposed and developed to form the photoresist pattern 16. Next, using the photoresist pattern 16 as a mask, the etch stop layer 15 and the buffer oxide film 13 are selectively removed so that a predetermined portion of the semiconductor substrate 11 is exposed to define the device isolation region and the active region. do.
도 1b를 참조하면, 포토레지스트 패턴(16)을 마스크로 사용하여 반도체기판(11)의 노출된 소자격리영역을 건식 식각 방법으로 소정 깊이로 식각하여 트렌치(17)를 형성한다.Referring to FIG. 1B, the trench 17 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth by using the photoresist pattern 16 as a mask.
도 1c를 참조하면, 포토레지스트 패턴(16)을 제거한다. 그리고, 식각정지층(15) 상에 트렌치(17)가 채워지도록 산화실리콘을 CVD 방법으로 증착한다. 그리고, 산화실리콘을 식각정지층(15)이 노출되도록 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법이나 화학-기계적연마(Chemical Mechanical Polishing : 이하, CMP라 칭함) 방법으로 제거한다. 이 때, 산화실리콘이 트렌치(27) 내에 잔류하게 되어 필드산화막(19)이 된다.Referring to FIG. 1C, the photoresist pattern 16 is removed. Then, silicon oxide is deposited by CVD to fill the trench 17 on the etch stop layer 15. Then, the silicon oxide is removed by reactive ion etching (hereinafter referred to as RIE) method or chemical mechanical polishing (hereinafter referred to as CMP) method so that the etching stop layer 15 is exposed. At this time, silicon oxide remains in the trench 27 to form the field oxide film 19.
도 1d를 참조하면, 식각정지층(15)과 버퍼산화막(13)을 습식 식각 방법으로 제거하여 반도체기판(11)의 활성영역을 노출시킨다. 상기에서 필드산화막(19)의 반도체기판(11) 보다 높은 부분은 버퍼산화막(13) 제거시, 또는, 식각정지층(15)과 버퍼산화막(13) 제거 후 세정 공정시에 제거되어 반도체기판(11)과 평탄하게 된다.Referring to FIG. 1D, the etch stop layer 15 and the buffer oxide layer 13 are removed by a wet etching method to expose the active region of the semiconductor substrate 11. The portion higher than the semiconductor substrate 11 of the field oxide film 19 is removed when the buffer oxide film 13 is removed or during the cleaning process after the etching stop layer 15 and the buffer oxide film 13 are removed. 11) and become flat.
그러나, 상술한 종래의 반도체장치의 소자격리방법은 소자들을 효과적으로 격리하기 위해 트렌치를 깊게 형성하여야 하는 문제점이 있었다.However, the device isolation method of the conventional semiconductor device described above has a problem in that the trenches must be deeply formed to effectively isolate the devices.
따라서, 본 발명의 목적은 트렌치를 깊게 형성하지 않고도 소자들을 효과적으로 격리할 수 있는 반도체장치의 소자격리방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a device isolation method for a semiconductor device which can effectively isolate devices without deeply forming trenches.
상기 목적을 달성하기 위해 본 발명에 따른 반도체장치의 소자격리방법은 반도체기판 상에 버퍼산화막 및 식각정지층을 형성하고 상기 마스크층 상에 소정 부분을 노출시키는 포토레지스트 패턴을 형성하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 반도체기판이 노출되도록 식각정지층과 버퍼산화막을 패터닝하여 소자격리영역과 활성영역을 한정하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 반도체기판의 소자격리영역을 이방성 식각 특성을 갖는 가스와 등방성 식각 특성을 갖는 가스를 혼합량을 변화시키면서 다 단계 식각하여 항아리 형상의 트렌치를 형성하는 공정과, 상기 포토레지스트 패턴을 제거하고 상기 트렌치 내에 필드산화막을 형성하는 공정을 구비한다.In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes forming a buffer oxide film and an etch stop layer on a semiconductor substrate and forming a photoresist pattern exposing a predetermined portion on the mask layer; Patterning an etch stop layer and a buffer oxide film to expose the semiconductor substrate using a photoresist pattern as a mask to define an isolation region and an active region; and isolation of the device from the semiconductor substrate using the photoresist pattern as a mask Forming a jar-shaped trench by multi-step etching the region having an anisotropic etching characteristic and a gas having an isotropic etching characteristic and varying the mixing amount; and removing the photoresist pattern and forming a field oxide film in the trench. It is provided.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 소자격리방법을 도시하는 공정도1A to 1D are process diagrams illustrating a device isolation method of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정도2A to 2D are process diagrams showing a device isolation method for a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정도이다.2A to 2D are process charts showing the device isolation method of the semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(21) 상에 열산화 방법에 의해 버퍼산화막(23)을 형성하고, 이 버퍼산화막(23) 상에 CVD 방법에 의해 질화실리콘을 증착하여 식각정지층(25)을 형성한다. 식각정지층(25) 상에 포토레지스트를 도포한 후 노광 및 현상하여 포토레지스트 패턴(26)을 형성한다. 그 다음, 포토레지스트 패턴(26)을 마스크로 사용하여 반도체기판(21)의 소정 부분이 노출되도록 식각정지층(25) 및 버퍼산화막(23)을 선택적으로 제거하여 소자격리영역과 활성영역을 한정한다.Referring to FIG. 2A, a buffer oxide film 23 is formed on a semiconductor substrate 21 by a thermal oxidation method, and silicon nitride is deposited on the buffer oxide film 23 by a CVD method to etch stop layer 25. To form. After the photoresist is applied on the etch stop layer 25, the photoresist pattern 26 is formed by exposure and development. Next, using the photoresist pattern 26 as a mask, the etch stop layer 25 and the buffer oxide film 23 are selectively removed so that a predetermined portion of the semiconductor substrate 21 is exposed to define the device isolation region and the active region. do.
도 2b를 참조하면, 포토레지스트 패턴(26)을 마스크로 사용하여 반도체기판(21)의 노출된 부분을 Cl2가스와 HBr 가스의 혼합량을 변화시키면서 연속적으로 다 단계 플라즈마 식각을 진행하여 항아리 형상의 트렌치(27)를 형성한다.Referring to FIG. 2B, using the photoresist pattern 26 as a mask, the exposed portion of the semiconductor substrate 21 is continuously subjected to multi-step plasma etching while varying the mixing amount of Cl 2 gas and HBr gas to form a jar shape. The trench 27 is formed.
상기에서 반도체기판(21)은 Cl2가스에 의해 이방성으로 식각되고 HBr 가스에 의해 등방성으로 식각된다. 그러므로, 초기 단계에는 Cl2가스를 HBr 가스에 비해 많은 양을 혼합하고, 마지막 단계에는 Cl2가스를 HBr 가스에 비해 적은 양을 혼합하여 식각하여 항아리 형상의 트렌치(27)를 형성한다.The semiconductor substrate 21 is anisotropically etched by Cl 2 gas and isotropically etched by HBr gas. Therefore, in the initial stage, Cl 2 gas is mixed with a larger amount than the HBr gas, and in the final stage, Cl 2 gas is mixed with a smaller amount than the HBr gas and etched to form a jar-shaped trench 27.
즉, 항아리 형상의 트렌치(27)는 식각장치(도시되지 않음)의 소스 파워를 900∼1200W로, 바이어스 파워를 100∼200W로 조절하고, 압력을 3∼6Torr로 유지시킨 후 Cl2가스와 HBr 가스를 45∼55sccm : 15∼25sccm, 25∼35sccm : 25∼35sccm 및 5∼15sccm : 55∼65sccm으로 혼합량을 3단계 변화시켜 식각하므로써 형성된다.That is, the jar-shaped trench 27 adjusts the source power of the etching apparatus (not shown) to 900 to 1200 W, the bias power to 100 to 200 W, and maintains the pressure at 3 to 6 Torr, followed by Cl 2 gas and HBr. The gas is etched by changing the mixing amount in three steps from 45 to 55 sccm: 15 to 25 sccm, 25 to 35 sccm: 25 to 35 sccm, and 5 to 15 sccm: 55 to 65 sccm.
도 2c를 참조하면, 포토레지스트 패턴(26)을 제거한다. 그리고, 식각정지층(25) 상에 항아리 형상의 트렌치(27)가 채워지도록 산화실리콘을 CVD 방법으로 증착한다. 그리고, 산화실리콘을 식각정지층(25)이 노출되고 트렌치(27) 내에 잔류도록 RIE 방법이나 CMP 방법으로 제거한다. 이 때, 트렌치(27) 내에 잔류하는 산화실리콘은 필드산화막(29)이 된다.Referring to FIG. 2C, the photoresist pattern 26 is removed. Then, silicon oxide is deposited by the CVD method so that the jar-shaped trench 27 is filled on the etch stop layer 25. The silicon oxide is removed by the RIE method or the CMP method so that the etch stop layer 25 is exposed and remains in the trench 27. At this time, the silicon oxide remaining in the trench 27 becomes the field oxide film 29.
도 2d를 참조하면, 식각정지층(25)과 버퍼산화막(23)을 습식 식각 방법으로 제거하여 반도체기판(21)의 활성영역을 노출시킨다. 버퍼산화막(23) 제거시, 또는, 식각정지층(25)과 버퍼산화막(23) 제거 후 세정 공정시에 필드산화막(29)의 반도체기판(21) 보다 높은 부분은 제거되어 반도체기판(21)과 평탄하게 된다.Referring to FIG. 2D, the etch stop layer 25 and the buffer oxide layer 23 are removed by a wet etching method to expose the active region of the semiconductor substrate 21. When the buffer oxide film 23 is removed or the etching stop layer 25 and the buffer oxide film 23 are removed, a portion higher than the semiconductor substrate 21 of the field oxide film 29 is removed to remove the semiconductor substrate 21. And flatten.
상술한 바와 같이 반도체기판을 이방성 식각하는 Cl2가스와 등방성 식각하는 HBr 가스를 초기 단계에는 Cl2가스를 HBr 가스에 비해 많은 양을 혼합하고, 마지막 단계에는 Cl2가스를 HBr 가스에 비해 적은 양을 혼합하면서 다 단계 식각하여 항아리 형상의 트렌치를 형성하므로써 트렌치를 깊게 형성하지 않아도 소자의 이격 거리를 증가시킨다.The initial step the Cl 2 gas and the isotropic etching HBr gas for anisotropically etching a semiconductor substrate by mixing a large amount compared to the Cl 2 gas in the HBr gas, the last step as described above is less than the Cl 2 gas in the HBr gas Multi-step etching to form a jar-shaped trench to increase the separation distance of the device without having to form a deep trench.
따라서, 본 발명은 트렌치를 깊게 형성하지 않고도 소자들을 효과적으로 격리할 수 있는 잇점이 있다.Thus, the present invention has the advantage that the devices can be effectively isolated without forming the trench deeply.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970057842A KR100246197B1 (en) | 1997-11-04 | 1997-11-04 | Method for isolating semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970057842A KR100246197B1 (en) | 1997-11-04 | 1997-11-04 | Method for isolating semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990038190A true KR19990038190A (en) | 1999-06-05 |
| KR100246197B1 KR100246197B1 (en) | 2000-03-15 |
Family
ID=19524079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970057842A Expired - Fee Related KR100246197B1 (en) | 1997-11-04 | 1997-11-04 | Method for isolating semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100246197B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333378B1 (en) * | 1999-06-23 | 2002-04-18 | 박종섭 | Method of manufacturing semiconductor device |
| KR100743619B1 (en) * | 2001-06-12 | 2007-07-27 | 주식회사 하이닉스반도체 | Trench Formation Method for Semiconductor Devices |
| KR100780655B1 (en) * | 2006-06-30 | 2007-11-29 | 주식회사 하이닉스반도체 | Bulb-type recess manufacturing method of semiconductor device |
| CN122028719A (en) * | 2026-04-16 | 2026-05-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970018141A (en) * | 1995-09-14 | 1997-04-30 | 김광호 | Trench Etching Method of Silicon Substrate |
-
1997
- 1997-11-04 KR KR1019970057842A patent/KR100246197B1/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333378B1 (en) * | 1999-06-23 | 2002-04-18 | 박종섭 | Method of manufacturing semiconductor device |
| KR100743619B1 (en) * | 2001-06-12 | 2007-07-27 | 주식회사 하이닉스반도체 | Trench Formation Method for Semiconductor Devices |
| KR100780655B1 (en) * | 2006-06-30 | 2007-11-29 | 주식회사 하이닉스반도체 | Bulb-type recess manufacturing method of semiconductor device |
| CN122028719A (en) * | 2026-04-16 | 2026-05-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100246197B1 (en) | 2000-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100249025B1 (en) | Semiconductor element isolating method | |
| KR100505713B1 (en) | Shallow trench isolation and method for forming the same | |
| US6355539B1 (en) | Method for forming shallow trench isolation | |
| KR100246197B1 (en) | Method for isolating semiconductor | |
| KR100242385B1 (en) | Device isolation method of semiconductor device | |
| KR100242526B1 (en) | Method for isolating semiconductor device | |
| KR100596876B1 (en) | Device Separator Formation Method of Semiconductor Device | |
| KR100344765B1 (en) | Method for isolating semiconductor devices | |
| KR100271802B1 (en) | A mothod of isolation in semicondcutor device | |
| KR100474588B1 (en) | Device isolation method of semiconductor device | |
| KR19990070373A (en) | Device isolation method of semiconductor device | |
| KR20000019068A (en) | Method for isolating semiconductor devices | |
| KR100249023B1 (en) | Semiconductor element isolating method | |
| KR100226500B1 (en) | Device isolation method of semiconductor device | |
| KR19990048259A (en) | Device isolation method of semiconductor device | |
| KR100249026B1 (en) | Semiconductor element isolating method | |
| KR19980084107A (en) | Device isolation method of semiconductor device | |
| KR100242523B1 (en) | Device isolation method of semiconductor device | |
| KR100246198B1 (en) | Method for isolating semiconductor device | |
| KR100269623B1 (en) | A method of isolating semiconductor devices | |
| KR19990041569A (en) | Device isolation method of semiconductor device | |
| KR20000015298A (en) | Isolation method of semiconductor device | |
| KR19990039742A (en) | Device isolation method of semiconductor device | |
| KR100269603B1 (en) | Mothod of forming field oxide of semiconductor device | |
| KR19990010247A (en) | Device isolation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U11-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20061122 Year of fee payment: 8 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20071205 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20071205 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |